Overall: 2910/4541 fields covered

ADC1

0x40012400: Analog to digital converter

77/77 fields covered. Toggle Registers.

SR

status register

Offset: 0x0, reset: 0x00000000, access: read-write

5/5 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
STRT
rw
JSTRT
rw
JEOC
rw
EOC
rw
AWD
rw
Toggle Fields.

AWD

Bit 0: Analog watchdog flag.

Allowed values:
0: NoEvent: No analog watchdog event occurred
1: Event: Analog watchdog event occurred

EOC

Bit 1: Regular channel end of conversion.

Allowed values:
0: NotComplete: Conversion is not complete
1: Complete: Conversion complete

JEOC

Bit 2: Injected channel end of conversion.

Allowed values:
0: NotComplete: Conversion is not complete
1: Complete: Conversion complete

JSTRT

Bit 3: Injected channel start flag.

Allowed values:
0: NotStarted: No injected group conversion started
1: Started: Injected group conversion has started

STRT

Bit 4: Regular channel start flag.

Allowed values:
0: NotStarted: No regular channel conversion started
1: Started: Regular channel conversion has started

CR1

control register 1

Offset: 0x4, reset: 0x00000000, access: read-write

13/13 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
AWDEN
rw
JAWDEN
rw
DUALMOD
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DISCNUM
rw
JDISCEN
rw
DISCEN
rw
JAUTO
rw
AWDSGL
rw
SCAN
rw
JEOCIE
rw
AWDIE
rw
EOCIE
rw
AWDCH
rw
Toggle Fields.

AWDCH

Bits 0-4: Analog watchdog channel select bits.

Allowed values: 0-17

EOCIE

Bit 5: Interrupt enable for EOC.

Allowed values:
0: Disabled: EOC interrupt disabled
1: Enabled: EOC interrupt enabled. An interrupt is generated when the EOC bit is set

AWDIE

Bit 6: Analog watchdog interrupt enable.

Allowed values:
0: Disabled: Analog watchdog interrupt disabled
1: Enabled: Analog watchdog interrupt enabled

JEOCIE

Bit 7: Interrupt enable for injected channels.

Allowed values:
0: Disabled: JEOC interrupt disabled
1: Enabled: JEOC interrupt enabled. An interrupt is generated when the JEOC bit is set

SCAN

Bit 8: Scan mode.

Allowed values:
0: Disabled: Scan mode disabled
1: Enabled: Scan mode enabled

AWDSGL

Bit 9: Enable the watchdog on a single channel in scan mode.

Allowed values:
0: All: Analog watchdog enabled on all channels
1: Single: Analog watchdog enabled on a single channel

JAUTO

Bit 10: Automatic injected group conversion.

Allowed values:
0: Disabled: Automatic injected group conversion disabled
1: Enabled: Automatic injected group conversion enabled

DISCEN

Bit 11: Discontinuous mode on regular channels.

Allowed values:
0: Disabled: Discontinuous mode on regular channels disabled
1: Enabled: Discontinuous mode on regular channels enabled

JDISCEN

Bit 12: Discontinuous mode on injected channels.

Allowed values:
0: Disabled: Discontinuous mode on injected channels disabled
1: Enabled: Discontinuous mode on injected channels enabled

DISCNUM

Bits 13-15: Discontinuous mode channel count.

Allowed values: 0-7

DUALMOD

Bits 16-19: Dual mode selection.

Allowed values:
0: Independent: Independent mode
1: RegularInjected: Combined regular simultaneous + injected simultaneous mode
2: RegularAlternateTrigger: Combined regular simultaneous + alternate trigger mode
3: InjectedFastInterleaved: Combined injected simultaneous + fast interleaved mode
4: InjectedSlowInterleaved: Combined injected simultaneous + slow interleaved mode
5: Injected: Injected simultaneous mode only
6: Regular: Regular simultaneous mode only
7: FastInterleaved: Fast interleaved mode only
8: SlowInterleaved: Slow interleaved mode only
9: AlternateTrigger: Alternate trigger mode only

JAWDEN

Bit 22: Analog watchdog enable on injected channels.

Allowed values:
0: Disabled: Analog watchdog disabled on injected channels
1: Enabled: Analog watchdog enabled on injected channels

AWDEN

Bit 23: Analog watchdog enable on regular channels.

Allowed values:
0: Disabled: Analog watchdog disabled on regular channels
1: Enabled: Analog watchdog enabled on regular channels

CR2

control register 2

Offset: 0x8, reset: 0x00000000, access: read-write

13/13 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
TSVREFE
rw
SWSTART
rw
JSWSTART
rw
EXTTRIG
rw
EXTSEL
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
JEXTTRIG
rw
JEXTSEL
rw
ALIGN
rw
DMA
rw
RSTCAL
rw
CAL
rw
CONT
rw
ADON
rw
Toggle Fields.

ADON

Bit 0: A/D converter ON / OFF.

Allowed values:
0: Disabled: Disable ADC conversion/calibration and go to power down mode
1: Enabled: Enable ADC and to start conversion

CONT

Bit 1: Continuous conversion.

Allowed values:
0: Single: Single conversion mode
1: Continuous: Continuous conversion mode

CAL

Bit 2: A/D calibration.

Allowed values:
0: Complete: Calibration completed
1: NotComplete: Calibrating

RSTCAL

Bit 3: Reset calibration.

Allowed values:
0: Initialized: Calibration register initialized
1: NotInitialized: Initializing calibration register

DMA

Bit 8: Direct memory access mode.

Allowed values:
0: Disabled: DMA mode disabled
1: Enabled: DMA mode enabled

ALIGN

Bit 11: Data alignment.

Allowed values:
0: Right: Right Alignment
1: Left: Left Alignment

JEXTSEL

Bits 12-14: External event select for injected group.

Allowed values:
0: Tim1Trgo: Timer 1 TRGO event
1: Tim1Cc4: Timer 1 CC4 event
2: Tim2Trgo: Timer 2 TRGO event
3: Tim2Cc1: Timer 2 CC1 event
4: Tim3Cc4: Timer 3 CC4 event
5: Tim4Trgo: Timer 4 TRGO event
6: Exti15: EXTI line15/TIM8_CC4 event (TIM8_CC4 is available only in high-density and XL-density devices)
7: Jswstart: JSWSTART

JEXTTRIG

Bit 15: External trigger conversion mode for injected channels.

Allowed values:
0: Disabled: Conversion on external event disabled
1: Enabled: Conversion on external event enabled

EXTSEL

Bits 17-19: External event select for regular group.

Allowed values:
0: Tim1Cc1: Timer 1 CC1 event
1: Tim1Cc2: Timer 1 CC2 event
2: Tim1Cc3: Timer 1 CC3 event
3: Tim2Cc2: Timer 2 CC2 event
4: Tim3Trgo: Timer 3 TRGO event
5: Tim4Cc4: Timer 4 CC4 event
6: Exti11: EXTI line 11/TIM8_TRGO event (TIM8_TRGO is available only in high-density and XL-density devices)
7: Swstart: SWSTART

EXTTRIG

Bit 20: External trigger conversion mode for regular channels.

Allowed values:
0: Disabled: Conversion on external event disabled
1: Enabled: Conversion on external event enabled

JSWSTART

Bit 21: Start conversion of injected channels.

Allowed values:
0: Started: Reset state
1: NotStarted: Starting conversion of injected channels

SWSTART

Bit 22: Start conversion of regular channels.

Allowed values:
0: Started: Reset state
1: NotStarted: Starting conversion of regular channels

TSVREFE

Bit 23: Temperature sensor and VREFINT enable.

Allowed values:
0: Disabled: Temperature sensor and V_REFINT channel disabled
1: Enabled: Temperature sensor and V_REFINT channel enabled

SMPR1

sample time register 1

Offset: 0xC, reset: 0x00000000, access: read-write

8/8 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
SMP17
rw
SMP16
rw
SMP15
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SMP15
rw
SMP14
rw
SMP13
rw
SMP12
rw
SMP11
rw
SMP10
rw
Toggle Fields.

SMP10

Bits 0-2: Channel 10 sample time selection.

Allowed values:
0: Cycles1_5: 1.5 ADC clock cycles
1: Cycles7_5: 7.5 ADC clock cycles
2: Cycles13_5: 13.5 ADC clock cycles
3: Cycles28_5: 28.5 ADC clock cycles
4: Cycles41_5: 41.5 ADC clock cycles
5: Cycles55_5: 55.5 ADC clock cycles
6: Cycles71_5: 71.5 ADC clock cycles
7: Cycles239_5: 239.5 ADC clock cycles

SMP11

Bits 3-5: Channel 11 sample time selection.

Allowed values:
0: Cycles1_5: 1.5 ADC clock cycles
1: Cycles7_5: 7.5 ADC clock cycles
2: Cycles13_5: 13.5 ADC clock cycles
3: Cycles28_5: 28.5 ADC clock cycles
4: Cycles41_5: 41.5 ADC clock cycles
5: Cycles55_5: 55.5 ADC clock cycles
6: Cycles71_5: 71.5 ADC clock cycles
7: Cycles239_5: 239.5 ADC clock cycles

SMP12

Bits 6-8: Channel 12 sample time selection.

Allowed values:
0: Cycles1_5: 1.5 ADC clock cycles
1: Cycles7_5: 7.5 ADC clock cycles
2: Cycles13_5: 13.5 ADC clock cycles
3: Cycles28_5: 28.5 ADC clock cycles
4: Cycles41_5: 41.5 ADC clock cycles
5: Cycles55_5: 55.5 ADC clock cycles
6: Cycles71_5: 71.5 ADC clock cycles
7: Cycles239_5: 239.5 ADC clock cycles

SMP13

Bits 9-11: Channel 13 sample time selection.

Allowed values:
0: Cycles1_5: 1.5 ADC clock cycles
1: Cycles7_5: 7.5 ADC clock cycles
2: Cycles13_5: 13.5 ADC clock cycles
3: Cycles28_5: 28.5 ADC clock cycles
4: Cycles41_5: 41.5 ADC clock cycles
5: Cycles55_5: 55.5 ADC clock cycles
6: Cycles71_5: 71.5 ADC clock cycles
7: Cycles239_5: 239.5 ADC clock cycles

SMP14

Bits 12-14: Channel 14 sample time selection.

Allowed values:
0: Cycles1_5: 1.5 ADC clock cycles
1: Cycles7_5: 7.5 ADC clock cycles
2: Cycles13_5: 13.5 ADC clock cycles
3: Cycles28_5: 28.5 ADC clock cycles
4: Cycles41_5: 41.5 ADC clock cycles
5: Cycles55_5: 55.5 ADC clock cycles
6: Cycles71_5: 71.5 ADC clock cycles
7: Cycles239_5: 239.5 ADC clock cycles

SMP15

Bits 15-17: Channel 15 sample time selection.

Allowed values:
0: Cycles1_5: 1.5 ADC clock cycles
1: Cycles7_5: 7.5 ADC clock cycles
2: Cycles13_5: 13.5 ADC clock cycles
3: Cycles28_5: 28.5 ADC clock cycles
4: Cycles41_5: 41.5 ADC clock cycles
5: Cycles55_5: 55.5 ADC clock cycles
6: Cycles71_5: 71.5 ADC clock cycles
7: Cycles239_5: 239.5 ADC clock cycles

SMP16

Bits 18-20: Channel 16 sample time selection.

Allowed values:
0: Cycles1_5: 1.5 ADC clock cycles
1: Cycles7_5: 7.5 ADC clock cycles
2: Cycles13_5: 13.5 ADC clock cycles
3: Cycles28_5: 28.5 ADC clock cycles
4: Cycles41_5: 41.5 ADC clock cycles
5: Cycles55_5: 55.5 ADC clock cycles
6: Cycles71_5: 71.5 ADC clock cycles
7: Cycles239_5: 239.5 ADC clock cycles

SMP17

Bits 21-23: Channel 17 sample time selection.

Allowed values:
0: Cycles1_5: 1.5 ADC clock cycles
1: Cycles7_5: 7.5 ADC clock cycles
2: Cycles13_5: 13.5 ADC clock cycles
3: Cycles28_5: 28.5 ADC clock cycles
4: Cycles41_5: 41.5 ADC clock cycles
5: Cycles55_5: 55.5 ADC clock cycles
6: Cycles71_5: 71.5 ADC clock cycles
7: Cycles239_5: 239.5 ADC clock cycles

SMPR2

sample time register 2

Offset: 0x10, reset: 0x00000000, access: read-write

10/10 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
SMP9
rw
SMP8
rw
SMP7
rw
SMP6
rw
SMP5
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SMP5
rw
SMP4
rw
SMP3
rw
SMP2
rw
SMP1
rw
SMP0
rw
Toggle Fields.

SMP0

Bits 0-2: Channel 0 sample time selection.

Allowed values:
0: Cycles1_5: 1.5 ADC clock cycles
1: Cycles7_5: 7.5 ADC clock cycles
2: Cycles13_5: 13.5 ADC clock cycles
3: Cycles28_5: 28.5 ADC clock cycles
4: Cycles41_5: 41.5 ADC clock cycles
5: Cycles55_5: 55.5 ADC clock cycles
6: Cycles71_5: 71.5 ADC clock cycles
7: Cycles239_5: 239.5 ADC clock cycles

SMP1

Bits 3-5: Channel 1 sample time selection.

Allowed values:
0: Cycles1_5: 1.5 ADC clock cycles
1: Cycles7_5: 7.5 ADC clock cycles
2: Cycles13_5: 13.5 ADC clock cycles
3: Cycles28_5: 28.5 ADC clock cycles
4: Cycles41_5: 41.5 ADC clock cycles
5: Cycles55_5: 55.5 ADC clock cycles
6: Cycles71_5: 71.5 ADC clock cycles
7: Cycles239_5: 239.5 ADC clock cycles

SMP2

Bits 6-8: Channel 2 sample time selection.

Allowed values:
0: Cycles1_5: 1.5 ADC clock cycles
1: Cycles7_5: 7.5 ADC clock cycles
2: Cycles13_5: 13.5 ADC clock cycles
3: Cycles28_5: 28.5 ADC clock cycles
4: Cycles41_5: 41.5 ADC clock cycles
5: Cycles55_5: 55.5 ADC clock cycles
6: Cycles71_5: 71.5 ADC clock cycles
7: Cycles239_5: 239.5 ADC clock cycles

SMP3

Bits 9-11: Channel 3 sample time selection.

Allowed values:
0: Cycles1_5: 1.5 ADC clock cycles
1: Cycles7_5: 7.5 ADC clock cycles
2: Cycles13_5: 13.5 ADC clock cycles
3: Cycles28_5: 28.5 ADC clock cycles
4: Cycles41_5: 41.5 ADC clock cycles
5: Cycles55_5: 55.5 ADC clock cycles
6: Cycles71_5: 71.5 ADC clock cycles
7: Cycles239_5: 239.5 ADC clock cycles

SMP4

Bits 12-14: Channel 4 sample time selection.

Allowed values:
0: Cycles1_5: 1.5 ADC clock cycles
1: Cycles7_5: 7.5 ADC clock cycles
2: Cycles13_5: 13.5 ADC clock cycles
3: Cycles28_5: 28.5 ADC clock cycles
4: Cycles41_5: 41.5 ADC clock cycles
5: Cycles55_5: 55.5 ADC clock cycles
6: Cycles71_5: 71.5 ADC clock cycles
7: Cycles239_5: 239.5 ADC clock cycles

SMP5

Bits 15-17: Channel 5 sample time selection.

Allowed values:
0: Cycles1_5: 1.5 ADC clock cycles
1: Cycles7_5: 7.5 ADC clock cycles
2: Cycles13_5: 13.5 ADC clock cycles
3: Cycles28_5: 28.5 ADC clock cycles
4: Cycles41_5: 41.5 ADC clock cycles
5: Cycles55_5: 55.5 ADC clock cycles
6: Cycles71_5: 71.5 ADC clock cycles
7: Cycles239_5: 239.5 ADC clock cycles

SMP6

Bits 18-20: Channel 6 sample time selection.

Allowed values:
0: Cycles1_5: 1.5 ADC clock cycles
1: Cycles7_5: 7.5 ADC clock cycles
2: Cycles13_5: 13.5 ADC clock cycles
3: Cycles28_5: 28.5 ADC clock cycles
4: Cycles41_5: 41.5 ADC clock cycles
5: Cycles55_5: 55.5 ADC clock cycles
6: Cycles71_5: 71.5 ADC clock cycles
7: Cycles239_5: 239.5 ADC clock cycles

SMP7

Bits 21-23: Channel 7 sample time selection.

Allowed values:
0: Cycles1_5: 1.5 ADC clock cycles
1: Cycles7_5: 7.5 ADC clock cycles
2: Cycles13_5: 13.5 ADC clock cycles
3: Cycles28_5: 28.5 ADC clock cycles
4: Cycles41_5: 41.5 ADC clock cycles
5: Cycles55_5: 55.5 ADC clock cycles
6: Cycles71_5: 71.5 ADC clock cycles
7: Cycles239_5: 239.5 ADC clock cycles

SMP8

Bits 24-26: Channel 8 sample time selection.

Allowed values:
0: Cycles1_5: 1.5 ADC clock cycles
1: Cycles7_5: 7.5 ADC clock cycles
2: Cycles13_5: 13.5 ADC clock cycles
3: Cycles28_5: 28.5 ADC clock cycles
4: Cycles41_5: 41.5 ADC clock cycles
5: Cycles55_5: 55.5 ADC clock cycles
6: Cycles71_5: 71.5 ADC clock cycles
7: Cycles239_5: 239.5 ADC clock cycles

SMP9

Bits 27-29: Channel 9 sample time selection.

Allowed values:
0: Cycles1_5: 1.5 ADC clock cycles
1: Cycles7_5: 7.5 ADC clock cycles
2: Cycles13_5: 13.5 ADC clock cycles
3: Cycles28_5: 28.5 ADC clock cycles
4: Cycles41_5: 41.5 ADC clock cycles
5: Cycles55_5: 55.5 ADC clock cycles
6: Cycles71_5: 71.5 ADC clock cycles
7: Cycles239_5: 239.5 ADC clock cycles

JOFR%s

injected channel data offset register x

Offset: 0x14, reset: 0x00000000, access: read-write

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
JOFFSET
rw
Toggle Fields.

JOFFSET

Bits 0-11: Data offset for injected channel x.

Allowed values: 0-4095

HTR

watchdog higher threshold register

Offset: 0x24, reset: 0x00000FFF, access: read-write

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
HT
rw
Toggle Fields.

HT

Bits 0-11: Analog watchdog higher threshold.

Allowed values: 0-4095

LTR

watchdog lower threshold register

Offset: 0x28, reset: 0x00000000, access: read-write

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LT
rw
Toggle Fields.

LT

Bits 0-11: Analog watchdog lower threshold.

Allowed values: 0-4095

SQR1

regular sequence register 1

Offset: 0x2C, reset: 0x00000000, access: read-write

5/5 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
L
rw
SQ16
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SQ16
rw
SQ15
rw
SQ14
rw
SQ13
rw
Toggle Fields.

SQ13

Bits 0-4: 13th conversion in regular sequence.

Allowed values: 0-17

SQ14

Bits 5-9: 14th conversion in regular sequence.

Allowed values: 0-17

SQ15

Bits 10-14: 15th conversion in regular sequence.

Allowed values: 0-17

SQ16

Bits 15-19: 16th conversion in regular sequence.

Allowed values: 0-17

L

Bits 20-23: Regular channel sequence length.

Allowed values: 0-15

SQR2

regular sequence register 2

Offset: 0x30, reset: 0x00000000, access: read-write

6/6 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
SQ12
rw
SQ11
rw
SQ10
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SQ10
rw
SQ9
rw
SQ8
rw
SQ7
rw
Toggle Fields.

SQ7

Bits 0-4: 7th conversion in regular sequence.

Allowed values: 0-17

SQ8

Bits 5-9: 8th conversion in regular sequence.

Allowed values: 0-17

SQ9

Bits 10-14: 9th conversion in regular sequence.

Allowed values: 0-17

SQ10

Bits 15-19: 10th conversion in regular sequence.

Allowed values: 0-17

SQ11

Bits 20-24: 11th conversion in regular sequence.

Allowed values: 0-17

SQ12

Bits 25-29: 12th conversion in regular sequence.

Allowed values: 0-17

SQR3

regular sequence register 3

Offset: 0x34, reset: 0x00000000, access: read-write

6/6 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
SQ6
rw
SQ5
rw
SQ4
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SQ4
rw
SQ3
rw
SQ2
rw
SQ1
rw
Toggle Fields.

SQ1

Bits 0-4: 1st conversion in regular sequence.

Allowed values: 0-17

SQ2

Bits 5-9: 2nd conversion in regular sequence.

Allowed values: 0-17

SQ3

Bits 10-14: 3rd conversion in regular sequence.

Allowed values: 0-17

SQ4

Bits 15-19: 4th conversion in regular sequence.

Allowed values: 0-17

SQ5

Bits 20-24: 5th conversion in regular sequence.

Allowed values: 0-17

SQ6

Bits 25-29: 6th conversion in regular sequence.

Allowed values: 0-17

JSQR

injected sequence register

Offset: 0x38, reset: 0x00000000, access: read-write

5/5 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
JL
rw
JSQ4
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
JSQ4
rw
JSQ3
rw
JSQ2
rw
JSQ1
rw
Toggle Fields.

JSQ1

Bits 0-4: 1st conversion in injected sequence.

Allowed values: 0-17

JSQ2

Bits 5-9: 2nd conversion in injected sequence.

Allowed values: 0-17

JSQ3

Bits 10-14: 3rd conversion in injected sequence.

Allowed values: 0-17

JSQ4

Bits 15-19: 4th conversion in injected sequence.

Allowed values: 0-17

JL

Bits 20-21: Injected sequence length.

Allowed values: 0-3

JDR%s

injected data register x

Offset: 0x3C, reset: 0x00000000, access: read-only

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
JDATA
r
Toggle Fields.

JDATA

Bits 0-15: Injected data.

DR

regular data register

Offset: 0x4C, reset: 0x00000000, access: read-only

2/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
ADC2DATA
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DATA
r
Toggle Fields.

DATA

Bits 0-15: Regular data.

ADC2DATA

Bits 16-31: ADC2 data.

ADC2

0x40012800: Analog to digital converter

74/75 fields covered. Toggle Registers.

SR

status register

Offset: 0x0, reset: 0x00000000, access: read-write

5/5 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
STRT
rw
JSTRT
rw
JEOC
rw
EOC
rw
AWD
rw
Toggle Fields.

AWD

Bit 0: Analog watchdog flag.

Allowed values:
0: NoEvent: No analog watchdog event occurred
1: Event: Analog watchdog event occurred

EOC

Bit 1: Regular channel end of conversion.

Allowed values:
0: NotComplete: Conversion is not complete
1: Complete: Conversion complete

JEOC

Bit 2: Injected channel end of conversion.

Allowed values:
0: NotComplete: Conversion is not complete
1: Complete: Conversion complete

JSTRT

Bit 3: Injected channel start flag.

Allowed values:
0: NotStarted: No injected group conversion started
1: Started: Injected group conversion has started

STRT

Bit 4: Regular channel start flag.

Allowed values:
0: NotStarted: No regular channel conversion started
1: Started: Regular channel conversion has started

CR1

control register 1

Offset: 0x4, reset: 0x00000000, access: read-write

12/12 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
AWDEN
rw
JAWDEN
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DISCNUM
rw
JDISCEN
rw
DISCEN
rw
JAUTO
rw
AWDSGL
rw
SCAN
rw
JEOCIE
rw
AWDIE
rw
EOCIE
rw
AWDCH
rw
Toggle Fields.

AWDCH

Bits 0-4: Analog watchdog channel select bits.

Allowed values: 0-17

EOCIE

Bit 5: Interrupt enable for EOC.

Allowed values:
0: Disabled: EOC interrupt disabled
1: Enabled: EOC interrupt enabled. An interrupt is generated when the EOC bit is set

AWDIE

Bit 6: Analog watchdog interrupt enable.

Allowed values:
0: Disabled: Analog watchdog interrupt disabled
1: Enabled: Analog watchdog interrupt enabled

JEOCIE

Bit 7: Interrupt enable for injected channels.

Allowed values:
0: Disabled: JEOC interrupt disabled
1: Enabled: JEOC interrupt enabled. An interrupt is generated when the JEOC bit is set

SCAN

Bit 8: Scan mode.

Allowed values:
0: Disabled: Scan mode disabled
1: Enabled: Scan mode enabled

AWDSGL

Bit 9: Enable the watchdog on a single channel in scan mode.

Allowed values:
0: All: Analog watchdog enabled on all channels
1: Single: Analog watchdog enabled on a single channel

JAUTO

Bit 10: Automatic injected group conversion.

Allowed values:
0: Disabled: Automatic injected group conversion disabled
1: Enabled: Automatic injected group conversion enabled

DISCEN

Bit 11: Discontinuous mode on regular channels.

Allowed values:
0: Disabled: Discontinuous mode on regular channels disabled
1: Enabled: Discontinuous mode on regular channels enabled

JDISCEN

Bit 12: Discontinuous mode on injected channels.

Allowed values:
0: Disabled: Discontinuous mode on injected channels disabled
1: Enabled: Discontinuous mode on injected channels enabled

DISCNUM

Bits 13-15: Discontinuous mode channel count.

Allowed values: 0-7

JAWDEN

Bit 22: Analog watchdog enable on injected channels.

Allowed values:
0: Disabled: Analog watchdog disabled on injected channels
1: Enabled: Analog watchdog enabled on injected channels

AWDEN

Bit 23: Analog watchdog enable on regular channels.

Allowed values:
0: Disabled: Analog watchdog disabled on regular channels
1: Enabled: Analog watchdog enabled on regular channels

CR2

control register 2

Offset: 0x8, reset: 0x00000000, access: read-write

12/13 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
TSVREFE
rw
SWSTART
rw
JSWSTART
rw
EXTTRIG
rw
EXTSEL
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
JEXTTRIG
rw
JEXTSEL
rw
ALIGN
rw
DMA
rw
RSTCAL
rw
CAL
rw
CONT
rw
ADON
rw
Toggle Fields.

ADON

Bit 0: A/D converter ON / OFF.

Allowed values:
0: Disabled: Disable ADC conversion/calibration and go to power down mode
1: Enabled: Enable ADC and to start conversion

CONT

Bit 1: Continuous conversion.

Allowed values:
0: Single: Single conversion mode
1: Continuous: Continuous conversion mode

CAL

Bit 2: A/D calibration.

Allowed values:
0: Complete: Calibration completed
1: NotComplete: Calibrating

RSTCAL

Bit 3: Reset calibration.

Allowed values:
0: Initialized: Calibration register initialized
1: NotInitialized: Initializing calibration register

DMA

Bit 8: Direct memory access mode.

ALIGN

Bit 11: Data alignment.

Allowed values:
0: Right: Right Alignment
1: Left: Left Alignment

JEXTSEL

Bits 12-14: External event select for injected group.

Allowed values:
0: Tim1Trgo: Timer 1 TRGO event
1: Tim1Cc4: Timer 1 CC4 event
2: Tim2Trgo: Timer 2 TRGO event
3: Tim2Cc1: Timer 2 CC1 event
4: Tim3Cc4: Timer 3 CC4 event
5: Tim4Trgo: Timer 4 TRGO event
6: Exti15: EXTI line15/TIM8_CC4 event (TIM8_CC4 is available only in high-density and XL-density devices)
7: Jswstart: JSWSTART

JEXTTRIG

Bit 15: External trigger conversion mode for injected channels.

Allowed values:
0: Disabled: Conversion on external event disabled
1: Enabled: Conversion on external event enabled

EXTSEL

Bits 17-19: External event select for regular group.

Allowed values:
0: Tim1Cc1: Timer 1 CC1 event
1: Tim1Cc2: Timer 1 CC2 event
2: Tim1Cc3: Timer 1 CC3 event
3: Tim2Cc2: Timer 2 CC2 event
4: Tim3Trgo: Timer 3 TRGO event
5: Tim4Cc4: Timer 4 CC4 event
6: Exti11: EXTI line 11/TIM8_TRGO event (TIM8_TRGO is available only in high-density and XL-density devices)
7: Swstart: SWSTART

EXTTRIG

Bit 20: External trigger conversion mode for regular channels.

Allowed values:
0: Disabled: Conversion on external event disabled
1: Enabled: Conversion on external event enabled

JSWSTART

Bit 21: Start conversion of injected channels.

Allowed values:
0: Started: Reset state
1: NotStarted: Starting conversion of injected channels

SWSTART

Bit 22: Start conversion of regular channels.

Allowed values:
0: Started: Reset state
1: NotStarted: Starting conversion of regular channels

TSVREFE

Bit 23: Temperature sensor and VREFINT enable.

Allowed values:
0: Disabled: Temperature sensor and V_REFINT channel disabled
1: Enabled: Temperature sensor and V_REFINT channel enabled

SMPR1

sample time register 1

Offset: 0xC, reset: 0x00000000, access: read-write

8/8 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
SMP17
rw
SMP16
rw
SMP15
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SMP15
rw
SMP14
rw
SMP13
rw
SMP12
rw
SMP11
rw
SMP10
rw
Toggle Fields.

SMP10

Bits 0-2: Channel 10 sample time selection.

Allowed values:
0: Cycles1_5: 1.5 ADC clock cycles
1: Cycles7_5: 7.5 ADC clock cycles
2: Cycles13_5: 13.5 ADC clock cycles
3: Cycles28_5: 28.5 ADC clock cycles
4: Cycles41_5: 41.5 ADC clock cycles
5: Cycles55_5: 55.5 ADC clock cycles
6: Cycles71_5: 71.5 ADC clock cycles
7: Cycles239_5: 239.5 ADC clock cycles

SMP11

Bits 3-5: Channel 11 sample time selection.

Allowed values:
0: Cycles1_5: 1.5 ADC clock cycles
1: Cycles7_5: 7.5 ADC clock cycles
2: Cycles13_5: 13.5 ADC clock cycles
3: Cycles28_5: 28.5 ADC clock cycles
4: Cycles41_5: 41.5 ADC clock cycles
5: Cycles55_5: 55.5 ADC clock cycles
6: Cycles71_5: 71.5 ADC clock cycles
7: Cycles239_5: 239.5 ADC clock cycles

SMP12

Bits 6-8: Channel 12 sample time selection.

Allowed values:
0: Cycles1_5: 1.5 ADC clock cycles
1: Cycles7_5: 7.5 ADC clock cycles
2: Cycles13_5: 13.5 ADC clock cycles
3: Cycles28_5: 28.5 ADC clock cycles
4: Cycles41_5: 41.5 ADC clock cycles
5: Cycles55_5: 55.5 ADC clock cycles
6: Cycles71_5: 71.5 ADC clock cycles
7: Cycles239_5: 239.5 ADC clock cycles

SMP13

Bits 9-11: Channel 13 sample time selection.

Allowed values:
0: Cycles1_5: 1.5 ADC clock cycles
1: Cycles7_5: 7.5 ADC clock cycles
2: Cycles13_5: 13.5 ADC clock cycles
3: Cycles28_5: 28.5 ADC clock cycles
4: Cycles41_5: 41.5 ADC clock cycles
5: Cycles55_5: 55.5 ADC clock cycles
6: Cycles71_5: 71.5 ADC clock cycles
7: Cycles239_5: 239.5 ADC clock cycles

SMP14

Bits 12-14: Channel 14 sample time selection.

Allowed values:
0: Cycles1_5: 1.5 ADC clock cycles
1: Cycles7_5: 7.5 ADC clock cycles
2: Cycles13_5: 13.5 ADC clock cycles
3: Cycles28_5: 28.5 ADC clock cycles
4: Cycles41_5: 41.5 ADC clock cycles
5: Cycles55_5: 55.5 ADC clock cycles
6: Cycles71_5: 71.5 ADC clock cycles
7: Cycles239_5: 239.5 ADC clock cycles

SMP15

Bits 15-17: Channel 15 sample time selection.

Allowed values:
0: Cycles1_5: 1.5 ADC clock cycles
1: Cycles7_5: 7.5 ADC clock cycles
2: Cycles13_5: 13.5 ADC clock cycles
3: Cycles28_5: 28.5 ADC clock cycles
4: Cycles41_5: 41.5 ADC clock cycles
5: Cycles55_5: 55.5 ADC clock cycles
6: Cycles71_5: 71.5 ADC clock cycles
7: Cycles239_5: 239.5 ADC clock cycles

SMP16

Bits 18-20: Channel 16 sample time selection.

Allowed values:
0: Cycles1_5: 1.5 ADC clock cycles
1: Cycles7_5: 7.5 ADC clock cycles
2: Cycles13_5: 13.5 ADC clock cycles
3: Cycles28_5: 28.5 ADC clock cycles
4: Cycles41_5: 41.5 ADC clock cycles
5: Cycles55_5: 55.5 ADC clock cycles
6: Cycles71_5: 71.5 ADC clock cycles
7: Cycles239_5: 239.5 ADC clock cycles

SMP17

Bits 21-23: Channel 17 sample time selection.

Allowed values:
0: Cycles1_5: 1.5 ADC clock cycles
1: Cycles7_5: 7.5 ADC clock cycles
2: Cycles13_5: 13.5 ADC clock cycles
3: Cycles28_5: 28.5 ADC clock cycles
4: Cycles41_5: 41.5 ADC clock cycles
5: Cycles55_5: 55.5 ADC clock cycles
6: Cycles71_5: 71.5 ADC clock cycles
7: Cycles239_5: 239.5 ADC clock cycles

SMPR2

sample time register 2

Offset: 0x10, reset: 0x00000000, access: read-write

10/10 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
SMP9
rw
SMP8
rw
SMP7
rw
SMP6
rw
SMP5
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SMP5
rw
SMP4
rw
SMP3
rw
SMP2
rw
SMP1
rw
SMP0
rw
Toggle Fields.

SMP0

Bits 0-2: Channel 0 sample time selection.

Allowed values:
0: Cycles1_5: 1.5 ADC clock cycles
1: Cycles7_5: 7.5 ADC clock cycles
2: Cycles13_5: 13.5 ADC clock cycles
3: Cycles28_5: 28.5 ADC clock cycles
4: Cycles41_5: 41.5 ADC clock cycles
5: Cycles55_5: 55.5 ADC clock cycles
6: Cycles71_5: 71.5 ADC clock cycles
7: Cycles239_5: 239.5 ADC clock cycles

SMP1

Bits 3-5: Channel 1 sample time selection.

Allowed values:
0: Cycles1_5: 1.5 ADC clock cycles
1: Cycles7_5: 7.5 ADC clock cycles
2: Cycles13_5: 13.5 ADC clock cycles
3: Cycles28_5: 28.5 ADC clock cycles
4: Cycles41_5: 41.5 ADC clock cycles
5: Cycles55_5: 55.5 ADC clock cycles
6: Cycles71_5: 71.5 ADC clock cycles
7: Cycles239_5: 239.5 ADC clock cycles

SMP2

Bits 6-8: Channel 2 sample time selection.

Allowed values:
0: Cycles1_5: 1.5 ADC clock cycles
1: Cycles7_5: 7.5 ADC clock cycles
2: Cycles13_5: 13.5 ADC clock cycles
3: Cycles28_5: 28.5 ADC clock cycles
4: Cycles41_5: 41.5 ADC clock cycles
5: Cycles55_5: 55.5 ADC clock cycles
6: Cycles71_5: 71.5 ADC clock cycles
7: Cycles239_5: 239.5 ADC clock cycles

SMP3

Bits 9-11: Channel 3 sample time selection.

Allowed values:
0: Cycles1_5: 1.5 ADC clock cycles
1: Cycles7_5: 7.5 ADC clock cycles
2: Cycles13_5: 13.5 ADC clock cycles
3: Cycles28_5: 28.5 ADC clock cycles
4: Cycles41_5: 41.5 ADC clock cycles
5: Cycles55_5: 55.5 ADC clock cycles
6: Cycles71_5: 71.5 ADC clock cycles
7: Cycles239_5: 239.5 ADC clock cycles

SMP4

Bits 12-14: Channel 4 sample time selection.

Allowed values:
0: Cycles1_5: 1.5 ADC clock cycles
1: Cycles7_5: 7.5 ADC clock cycles
2: Cycles13_5: 13.5 ADC clock cycles
3: Cycles28_5: 28.5 ADC clock cycles
4: Cycles41_5: 41.5 ADC clock cycles
5: Cycles55_5: 55.5 ADC clock cycles
6: Cycles71_5: 71.5 ADC clock cycles
7: Cycles239_5: 239.5 ADC clock cycles

SMP5

Bits 15-17: Channel 5 sample time selection.

Allowed values:
0: Cycles1_5: 1.5 ADC clock cycles
1: Cycles7_5: 7.5 ADC clock cycles
2: Cycles13_5: 13.5 ADC clock cycles
3: Cycles28_5: 28.5 ADC clock cycles
4: Cycles41_5: 41.5 ADC clock cycles
5: Cycles55_5: 55.5 ADC clock cycles
6: Cycles71_5: 71.5 ADC clock cycles
7: Cycles239_5: 239.5 ADC clock cycles

SMP6

Bits 18-20: Channel 6 sample time selection.

Allowed values:
0: Cycles1_5: 1.5 ADC clock cycles
1: Cycles7_5: 7.5 ADC clock cycles
2: Cycles13_5: 13.5 ADC clock cycles
3: Cycles28_5: 28.5 ADC clock cycles
4: Cycles41_5: 41.5 ADC clock cycles
5: Cycles55_5: 55.5 ADC clock cycles
6: Cycles71_5: 71.5 ADC clock cycles
7: Cycles239_5: 239.5 ADC clock cycles

SMP7

Bits 21-23: Channel 7 sample time selection.

Allowed values:
0: Cycles1_5: 1.5 ADC clock cycles
1: Cycles7_5: 7.5 ADC clock cycles
2: Cycles13_5: 13.5 ADC clock cycles
3: Cycles28_5: 28.5 ADC clock cycles
4: Cycles41_5: 41.5 ADC clock cycles
5: Cycles55_5: 55.5 ADC clock cycles
6: Cycles71_5: 71.5 ADC clock cycles
7: Cycles239_5: 239.5 ADC clock cycles

SMP8

Bits 24-26: Channel 8 sample time selection.

Allowed values:
0: Cycles1_5: 1.5 ADC clock cycles
1: Cycles7_5: 7.5 ADC clock cycles
2: Cycles13_5: 13.5 ADC clock cycles
3: Cycles28_5: 28.5 ADC clock cycles
4: Cycles41_5: 41.5 ADC clock cycles
5: Cycles55_5: 55.5 ADC clock cycles
6: Cycles71_5: 71.5 ADC clock cycles
7: Cycles239_5: 239.5 ADC clock cycles

SMP9

Bits 27-29: Channel 9 sample time selection.

Allowed values:
0: Cycles1_5: 1.5 ADC clock cycles
1: Cycles7_5: 7.5 ADC clock cycles
2: Cycles13_5: 13.5 ADC clock cycles
3: Cycles28_5: 28.5 ADC clock cycles
4: Cycles41_5: 41.5 ADC clock cycles
5: Cycles55_5: 55.5 ADC clock cycles
6: Cycles71_5: 71.5 ADC clock cycles
7: Cycles239_5: 239.5 ADC clock cycles

JOFR%s

injected channel data offset register x

Offset: 0x14, reset: 0x00000000, access: read-write

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
JOFFSET
rw
Toggle Fields.

JOFFSET

Bits 0-11: Data offset for injected channel x.

Allowed values: 0-4095

HTR

watchdog higher threshold register

Offset: 0x24, reset: 0x00000FFF, access: read-write

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
HT
rw
Toggle Fields.

HT

Bits 0-11: Analog watchdog higher threshold.

Allowed values: 0-4095

LTR

watchdog lower threshold register

Offset: 0x28, reset: 0x00000000, access: read-write

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LT
rw
Toggle Fields.

LT

Bits 0-11: Analog watchdog lower threshold.

Allowed values: 0-4095

SQR1

regular sequence register 1

Offset: 0x2C, reset: 0x00000000, access: read-write

5/5 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
L
rw
SQ16
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SQ16
rw
SQ15
rw
SQ14
rw
SQ13
rw
Toggle Fields.

SQ13

Bits 0-4: 13th conversion in regular sequence.

Allowed values: 0-17

SQ14

Bits 5-9: 14th conversion in regular sequence.

Allowed values: 0-17

SQ15

Bits 10-14: 15th conversion in regular sequence.

Allowed values: 0-17

SQ16

Bits 15-19: 16th conversion in regular sequence.

Allowed values: 0-17

L

Bits 20-23: Regular channel sequence length.

Allowed values: 0-15

SQR2

regular sequence register 2

Offset: 0x30, reset: 0x00000000, access: read-write

6/6 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
SQ12
rw
SQ11
rw
SQ10
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SQ10
rw
SQ9
rw
SQ8
rw
SQ7
rw
Toggle Fields.

SQ7

Bits 0-4: 7th conversion in regular sequence.

Allowed values: 0-17

SQ8

Bits 5-9: 8th conversion in regular sequence.

Allowed values: 0-17

SQ9

Bits 10-14: 9th conversion in regular sequence.

Allowed values: 0-17

SQ10

Bits 15-19: 10th conversion in regular sequence.

Allowed values: 0-17

SQ11

Bits 20-24: 11th conversion in regular sequence.

Allowed values: 0-17

SQ12

Bits 25-29: 12th conversion in regular sequence.

Allowed values: 0-17

SQR3

regular sequence register 3

Offset: 0x34, reset: 0x00000000, access: read-write

6/6 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
SQ6
rw
SQ5
rw
SQ4
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SQ4
rw
SQ3
rw
SQ2
rw
SQ1
rw
Toggle Fields.

SQ1

Bits 0-4: 1st conversion in regular sequence.

Allowed values: 0-17

SQ2

Bits 5-9: 2nd conversion in regular sequence.

Allowed values: 0-17

SQ3

Bits 10-14: 3rd conversion in regular sequence.

Allowed values: 0-17

SQ4

Bits 15-19: 4th conversion in regular sequence.

Allowed values: 0-17

SQ5

Bits 20-24: 5th conversion in regular sequence.

Allowed values: 0-17

SQ6

Bits 25-29: 6th conversion in regular sequence.

Allowed values: 0-17

JSQR

injected sequence register

Offset: 0x38, reset: 0x00000000, access: read-write

5/5 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
JL
rw
JSQ4
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
JSQ4
rw
JSQ3
rw
JSQ2
rw
JSQ1
rw
Toggle Fields.

JSQ1

Bits 0-4: 1st conversion in injected sequence.

Allowed values: 0-17

JSQ2

Bits 5-9: 2nd conversion in injected sequence.

Allowed values: 0-17

JSQ3

Bits 10-14: 3rd conversion in injected sequence.

Allowed values: 0-17

JSQ4

Bits 15-19: 4th conversion in injected sequence.

Allowed values: 0-17

JL

Bits 20-21: Injected sequence length.

Allowed values: 0-3

JDR%s

injected data register x

Offset: 0x3C, reset: 0x00000000, access: read-only

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
JDATA
r
Toggle Fields.

JDATA

Bits 0-15: Injected data.

DR

regular data register

Offset: 0x4C, reset: 0x00000000, access: read-only

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DATA
r
Toggle Fields.

DATA

Bits 0-15: Regular data.

ADC3

0x40013C00: Analog to digital converter

75/75 fields covered. Toggle Registers.

SR

status register

Offset: 0x0, reset: 0x00000000, access: read-write

5/5 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
STRT
rw
JSTRT
rw
JEOC
rw
EOC
rw
AWD
rw
Toggle Fields.

AWD

Bit 0: Analog watchdog flag.

Allowed values:
0: NoEvent: No analog watchdog event occurred
1: Event: Analog watchdog event occurred

EOC

Bit 1: Regular channel end of conversion.

Allowed values:
0: NotComplete: Conversion is not complete
1: Complete: Conversion complete

JEOC

Bit 2: Injected channel end of conversion.

Allowed values:
0: NotComplete: Conversion is not complete
1: Complete: Conversion complete

JSTRT

Bit 3: Injected channel start flag.

Allowed values:
0: NotStarted: No injected group conversion started
1: Started: Injected group conversion has started

STRT

Bit 4: Regular channel start flag.

Allowed values:
0: NotStarted: No regular channel conversion started
1: Started: Regular channel conversion has started

CR1

control register 1

Offset: 0x4, reset: 0x00000000, access: read-write

12/12 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
AWDEN
rw
JAWDEN
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DISCNUM
rw
JDISCEN
rw
DISCEN
rw
JAUTO
rw
AWDSGL
rw
SCAN
rw
JEOCIE
rw
AWDIE
rw
EOCIE
rw
AWDCH
rw
Toggle Fields.

AWDCH

Bits 0-4: Analog watchdog channel select bits.

Allowed values: 0-17

EOCIE

Bit 5: Interrupt enable for EOC.

Allowed values:
0: Disabled: EOC interrupt disabled
1: Enabled: EOC interrupt enabled. An interrupt is generated when the EOC bit is set

AWDIE

Bit 6: Analog watchdog interrupt enable.

Allowed values:
0: Disabled: Analog watchdog interrupt disabled
1: Enabled: Analog watchdog interrupt enabled

JEOCIE

Bit 7: Interrupt enable for injected channels.

Allowed values:
0: Disabled: JEOC interrupt disabled
1: Enabled: JEOC interrupt enabled. An interrupt is generated when the JEOC bit is set

SCAN

Bit 8: Scan mode.

Allowed values:
0: Disabled: Scan mode disabled
1: Enabled: Scan mode enabled

AWDSGL

Bit 9: Enable the watchdog on a single channel in scan mode.

Allowed values:
0: All: Analog watchdog enabled on all channels
1: Single: Analog watchdog enabled on a single channel

JAUTO

Bit 10: Automatic injected group conversion.

Allowed values:
0: Disabled: Automatic injected group conversion disabled
1: Enabled: Automatic injected group conversion enabled

DISCEN

Bit 11: Discontinuous mode on regular channels.

Allowed values:
0: Disabled: Discontinuous mode on regular channels disabled
1: Enabled: Discontinuous mode on regular channels enabled

JDISCEN

Bit 12: Discontinuous mode on injected channels.

Allowed values:
0: Disabled: Discontinuous mode on injected channels disabled
1: Enabled: Discontinuous mode on injected channels enabled

DISCNUM

Bits 13-15: Discontinuous mode channel count.

Allowed values: 0-7

JAWDEN

Bit 22: Analog watchdog enable on injected channels.

Allowed values:
0: Disabled: Analog watchdog disabled on injected channels
1: Enabled: Analog watchdog enabled on injected channels

AWDEN

Bit 23: Analog watchdog enable on regular channels.

Allowed values:
0: Disabled: Analog watchdog disabled on regular channels
1: Enabled: Analog watchdog enabled on regular channels

CR2

control register 2

Offset: 0x8, reset: 0x00000000, access: read-write

13/13 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
TSVREFE
rw
SWSTART
rw
JSWSTART
rw
EXTTRIG
rw
EXTSEL
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
JEXTTRIG
rw
JEXTSEL
rw
ALIGN
rw
DMA
rw
RSTCAL
rw
CAL
rw
CONT
rw
ADON
rw
Toggle Fields.

ADON

Bit 0: A/D converter ON / OFF.

Allowed values:
0: Disabled: Disable ADC conversion/calibration and go to power down mode
1: Enabled: Enable ADC and to start conversion

CONT

Bit 1: Continuous conversion.

Allowed values:
0: Single: Single conversion mode
1: Continuous: Continuous conversion mode

CAL

Bit 2: A/D calibration.

Allowed values:
0: Complete: Calibration completed
1: NotComplete: Calibrating

RSTCAL

Bit 3: Reset calibration.

Allowed values:
0: Initialized: Calibration register initialized
1: NotInitialized: Initializing calibration register

DMA

Bit 8: Direct memory access mode.

Allowed values:
0: Disabled: DMA mode disabled
1: Enabled: DMA mode enabled

ALIGN

Bit 11: Data alignment.

Allowed values:
0: Right: Right Alignment
1: Left: Left Alignment

JEXTSEL

Bits 12-14: External event select for injected group.

Allowed values:
0: Tim1Trgo: Timer 1 TRGO event
1: Tim1Cc4: Timer 1 CC4 event
2: Tim4Cc3: Timer 4 CC3 event
3: Tim8Cc2: Timer 8 CC2 event
4: Tim8Cc4: Timer 8 CC4 event
5: Tim5Trgo: Timer 5 TRGO event
6: Tim5Cc4: Timer 5 CC4 event
7: Jswstart: JSWSTART

JEXTTRIG

Bit 15: External trigger conversion mode for injected channels.

Allowed values:
0: Disabled: Conversion on external event disabled
1: Enabled: Conversion on external event enabled

EXTSEL

Bits 17-19: External event select for regular group.

Allowed values:
0: Tim3Cc1: Timer 3 CC1 event
1: Tim2Cc3: Timer 2 CC3 event
2: Tim1Cc3: Timer 1 CC3 event
3: Tim8Cc1: Timer 8 CC1 event
4: Tim8Trgo: Timer 8 TRGO event
5: Tim5Cc1: Timer 5 CC1 event
6: Tim5Cc3: Timer 5 CC3 event
7: Swstart: SWSTART

EXTTRIG

Bit 20: External trigger conversion mode for regular channels.

Allowed values:
0: Disabled: Conversion on external event disabled
1: Enabled: Conversion on external event enabled

JSWSTART

Bit 21: Start conversion of injected channels.

Allowed values:
0: Started: Reset state
1: NotStarted: Starting conversion of injected channels

SWSTART

Bit 22: Start conversion of regular channels.

Allowed values:
0: Started: Reset state
1: NotStarted: Starting conversion of regular channels

TSVREFE

Bit 23: Temperature sensor and VREFINT enable.

Allowed values:
0: Disabled: Temperature sensor and V_REFINT channel disabled
1: Enabled: Temperature sensor and V_REFINT channel enabled

SMPR1

sample time register 1

Offset: 0xC, reset: 0x00000000, access: read-write

8/8 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
SMP17
rw
SMP16
rw
SMP15
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SMP15
rw
SMP14
rw
SMP13
rw
SMP12
rw
SMP11
rw
SMP10
rw
Toggle Fields.

SMP10

Bits 0-2: Channel 10 sample time selection.

Allowed values:
0: Cycles1_5: 1.5 ADC clock cycles
1: Cycles7_5: 7.5 ADC clock cycles
2: Cycles13_5: 13.5 ADC clock cycles
3: Cycles28_5: 28.5 ADC clock cycles
4: Cycles41_5: 41.5 ADC clock cycles
5: Cycles55_5: 55.5 ADC clock cycles
6: Cycles71_5: 71.5 ADC clock cycles
7: Cycles239_5: 239.5 ADC clock cycles

SMP11

Bits 3-5: Channel 11 sample time selection.

Allowed values:
0: Cycles1_5: 1.5 ADC clock cycles
1: Cycles7_5: 7.5 ADC clock cycles
2: Cycles13_5: 13.5 ADC clock cycles
3: Cycles28_5: 28.5 ADC clock cycles
4: Cycles41_5: 41.5 ADC clock cycles
5: Cycles55_5: 55.5 ADC clock cycles
6: Cycles71_5: 71.5 ADC clock cycles
7: Cycles239_5: 239.5 ADC clock cycles

SMP12

Bits 6-8: Channel 12 sample time selection.

Allowed values:
0: Cycles1_5: 1.5 ADC clock cycles
1: Cycles7_5: 7.5 ADC clock cycles
2: Cycles13_5: 13.5 ADC clock cycles
3: Cycles28_5: 28.5 ADC clock cycles
4: Cycles41_5: 41.5 ADC clock cycles
5: Cycles55_5: 55.5 ADC clock cycles
6: Cycles71_5: 71.5 ADC clock cycles
7: Cycles239_5: 239.5 ADC clock cycles

SMP13

Bits 9-11: Channel 13 sample time selection.

Allowed values:
0: Cycles1_5: 1.5 ADC clock cycles
1: Cycles7_5: 7.5 ADC clock cycles
2: Cycles13_5: 13.5 ADC clock cycles
3: Cycles28_5: 28.5 ADC clock cycles
4: Cycles41_5: 41.5 ADC clock cycles
5: Cycles55_5: 55.5 ADC clock cycles
6: Cycles71_5: 71.5 ADC clock cycles
7: Cycles239_5: 239.5 ADC clock cycles

SMP14

Bits 12-14: Channel 14 sample time selection.

Allowed values:
0: Cycles1_5: 1.5 ADC clock cycles
1: Cycles7_5: 7.5 ADC clock cycles
2: Cycles13_5: 13.5 ADC clock cycles
3: Cycles28_5: 28.5 ADC clock cycles
4: Cycles41_5: 41.5 ADC clock cycles
5: Cycles55_5: 55.5 ADC clock cycles
6: Cycles71_5: 71.5 ADC clock cycles
7: Cycles239_5: 239.5 ADC clock cycles

SMP15

Bits 15-17: Channel 15 sample time selection.

Allowed values:
0: Cycles1_5: 1.5 ADC clock cycles
1: Cycles7_5: 7.5 ADC clock cycles
2: Cycles13_5: 13.5 ADC clock cycles
3: Cycles28_5: 28.5 ADC clock cycles
4: Cycles41_5: 41.5 ADC clock cycles
5: Cycles55_5: 55.5 ADC clock cycles
6: Cycles71_5: 71.5 ADC clock cycles
7: Cycles239_5: 239.5 ADC clock cycles

SMP16

Bits 18-20: Channel 16 sample time selection.

Allowed values:
0: Cycles1_5: 1.5 ADC clock cycles
1: Cycles7_5: 7.5 ADC clock cycles
2: Cycles13_5: 13.5 ADC clock cycles
3: Cycles28_5: 28.5 ADC clock cycles
4: Cycles41_5: 41.5 ADC clock cycles
5: Cycles55_5: 55.5 ADC clock cycles
6: Cycles71_5: 71.5 ADC clock cycles
7: Cycles239_5: 239.5 ADC clock cycles

SMP17

Bits 21-23: Channel 17 sample time selection.

Allowed values:
0: Cycles1_5: 1.5 ADC clock cycles
1: Cycles7_5: 7.5 ADC clock cycles
2: Cycles13_5: 13.5 ADC clock cycles
3: Cycles28_5: 28.5 ADC clock cycles
4: Cycles41_5: 41.5 ADC clock cycles
5: Cycles55_5: 55.5 ADC clock cycles
6: Cycles71_5: 71.5 ADC clock cycles
7: Cycles239_5: 239.5 ADC clock cycles

SMPR2

sample time register 2

Offset: 0x10, reset: 0x00000000, access: read-write

10/10 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
SMP9
rw
SMP8
rw
SMP7
rw
SMP6
rw
SMP5
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SMP5
rw
SMP4
rw
SMP3
rw
SMP2
rw
SMP1
rw
SMP0
rw
Toggle Fields.

SMP0

Bits 0-2: Channel 0 sample time selection.

Allowed values:
0: Cycles1_5: 1.5 ADC clock cycles
1: Cycles7_5: 7.5 ADC clock cycles
2: Cycles13_5: 13.5 ADC clock cycles
3: Cycles28_5: 28.5 ADC clock cycles
4: Cycles41_5: 41.5 ADC clock cycles
5: Cycles55_5: 55.5 ADC clock cycles
6: Cycles71_5: 71.5 ADC clock cycles
7: Cycles239_5: 239.5 ADC clock cycles

SMP1

Bits 3-5: Channel 1 sample time selection.

Allowed values:
0: Cycles1_5: 1.5 ADC clock cycles
1: Cycles7_5: 7.5 ADC clock cycles
2: Cycles13_5: 13.5 ADC clock cycles
3: Cycles28_5: 28.5 ADC clock cycles
4: Cycles41_5: 41.5 ADC clock cycles
5: Cycles55_5: 55.5 ADC clock cycles
6: Cycles71_5: 71.5 ADC clock cycles
7: Cycles239_5: 239.5 ADC clock cycles

SMP2

Bits 6-8: Channel 2 sample time selection.

Allowed values:
0: Cycles1_5: 1.5 ADC clock cycles
1: Cycles7_5: 7.5 ADC clock cycles
2: Cycles13_5: 13.5 ADC clock cycles
3: Cycles28_5: 28.5 ADC clock cycles
4: Cycles41_5: 41.5 ADC clock cycles
5: Cycles55_5: 55.5 ADC clock cycles
6: Cycles71_5: 71.5 ADC clock cycles
7: Cycles239_5: 239.5 ADC clock cycles

SMP3

Bits 9-11: Channel 3 sample time selection.

Allowed values:
0: Cycles1_5: 1.5 ADC clock cycles
1: Cycles7_5: 7.5 ADC clock cycles
2: Cycles13_5: 13.5 ADC clock cycles
3: Cycles28_5: 28.5 ADC clock cycles
4: Cycles41_5: 41.5 ADC clock cycles
5: Cycles55_5: 55.5 ADC clock cycles
6: Cycles71_5: 71.5 ADC clock cycles
7: Cycles239_5: 239.5 ADC clock cycles

SMP4

Bits 12-14: Channel 4 sample time selection.

Allowed values:
0: Cycles1_5: 1.5 ADC clock cycles
1: Cycles7_5: 7.5 ADC clock cycles
2: Cycles13_5: 13.5 ADC clock cycles
3: Cycles28_5: 28.5 ADC clock cycles
4: Cycles41_5: 41.5 ADC clock cycles
5: Cycles55_5: 55.5 ADC clock cycles
6: Cycles71_5: 71.5 ADC clock cycles
7: Cycles239_5: 239.5 ADC clock cycles

SMP5

Bits 15-17: Channel 5 sample time selection.

Allowed values:
0: Cycles1_5: 1.5 ADC clock cycles
1: Cycles7_5: 7.5 ADC clock cycles
2: Cycles13_5: 13.5 ADC clock cycles
3: Cycles28_5: 28.5 ADC clock cycles
4: Cycles41_5: 41.5 ADC clock cycles
5: Cycles55_5: 55.5 ADC clock cycles
6: Cycles71_5: 71.5 ADC clock cycles
7: Cycles239_5: 239.5 ADC clock cycles

SMP6

Bits 18-20: Channel 6 sample time selection.

Allowed values:
0: Cycles1_5: 1.5 ADC clock cycles
1: Cycles7_5: 7.5 ADC clock cycles
2: Cycles13_5: 13.5 ADC clock cycles
3: Cycles28_5: 28.5 ADC clock cycles
4: Cycles41_5: 41.5 ADC clock cycles
5: Cycles55_5: 55.5 ADC clock cycles
6: Cycles71_5: 71.5 ADC clock cycles
7: Cycles239_5: 239.5 ADC clock cycles

SMP7

Bits 21-23: Channel 7 sample time selection.

Allowed values:
0: Cycles1_5: 1.5 ADC clock cycles
1: Cycles7_5: 7.5 ADC clock cycles
2: Cycles13_5: 13.5 ADC clock cycles
3: Cycles28_5: 28.5 ADC clock cycles
4: Cycles41_5: 41.5 ADC clock cycles
5: Cycles55_5: 55.5 ADC clock cycles
6: Cycles71_5: 71.5 ADC clock cycles
7: Cycles239_5: 239.5 ADC clock cycles

SMP8

Bits 24-26: Channel 8 sample time selection.

Allowed values:
0: Cycles1_5: 1.5 ADC clock cycles
1: Cycles7_5: 7.5 ADC clock cycles
2: Cycles13_5: 13.5 ADC clock cycles
3: Cycles28_5: 28.5 ADC clock cycles
4: Cycles41_5: 41.5 ADC clock cycles
5: Cycles55_5: 55.5 ADC clock cycles
6: Cycles71_5: 71.5 ADC clock cycles
7: Cycles239_5: 239.5 ADC clock cycles

SMP9

Bits 27-29: Channel 9 sample time selection.

Allowed values:
0: Cycles1_5: 1.5 ADC clock cycles
1: Cycles7_5: 7.5 ADC clock cycles
2: Cycles13_5: 13.5 ADC clock cycles
3: Cycles28_5: 28.5 ADC clock cycles
4: Cycles41_5: 41.5 ADC clock cycles
5: Cycles55_5: 55.5 ADC clock cycles
6: Cycles71_5: 71.5 ADC clock cycles
7: Cycles239_5: 239.5 ADC clock cycles

JOFR%s

injected channel data offset register x

Offset: 0x14, reset: 0x00000000, access: read-write

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
JOFFSET
rw
Toggle Fields.

JOFFSET

Bits 0-11: Data offset for injected channel x.

Allowed values: 0-4095

HTR

watchdog higher threshold register

Offset: 0x24, reset: 0x00000FFF, access: read-write

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
HT
rw
Toggle Fields.

HT

Bits 0-11: Analog watchdog higher threshold.

Allowed values: 0-4095

LTR

watchdog lower threshold register

Offset: 0x28, reset: 0x00000000, access: read-write

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LT
rw
Toggle Fields.

LT

Bits 0-11: Analog watchdog lower threshold.

Allowed values: 0-4095

SQR1

regular sequence register 1

Offset: 0x2C, reset: 0x00000000, access: read-write

5/5 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
L
rw
SQ16
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SQ16
rw
SQ15
rw
SQ14
rw
SQ13
rw
Toggle Fields.

SQ13

Bits 0-4: 13th conversion in regular sequence.

Allowed values: 0-17

SQ14

Bits 5-9: 14th conversion in regular sequence.

Allowed values: 0-17

SQ15

Bits 10-14: 15th conversion in regular sequence.

Allowed values: 0-17

SQ16

Bits 15-19: 16th conversion in regular sequence.

Allowed values: 0-17

L

Bits 20-23: Regular channel sequence length.

Allowed values: 0-15

SQR2

regular sequence register 2

Offset: 0x30, reset: 0x00000000, access: read-write

6/6 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
SQ12
rw
SQ11
rw
SQ10
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SQ10
rw
SQ9
rw
SQ8
rw
SQ7
rw
Toggle Fields.

SQ7

Bits 0-4: 7th conversion in regular sequence.

Allowed values: 0-17

SQ8

Bits 5-9: 8th conversion in regular sequence.

Allowed values: 0-17

SQ9

Bits 10-14: 9th conversion in regular sequence.

Allowed values: 0-17

SQ10

Bits 15-19: 10th conversion in regular sequence.

Allowed values: 0-17

SQ11

Bits 20-24: 11th conversion in regular sequence.

Allowed values: 0-17

SQ12

Bits 25-29: 12th conversion in regular sequence.

Allowed values: 0-17

SQR3

regular sequence register 3

Offset: 0x34, reset: 0x00000000, access: read-write

6/6 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
SQ6
rw
SQ5
rw
SQ4
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SQ4
rw
SQ3
rw
SQ2
rw
SQ1
rw
Toggle Fields.

SQ1

Bits 0-4: 1st conversion in regular sequence.

Allowed values: 0-17

SQ2

Bits 5-9: 2nd conversion in regular sequence.

Allowed values: 0-17

SQ3

Bits 10-14: 3rd conversion in regular sequence.

Allowed values: 0-17

SQ4

Bits 15-19: 4th conversion in regular sequence.

Allowed values: 0-17

SQ5

Bits 20-24: 5th conversion in regular sequence.

Allowed values: 0-17

SQ6

Bits 25-29: 6th conversion in regular sequence.

Allowed values: 0-17

JSQR

injected sequence register

Offset: 0x38, reset: 0x00000000, access: read-write

5/5 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
JL
rw
JSQ4
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
JSQ4
rw
JSQ3
rw
JSQ2
rw
JSQ1
rw
Toggle Fields.

JSQ1

Bits 0-4: 1st conversion in injected sequence.

Allowed values: 0-17

JSQ2

Bits 5-9: 2nd conversion in injected sequence.

Allowed values: 0-17

JSQ3

Bits 10-14: 3rd conversion in injected sequence.

Allowed values: 0-17

JSQ4

Bits 15-19: 4th conversion in injected sequence.

Allowed values: 0-17

JL

Bits 20-21: Injected sequence length.

Allowed values: 0-3

JDR%s

injected data register x

Offset: 0x3C, reset: 0x00000000, access: read-only

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
JDATA
r
Toggle Fields.

JDATA

Bits 0-15: Injected data.

DR

regular data register

Offset: 0x4C, reset: 0x00000000, access: read-only

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DATA
r
Toggle Fields.

DATA

Bits 0-15: Regular data.

AFIO

0x40010000: Alternate function I/O

0/42 fields covered. Toggle Registers.

EVCR

Event Control Register (AFIO_EVCR)

Offset: 0x0, reset: 0x00000000, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
EVOE
rw
PORT
rw
PIN
rw
Toggle Fields.

PIN

Bits 0-3: Pin selection.

PORT

Bits 4-6: Port selection.

EVOE

Bit 7: Event Output Enable.

MAPR

AF remap and debug I/O configuration register (AFIO_MAPR)

Offset: 0x4, reset: 0x00000000, access: Unspecified

0/17 fields covered.

SPI1_REMAP

Bit 0: SPI1 remapping.

I2C1_REMAP

Bit 1: I2C1 remapping.

USART1_REMAP

Bit 2: USART1 remapping.

USART2_REMAP

Bit 3: USART2 remapping.

USART3_REMAP

Bits 4-5: USART3 remapping.

TIM1_REMAP

Bits 6-7: TIM1 remapping.

TIM2_REMAP

Bits 8-9: TIM2 remapping.

TIM3_REMAP

Bits 10-11: TIM3 remapping.

TIM4_REMAP

Bit 12: TIM4 remapping.

CAN_REMAP

Bits 13-14: CAN1 remapping.

PD01_REMAP

Bit 15: Port D0/Port D1 mapping on OSCIN/OSCOUT.

TIM5CH4_IREMAP

Bit 16: Set and cleared by software.

ADC1_ETRGINJ_REMAP

Bit 17: ADC 1 External trigger injected conversion remapping.

ADC1_ETRGREG_REMAP

Bit 18: ADC 1 external trigger regular conversion remapping.

ADC2_ETRGINJ_REMAP

Bit 19: ADC 2 external trigger injected conversion remapping.

ADC2_ETRGREG_REMAP

Bit 20: ADC 2 external trigger regular conversion remapping.

SWJ_CFG

Bits 24-26: Serial wire JTAG configuration.

EXTICR1

External interrupt configuration register 1 (AFIO_EXTICR1)

Offset: 0x8, reset: 0x00000000, access: read-write

0/4 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
EXTI3
rw
EXTI2
rw
EXTI1
rw
EXTI0
rw
Toggle Fields.

EXTI0

Bits 0-3: EXTI0 configuration.

EXTI1

Bits 4-7: EXTI1 configuration.

EXTI2

Bits 8-11: EXTI2 configuration.

EXTI3

Bits 12-15: EXTI3 configuration.

EXTICR2

External interrupt configuration register 2 (AFIO_EXTICR2)

Offset: 0xC, reset: 0x00000000, access: read-write

0/4 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
EXTI7
rw
EXTI6
rw
EXTI5
rw
EXTI4
rw
Toggle Fields.

EXTI4

Bits 0-3: EXTI4 configuration.

EXTI5

Bits 4-7: EXTI5 configuration.

EXTI6

Bits 8-11: EXTI6 configuration.

EXTI7

Bits 12-15: EXTI7 configuration.

EXTICR3

External interrupt configuration register 3 (AFIO_EXTICR3)

Offset: 0x10, reset: 0x00000000, access: read-write

0/4 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
EXTI11
rw
EXTI10
rw
EXTI9
rw
EXTI8
rw
Toggle Fields.

EXTI8

Bits 0-3: EXTI8 configuration.

EXTI9

Bits 4-7: EXTI9 configuration.

EXTI10

Bits 8-11: EXTI10 configuration.

EXTI11

Bits 12-15: EXTI11 configuration.

EXTICR4

External interrupt configuration register 4 (AFIO_EXTICR4)

Offset: 0x14, reset: 0x00000000, access: read-write

0/4 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
EXTI15
rw
EXTI14
rw
EXTI13
rw
EXTI12
rw
Toggle Fields.

EXTI12

Bits 0-3: EXTI12 configuration.

EXTI13

Bits 4-7: EXTI13 configuration.

EXTI14

Bits 8-11: EXTI14 configuration.

EXTI15

Bits 12-15: EXTI15 configuration.

MAPR2

AF remap and debug I/O configuration register

Offset: 0x1C, reset: 0x00000000, access: read-write

0/6 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FSMC_NADV
rw
TIM14_REMAP
rw
TIM13_REMAP
rw
TIM11_REMAP
rw
TIM10_REMAP
rw
TIM9_REMAP
rw
Toggle Fields.

TIM9_REMAP

Bit 5: TIM9 remapping.

TIM10_REMAP

Bit 6: TIM10 remapping.

TIM11_REMAP

Bit 7: TIM11 remapping.

TIM13_REMAP

Bit 8: TIM13 remapping.

TIM14_REMAP

Bit 9: TIM14 remapping.

FSMC_NADV

Bit 10: NADV connect/disconnect.

BKP

0x40006C04: Backup registers

12/13 fields covered. Toggle Registers.

DR%s

Backup data register (BKP_DR)

Offset: 0x0, reset: 0x00000000, access: read-write

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
D
rw
Toggle Fields.

D

Bits 0-15: Backup data.

Allowed values: 0-65535

RTCCR

RTC clock calibration register (BKP_RTCCR)

Offset: 0x28, reset: 0x00000000, access: read-write

3/4 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ASOS
rw
ASOE
rw
CCO
rw
CAL
rw
Toggle Fields.

CAL

Bits 0-6: Calibration value.

Allowed values: 0-121

CCO

Bit 7: Calibration Clock Output.

ASOE

Bit 8: Alarm or second output enable.

Allowed values:
0: Disabled: Disabled
1: Enabled: Setting this bit outputs either the RTC Alarm pulse signal or the Second pulse signal on the TAMPER pin depending on the ASOS bit

ASOS

Bit 9: Alarm or second output selection.

Allowed values:
0: Alarm: RTC Alarm pulse output selected
1: Second: RTC Second pulse output selected

CR

Backup control register (BKP_CR)

Offset: 0x2C, reset: 0x00000000, access: read-write

2/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TPAL
rw
TPE
rw
Toggle Fields.

TPE

Bit 0: Tamper pin enable.

Allowed values:
0: General: The TAMPER pin is free for general purpose I/O
1: Alternate: Tamper alternate I/O function is activated

TPAL

Bit 1: Tamper pin active level.

Allowed values:
0: High: A high level on the TAMPER pin resets all data backup registers (if TPE bit is set)
1: Low: A low level on the TAMPER pin resets all data backup registers (if TPE bit is set)

CSR

BKP_CSR control/status register (BKP_CSR)

Offset: 0x30, reset: 0x00000000, access: Unspecified

5/5 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TIF
r
TEF
r
TPIE
rw
CTI
w
CTE
w
Toggle Fields.

CTE

Bit 0: Clear Tamper event.

Allowed values:
1: Reset: Reset the TEF Tamper event flag (and the Tamper detector)

CTI

Bit 1: Clear Tamper Interrupt.

Allowed values:
1: Clear: Clear the Tamper interrupt and the TIF Tamper interrupt flag

TPIE

Bit 2: Tamper Pin interrupt enable.

Allowed values:
0: Disabled: Tamper interrupt disabled
1: Enabled: Tamper interrupt enabled (the TPE bit must also be set in the BKP_CR register

TEF

Bit 8: Tamper Event Flag.

TIF

Bit 9: Tamper Interrupt Flag.

BKP_DR%s

Backup data register (BKP_DR)

Offset: 0x3C, reset: 0x00000000, access: read-write

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
D
rw
Toggle Fields.

D

Bits 0-15: Backup data.

Allowed values: 0-65535

CAN1

0x40006400: Controller area network

57/161 fields covered. Toggle Registers.

FR1

Filter bank 0 register 1

Offset: 0x0, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
FB
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FB
rw
Toggle Fields.

FB

Bits 0-31: Filter bits.

FR2

Filter bank 0 register 2

Offset: 0x4, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
FB
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FB
rw
Toggle Fields.

FB

Bits 0-31: Filter bits.

RDLR

CAN_RDL0R

Offset: 0x8, reset: 0x00000000, access: read-only

4/4 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DATA3
r
DATA2
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DATA1
r
DATA0
r
Toggle Fields.

DATA0

Bits 0-7: DATA0.

DATA1

Bits 8-15: DATA1.

DATA2

Bits 16-23: DATA2.

DATA3

Bits 24-31: DATA3.

RDHR

CAN_RDH0R

Offset: 0xC, reset: 0x00000000, access: read-only

4/4 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DATA7
r
DATA6
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DATA5
r
DATA4
r
Toggle Fields.

DATA4

Bits 0-7: DATA4.

DATA5

Bits 8-15: DATA5.

DATA6

Bits 16-23: DATA6.

DATA7

Bits 24-31: DATA7.

IER

CAN_IER

Offset: 0x14, reset: 0x00000000, access: read-write

14/14 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
SLKIE
rw
WKUIE
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ERRIE
rw
LECIE
rw
BOFIE
rw
EPVIE
rw
EWGIE
rw
FOVIE1
rw
FFIE1
rw
FMPIE1
rw
FOVIE0
rw
FFIE0
rw
FMPIE0
rw
TMEIE
rw
Toggle Fields.

TMEIE

Bit 0: TMEIE.

Allowed values:
0: Disabled: No interrupt when RQCPx bit is set
1: Enabled: Interrupt generated when RQCPx bit is set

FMPIE0

Bit 1: FMPIE0.

Allowed values:
0: Disabled: No interrupt generated when state of FMP[1:0] bits are not 00
1: Enabled: Interrupt generated when state of FMP[1:0] bits are not 00b

FFIE0

Bit 2: FFIE0.

Allowed values:
0: Disabled: No interrupt when FULL bit is set
1: Enabled: Interrupt generated when FULL bit is set

FOVIE0

Bit 3: FOVIE0.

Allowed values:
0: Disabled: No interrupt when FOVR bit is set
1: Enabled: Interrupt generated when FOVR bit is set

FMPIE1

Bit 4: FMPIE1.

Allowed values:
0: Disabled: No interrupt generated when state of FMP[1:0] bits are not 00b
1: Enabled: Interrupt generated when state of FMP[1:0] bits are not 00b

FFIE1

Bit 5: FFIE1.

Allowed values:
0: Disabled: No interrupt when FULL bit is set
1: Enabled: Interrupt generated when FULL bit is set

FOVIE1

Bit 6: FOVIE1.

Allowed values:
0: Disabled: No interrupt when FOVR is set
1: Enabled: Interrupt generation when FOVR is set

EWGIE

Bit 8: EWGIE.

Allowed values:
0: Disabled: ERRI bit will not be set when EWGF is set
1: Enabled: ERRI bit will be set when EWGF is set

EPVIE

Bit 9: EPVIE.

Allowed values:
0: Disabled: ERRI bit will not be set when EPVF is set
1: Enabled: ERRI bit will be set when EPVF is set

BOFIE

Bit 10: BOFIE.

Allowed values:
0: Disabled: ERRI bit will not be set when BOFF is set
1: Enabled: ERRI bit will be set when BOFF is set

LECIE

Bit 11: LECIE.

Allowed values:
0: Disabled: ERRI bit will not be set when the error code in LEC[2:0] is set by hardware on error detection
1: Enabled: ERRI bit will be set when the error code in LEC[2:0] is set by hardware on error detection

ERRIE

Bit 15: ERRIE.

Allowed values:
0: Disabled: No interrupt will be generated when an error condition is pending in the CAN_ESR
1: Enabled: An interrupt will be generation when an error condition is pending in the CAN_ESR

WKUIE

Bit 16: WKUIE.

Allowed values:
0: Disabled: No interrupt when WKUI is set
1: Enabled: Interrupt generated when WKUI bit is set

SLKIE

Bit 17: SLKIE.

Allowed values:
0: Disabled: No interrupt when SLAKI bit is set
1: Enabled: Interrupt generated when SLAKI bit is set

ESR

CAN_ESR

Offset: 0x18, reset: 0x00000000, access: Unspecified

6/6 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
REC
r
TEC
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LEC
rw
BOFF
r
EPVF
r
EWGF
r
Toggle Fields.

EWGF

Bit 0: EWGF.

EPVF

Bit 1: EPVF.

BOFF

Bit 2: BOFF.

LEC

Bits 4-6: LEC.

Allowed values:
0: NoError: No Error
1: Stuff: Stuff Error
2: Form: Form Error
3: Ack: Acknowledgment Error
4: BitRecessive: Bit recessive Error
5: BitDominant: Bit dominant Error
6: Crc: CRC Error
7: Custom: Set by software

TEC

Bits 16-23: TEC.

REC

Bits 24-31: REC.

BTR

CAN_BTR

Offset: 0x1C, reset: 0x00000000, access: read-write

2/6 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
SILM
rw
LBKM
rw
SJW
rw
TS2
rw
TS1
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
BRP
rw
Toggle Fields.

BRP

Bits 0-9: BRP.

TS1

Bits 16-19: TS1.

TS2

Bits 20-22: TS2.

SJW

Bits 24-25: SJW.

LBKM

Bit 30: LBKM.

Allowed values:
0: Disabled: Loop Back Mode disabled
1: Enabled: Loop Back Mode enabled

SILM

Bit 31: SILM.

Allowed values:
0: Normal: Normal operation
1: Silent: Silent Mode

FMR

CAN_FMR

Offset: 0x200, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FINIT
rw
Toggle Fields.

FINIT

Bit 0: FINIT.

FM1R

CAN_FM1R

Offset: 0x204, reset: 0x00000000, access: read-write

0/14 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FBM13
rw
FBM12
rw
FBM11
rw
FBM10
rw
FBM9
rw
FBM8
rw
FBM7
rw
FBM6
rw
FBM5
rw
FBM4
rw
FBM3
rw
FBM2
rw
FBM1
rw
FBM0
rw
Toggle Fields.

FBM0

Bit 0: Filter mode.

FBM1

Bit 1: Filter mode.

FBM2

Bit 2: Filter mode.

FBM3

Bit 3: Filter mode.

FBM4

Bit 4: Filter mode.

FBM5

Bit 5: Filter mode.

FBM6

Bit 6: Filter mode.

FBM7

Bit 7: Filter mode.

FBM8

Bit 8: Filter mode.

FBM9

Bit 9: Filter mode.

FBM10

Bit 10: Filter mode.

FBM11

Bit 11: Filter mode.

FBM12

Bit 12: Filter mode.

FBM13

Bit 13: Filter mode.

FS1R

CAN_FS1R

Offset: 0x20C, reset: 0x00000000, access: read-write

0/14 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FSC13
rw
FSC12
rw
FSC11
rw
FSC10
rw
FSC9
rw
FSC8
rw
FSC7
rw
FSC6
rw
FSC5
rw
FSC4
rw
FSC3
rw
FSC2
rw
FSC1
rw
FSC0
rw
Toggle Fields.

FSC0

Bit 0: Filter scale configuration.

FSC1

Bit 1: Filter scale configuration.

FSC2

Bit 2: Filter scale configuration.

FSC3

Bit 3: Filter scale configuration.

FSC4

Bit 4: Filter scale configuration.

FSC5

Bit 5: Filter scale configuration.

FSC6

Bit 6: Filter scale configuration.

FSC7

Bit 7: Filter scale configuration.

FSC8

Bit 8: Filter scale configuration.

FSC9

Bit 9: Filter scale configuration.

FSC10

Bit 10: Filter scale configuration.

FSC11

Bit 11: Filter scale configuration.

FSC12

Bit 12: Filter scale configuration.

FSC13

Bit 13: Filter scale configuration.

FFA1R

CAN_FFA1R

Offset: 0x214, reset: 0x00000000, access: read-write

0/14 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FFA13
rw
FFA12
rw
FFA11
rw
FFA10
rw
FFA9
rw
FFA8
rw
FFA7
rw
FFA6
rw
FFA5
rw
FFA4
rw
FFA3
rw
FFA2
rw
FFA1
rw
FFA0
rw
Toggle Fields.

FFA0

Bit 0: Filter FIFO assignment for filter 0.

FFA1

Bit 1: Filter FIFO assignment for filter 1.

FFA2

Bit 2: Filter FIFO assignment for filter 2.

FFA3

Bit 3: Filter FIFO assignment for filter 3.

FFA4

Bit 4: Filter FIFO assignment for filter 4.

FFA5

Bit 5: Filter FIFO assignment for filter 5.

FFA6

Bit 6: Filter FIFO assignment for filter 6.

FFA7

Bit 7: Filter FIFO assignment for filter 7.

FFA8

Bit 8: Filter FIFO assignment for filter 8.

FFA9

Bit 9: Filter FIFO assignment for filter 9.

FFA10

Bit 10: Filter FIFO assignment for filter 10.

FFA11

Bit 11: Filter FIFO assignment for filter 11.

FFA12

Bit 12: Filter FIFO assignment for filter 12.

FFA13

Bit 13: Filter FIFO assignment for filter 13.

FA1R

CAN_FA1R

Offset: 0x21C, reset: 0x00000000, access: read-write

0/14 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FACT13
rw
FACT12
rw
FACT11
rw
FACT10
rw
FACT9
rw
FACT8
rw
FACT7
rw
FACT6
rw
FACT5
rw
FACT4
rw
FACT3
rw
FACT2
rw
FACT1
rw
FACT0
rw
Toggle Fields.

FACT0

Bit 0: Filter active.

FACT1

Bit 1: Filter active.

FACT2

Bit 2: Filter active.

FACT3

Bit 3: Filter active.

FACT4

Bit 4: Filter active.

FACT5

Bit 5: Filter active.

FACT6

Bit 6: Filter active.

FACT7

Bit 7: Filter active.

FACT8

Bit 8: Filter active.

FACT9

Bit 9: Filter active.

FACT10

Bit 10: Filter active.

FACT11

Bit 11: Filter active.

FACT12

Bit 12: Filter active.

FACT13

Bit 13: Filter active.

CAN2

0x40006800: Controller area network

57/161 fields covered. Toggle Registers.

FR1

Filter bank 0 register 1

Offset: 0x0, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
FB
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FB
rw
Toggle Fields.

FB

Bits 0-31: Filter bits.

FR2

Filter bank 0 register 2

Offset: 0x4, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
FB
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FB
rw
Toggle Fields.

FB

Bits 0-31: Filter bits.

RDLR

CAN_RDL0R

Offset: 0x8, reset: 0x00000000, access: read-only

4/4 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DATA3
r
DATA2
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DATA1
r
DATA0
r
Toggle Fields.

DATA0

Bits 0-7: DATA0.

DATA1

Bits 8-15: DATA1.

DATA2

Bits 16-23: DATA2.

DATA3

Bits 24-31: DATA3.

RDHR

CAN_RDH0R

Offset: 0xC, reset: 0x00000000, access: read-only

4/4 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DATA7
r
DATA6
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DATA5
r
DATA4
r
Toggle Fields.

DATA4

Bits 0-7: DATA4.

DATA5

Bits 8-15: DATA5.

DATA6

Bits 16-23: DATA6.

DATA7

Bits 24-31: DATA7.

IER

CAN_IER

Offset: 0x14, reset: 0x00000000, access: read-write

14/14 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
SLKIE
rw
WKUIE
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ERRIE
rw
LECIE
rw
BOFIE
rw
EPVIE
rw
EWGIE
rw
FOVIE1
rw
FFIE1
rw
FMPIE1
rw
FOVIE0
rw
FFIE0
rw
FMPIE0
rw
TMEIE
rw
Toggle Fields.

TMEIE

Bit 0: TMEIE.

Allowed values:
0: Disabled: No interrupt when RQCPx bit is set
1: Enabled: Interrupt generated when RQCPx bit is set

FMPIE0

Bit 1: FMPIE0.

Allowed values:
0: Disabled: No interrupt generated when state of FMP[1:0] bits are not 00
1: Enabled: Interrupt generated when state of FMP[1:0] bits are not 00b

FFIE0

Bit 2: FFIE0.

Allowed values:
0: Disabled: No interrupt when FULL bit is set
1: Enabled: Interrupt generated when FULL bit is set

FOVIE0

Bit 3: FOVIE0.

Allowed values:
0: Disabled: No interrupt when FOVR bit is set
1: Enabled: Interrupt generated when FOVR bit is set

FMPIE1

Bit 4: FMPIE1.

Allowed values:
0: Disabled: No interrupt generated when state of FMP[1:0] bits are not 00b
1: Enabled: Interrupt generated when state of FMP[1:0] bits are not 00b

FFIE1

Bit 5: FFIE1.

Allowed values:
0: Disabled: No interrupt when FULL bit is set
1: Enabled: Interrupt generated when FULL bit is set

FOVIE1

Bit 6: FOVIE1.

Allowed values:
0: Disabled: No interrupt when FOVR is set
1: Enabled: Interrupt generation when FOVR is set

EWGIE

Bit 8: EWGIE.

Allowed values:
0: Disabled: ERRI bit will not be set when EWGF is set
1: Enabled: ERRI bit will be set when EWGF is set

EPVIE

Bit 9: EPVIE.

Allowed values:
0: Disabled: ERRI bit will not be set when EPVF is set
1: Enabled: ERRI bit will be set when EPVF is set

BOFIE

Bit 10: BOFIE.

Allowed values:
0: Disabled: ERRI bit will not be set when BOFF is set
1: Enabled: ERRI bit will be set when BOFF is set

LECIE

Bit 11: LECIE.

Allowed values:
0: Disabled: ERRI bit will not be set when the error code in LEC[2:0] is set by hardware on error detection
1: Enabled: ERRI bit will be set when the error code in LEC[2:0] is set by hardware on error detection

ERRIE

Bit 15: ERRIE.

Allowed values:
0: Disabled: No interrupt will be generated when an error condition is pending in the CAN_ESR
1: Enabled: An interrupt will be generation when an error condition is pending in the CAN_ESR

WKUIE

Bit 16: WKUIE.

Allowed values:
0: Disabled: No interrupt when WKUI is set
1: Enabled: Interrupt generated when WKUI bit is set

SLKIE

Bit 17: SLKIE.

Allowed values:
0: Disabled: No interrupt when SLAKI bit is set
1: Enabled: Interrupt generated when SLAKI bit is set

ESR

CAN_ESR

Offset: 0x18, reset: 0x00000000, access: Unspecified

6/6 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
REC
r
TEC
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LEC
rw
BOFF
r
EPVF
r
EWGF
r
Toggle Fields.

EWGF

Bit 0: EWGF.

EPVF

Bit 1: EPVF.

BOFF

Bit 2: BOFF.

LEC

Bits 4-6: LEC.

Allowed values:
0: NoError: No Error
1: Stuff: Stuff Error
2: Form: Form Error
3: Ack: Acknowledgment Error
4: BitRecessive: Bit recessive Error
5: BitDominant: Bit dominant Error
6: Crc: CRC Error
7: Custom: Set by software

TEC

Bits 16-23: TEC.

REC

Bits 24-31: REC.

BTR

CAN_BTR

Offset: 0x1C, reset: 0x00000000, access: read-write

2/6 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
SILM
rw
LBKM
rw
SJW
rw
TS2
rw
TS1
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
BRP
rw
Toggle Fields.

BRP

Bits 0-9: BRP.

TS1

Bits 16-19: TS1.

TS2

Bits 20-22: TS2.

SJW

Bits 24-25: SJW.

LBKM

Bit 30: LBKM.

Allowed values:
0: Disabled: Loop Back Mode disabled
1: Enabled: Loop Back Mode enabled

SILM

Bit 31: SILM.

Allowed values:
0: Normal: Normal operation
1: Silent: Silent Mode

FMR

CAN_FMR

Offset: 0x200, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FINIT
rw
Toggle Fields.

FINIT

Bit 0: FINIT.

FM1R

CAN_FM1R

Offset: 0x204, reset: 0x00000000, access: read-write

0/14 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FBM13
rw
FBM12
rw
FBM11
rw
FBM10
rw
FBM9
rw
FBM8
rw
FBM7
rw
FBM6
rw
FBM5
rw
FBM4
rw
FBM3
rw
FBM2
rw
FBM1
rw
FBM0
rw
Toggle Fields.

FBM0

Bit 0: Filter mode.

FBM1

Bit 1: Filter mode.

FBM2

Bit 2: Filter mode.

FBM3

Bit 3: Filter mode.

FBM4

Bit 4: Filter mode.

FBM5

Bit 5: Filter mode.

FBM6

Bit 6: Filter mode.

FBM7

Bit 7: Filter mode.

FBM8

Bit 8: Filter mode.

FBM9

Bit 9: Filter mode.

FBM10

Bit 10: Filter mode.

FBM11

Bit 11: Filter mode.

FBM12

Bit 12: Filter mode.

FBM13

Bit 13: Filter mode.

FS1R

CAN_FS1R

Offset: 0x20C, reset: 0x00000000, access: read-write

0/14 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FSC13
rw
FSC12
rw
FSC11
rw
FSC10
rw
FSC9
rw
FSC8
rw
FSC7
rw
FSC6
rw
FSC5
rw
FSC4
rw
FSC3
rw
FSC2
rw
FSC1
rw
FSC0
rw
Toggle Fields.

FSC0

Bit 0: Filter scale configuration.

FSC1

Bit 1: Filter scale configuration.

FSC2

Bit 2: Filter scale configuration.

FSC3

Bit 3: Filter scale configuration.

FSC4

Bit 4: Filter scale configuration.

FSC5

Bit 5: Filter scale configuration.

FSC6

Bit 6: Filter scale configuration.

FSC7

Bit 7: Filter scale configuration.

FSC8

Bit 8: Filter scale configuration.

FSC9

Bit 9: Filter scale configuration.

FSC10

Bit 10: Filter scale configuration.

FSC11

Bit 11: Filter scale configuration.

FSC12

Bit 12: Filter scale configuration.

FSC13

Bit 13: Filter scale configuration.

FFA1R

CAN_FFA1R

Offset: 0x214, reset: 0x00000000, access: read-write

0/14 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FFA13
rw
FFA12
rw
FFA11
rw
FFA10
rw
FFA9
rw
FFA8
rw
FFA7
rw
FFA6
rw
FFA5
rw
FFA4
rw
FFA3
rw
FFA2
rw
FFA1
rw
FFA0
rw
Toggle Fields.

FFA0

Bit 0: Filter FIFO assignment for filter 0.

FFA1

Bit 1: Filter FIFO assignment for filter 1.

FFA2

Bit 2: Filter FIFO assignment for filter 2.

FFA3

Bit 3: Filter FIFO assignment for filter 3.

FFA4

Bit 4: Filter FIFO assignment for filter 4.

FFA5

Bit 5: Filter FIFO assignment for filter 5.

FFA6

Bit 6: Filter FIFO assignment for filter 6.

FFA7

Bit 7: Filter FIFO assignment for filter 7.

FFA8

Bit 8: Filter FIFO assignment for filter 8.

FFA9

Bit 9: Filter FIFO assignment for filter 9.

FFA10

Bit 10: Filter FIFO assignment for filter 10.

FFA11

Bit 11: Filter FIFO assignment for filter 11.

FFA12

Bit 12: Filter FIFO assignment for filter 12.

FFA13

Bit 13: Filter FIFO assignment for filter 13.

FA1R

CAN_FA1R

Offset: 0x21C, reset: 0x00000000, access: read-write

0/14 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FACT13
rw
FACT12
rw
FACT11
rw
FACT10
rw
FACT9
rw
FACT8
rw
FACT7
rw
FACT6
rw
FACT5
rw
FACT4
rw
FACT3
rw
FACT2
rw
FACT1
rw
FACT0
rw
Toggle Fields.

FACT0

Bit 0: Filter active.

FACT1

Bit 1: Filter active.

FACT2

Bit 2: Filter active.

FACT3

Bit 3: Filter active.

FACT4

Bit 4: Filter active.

FACT5

Bit 5: Filter active.

FACT6

Bit 6: Filter active.

FACT7

Bit 7: Filter active.

FACT8

Bit 8: Filter active.

FACT9

Bit 9: Filter active.

FACT10

Bit 10: Filter active.

FACT11

Bit 11: Filter active.

FACT12

Bit 12: Filter active.

FACT13

Bit 13: Filter active.

CRC

0x40023000: CRC calculation unit

3/3 fields covered. Toggle Registers.

DR

Data register

Offset: 0x0, reset: 0xFFFFFFFF, access: read-write

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DR
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DR
rw
Toggle Fields.

DR

Bits 0-31: Data Register.

Allowed values: 0-4294967295

IDR

Independent Data register

Offset: 0x4, reset: 0x00000000, access: read-write

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
IDR
rw
Toggle Fields.

IDR

Bits 0-7: Independent Data register.

Allowed values: 0-255

CR

Control register

Offset: 0x8, reset: 0x00000000, access: write-only

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RESET
w
Toggle Fields.

RESET

Bit 0: Reset bit.

Allowed values:
1: Reset: Resets the CRC calculation unit and sets the data register to 0xFFFF FFFF

DAC

0x40007400: Digital to analog converter

30/30 fields covered. Toggle Registers.

CR

Control register (DAC_CR)

Offset: 0x0, reset: 0x00000000, access: read-write

14/14 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DMAEN2
rw
MAMP2
rw
WAVE2
rw
TSEL2
rw
TEN2
rw
BOFF2
rw
EN2
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DMAEN1
rw
MAMP1
rw
WAVE1
rw
TSEL1
rw
TEN1
rw
BOFF1
rw
EN1
rw
Toggle Fields.

EN1

Bit 0: DAC channel1 enable.

Allowed values:
0: Disabled: DAC channel X disabled
1: Enabled: DAC channel X enabled

BOFF1

Bit 1: DAC channel1 output buffer disable.

Allowed values:
0: Enabled: DAC channel X output buffer enabled
1: Disabled: DAC channel X output buffer disabled

TEN1

Bit 2: DAC channel1 trigger enable.

Allowed values:
0: Disabled: DAC channel X trigger disabled
1: Enabled: DAC channel X trigger enabled

TSEL1

Bits 3-5: DAC channel1 trigger selection.

Allowed values:
0: TIM6_TRGO: Timer 6 TRGO event
1: TIM3_TRGO: Timer 3 TRGO event
2: TIM7_TRGO: Timer 7 TRGO event
3: TIM15_TRGO: Timer 15 TRGO event
4: TIM2_TRGO: Timer 2 TRGO event
6: EXTI9: EXTI line9
7: SOFTWARE: Software trigger

WAVE1

Bits 6-7: DAC channel1 noise/triangle wave generation enable.

Allowed values:
0: Disabled: Wave generation disabled
1: Noise: Noise wave generation enabled
2: Triangle: Triangle wave generation enabled

MAMP1

Bits 8-11: DAC channel1 mask/amplitude selector.

Allowed values: 0-15

DMAEN1

Bit 12: DAC channel1 DMA enable.

Allowed values:
0: Disabled: DAC channel X DMA mode disabled
1: Enabled: DAC channel X DMA mode enabled

EN2

Bit 16: DAC channel2 enable.

Allowed values:
0: Disabled: DAC channel X disabled
1: Enabled: DAC channel X enabled

BOFF2

Bit 17: DAC channel2 output buffer disable.

Allowed values:
0: Enabled: DAC channel X output buffer enabled
1: Disabled: DAC channel X output buffer disabled

TEN2

Bit 18: DAC channel2 trigger enable.

Allowed values:
0: Disabled: DAC channel X trigger disabled
1: Enabled: DAC channel X trigger enabled

TSEL2

Bits 19-21: DAC channel2 trigger selection.

Allowed values:
0: TIM6_TRGO: Timer 6 TRGO event
1: TIM8_TRGO: Timer 8 TRGO event
2: TIM7_TRGO: Timer 7 TRGO event
3: TIM5_TRGO: Timer 5 TRGO event
4: TIM2_TRGO: Timer 2 TRGO event
5: TIM4_TRGO: Timer 4 TRGO event
6: EXTI9: EXTI line9
7: SOFTWARE: Software trigger

WAVE2

Bits 22-23: DAC channel2 noise/triangle wave generation enable.

Allowed values:
0: Disabled: Wave generation disabled
1: Noise: Noise wave generation enabled
2: Triangle: Triangle wave generation enabled

MAMP2

Bits 24-27: DAC channel2 mask/amplitude selector.

Allowed values: 0-15

DMAEN2

Bit 28: DAC channel2 DMA enable.

Allowed values:
0: Disabled: DAC channel X DMA mode disabled
1: Enabled: DAC channel X DMA mode enabled

SWTRIGR

DAC software trigger register (DAC_SWTRIGR)

Offset: 0x4, reset: 0x00000000, access: write-only

2/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SWTRIG2
w
SWTRIG1
w
Toggle Fields.

SWTRIG1

Bit 0: DAC channel1 software trigger.

Allowed values:
0: Disabled: DAC channel X software trigger disabled
1: Enabled: DAC channel X software trigger enabled

SWTRIG2

Bit 1: DAC channel2 software trigger.

Allowed values:
0: Disabled: DAC channel X software trigger disabled
1: Enabled: DAC channel X software trigger enabled

DHR12R1

DAC channel1 12-bit right-aligned data holding register(DAC_DHR12R1)

Offset: 0x8, reset: 0x00000000, access: read-write

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DACC1DHR
rw
Toggle Fields.

DACC1DHR

Bits 0-11: DAC channel1 12-bit right-aligned data.

Allowed values: 0-4096

DHR12L1

DAC channel1 12-bit left aligned data holding register (DAC_DHR12L1)

Offset: 0xC, reset: 0x00000000, access: read-write

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DACC1DHR
rw
Toggle Fields.

DACC1DHR

Bits 4-15: DAC channel1 12-bit left-aligned data.

Allowed values: 0-4096

DHR8R1

DAC channel1 8-bit right aligned data holding register (DAC_DHR8R1)

Offset: 0x10, reset: 0x00000000, access: read-write

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DACC1DHR
rw
Toggle Fields.

DACC1DHR

Bits 0-7: DAC channel1 8-bit right-aligned data.

Allowed values: 0-255

DHR12R2

DAC channel2 12-bit right aligned data holding register (DAC_DHR12R2)

Offset: 0x14, reset: 0x00000000, access: read-write

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DACC2DHR
rw
Toggle Fields.

DACC2DHR

Bits 0-11: DAC channel2 12-bit right-aligned data.

Allowed values: 0-4096

DHR12L2

DAC channel2 12-bit left aligned data holding register (DAC_DHR12L2)

Offset: 0x18, reset: 0x00000000, access: read-write

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DACC2DHR
rw
Toggle Fields.

DACC2DHR

Bits 4-15: DAC channel2 12-bit left-aligned data.

Allowed values: 0-4096

DHR8R2

DAC channel2 8-bit right-aligned data holding register (DAC_DHR8R2)

Offset: 0x1C, reset: 0x00000000, access: read-write

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DACC2DHR
rw
Toggle Fields.

DACC2DHR

Bits 0-7: DAC channel2 8-bit right-aligned data.

Allowed values: 0-255

DHR12RD

Dual DAC 12-bit right-aligned data holding register (DAC_DHR12RD), Bits 31:28 Reserved, Bits 15:12 Reserved

Offset: 0x20, reset: 0x00000000, access: read-write

2/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DACC2DHR
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DACC1DHR
rw
Toggle Fields.

DACC1DHR

Bits 0-11: DAC channel1 12-bit right-aligned data.

Allowed values: 0-4096

DACC2DHR

Bits 16-27: DAC channel2 12-bit right-aligned data.

Allowed values: 0-4096

DHR12LD

DUAL DAC 12-bit left aligned data holding register (DAC_DHR12LD), Bits 19:16 Reserved, Bits 3:0 Reserved

Offset: 0x24, reset: 0x00000000, access: read-write

2/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DACC2DHR
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DACC1DHR
rw
Toggle Fields.

DACC1DHR

Bits 4-15: DAC channel1 12-bit left-aligned data.

Allowed values: 0-4096

DACC2DHR

Bits 20-31: DAC channel2 12-bit right-aligned data.

Allowed values: 0-4096

DHR8RD

DUAL DAC 8-bit right aligned data holding register (DAC_DHR8RD), Bits 31:16 Reserved

Offset: 0x28, reset: 0x00000000, access: read-write

2/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DACC2DHR
rw
DACC1DHR
rw
Toggle Fields.

DACC1DHR

Bits 0-7: DAC channel1 8-bit right-aligned data.

Allowed values: 0-255

DACC2DHR

Bits 8-15: DAC channel2 8-bit right-aligned data.

Allowed values: 0-255

DOR1

DAC channel1 data output register (DAC_DOR1)

Offset: 0x2C, reset: 0x00000000, access: read-only

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DACC1DOR
r
Toggle Fields.

DACC1DOR

Bits 0-11: DAC channel1 data output.

DOR2

DAC channel2 data output register (DAC_DOR2)

Offset: 0x30, reset: 0x00000000, access: read-only

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DACC2DOR
r
Toggle Fields.

DACC2DOR

Bits 0-11: DAC channel2 data output.

DBGMCU

0xE0042000: Debug support

2/21 fields covered. Toggle Registers.

IDCODE

DBGMCU_IDCODE

Offset: 0x0, reset: 0x0, access: read-only

2/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
REV_ID
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DEV_ID
r
Toggle Fields.

DEV_ID

Bits 0-11: DEV_ID.

REV_ID

Bits 16-31: REV_ID.

CR

DBGMCU_CR

Offset: 0x4, reset: 0x0, access: read-write

0/19 fields covered.

DBG_SLEEP

Bit 0: DBG_SLEEP.

DBG_STOP

Bit 1: DBG_STOP.

DBG_STANDBY

Bit 2: DBG_STANDBY.

TRACE_IOEN

Bit 5: TRACE_IOEN.

TRACE_MODE

Bits 6-7: TRACE_MODE.

DBG_IWDG_STOP

Bit 8: DBG_IWDG_STOP.

DBG_WWDG_STOP

Bit 9: DBG_WWDG_STOP.

DBG_TIM1_STOP

Bit 10: DBG_TIM1_STOP.

DBG_TIM2_STOP

Bit 11: DBG_TIM2_STOP.

DBG_TIM3_STOP

Bit 12: DBG_TIM3_STOP.

DBG_TIM4_STOP

Bit 13: DBG_TIM4_STOP.

DBG_CAN1_STOP

Bit 14: DBG_CAN1_STOP.

DBG_I2C1_SMBUS_TIMEOUT

Bit 15: DBG_I2C1_SMBUS_TIMEOUT.

DBG_I2C2_SMBUS_TIMEOUT

Bit 16: DBG_I2C2_SMBUS_TIMEOUT.

DBG_TIM8_STOP

Bit 17: DBG_TIM8_STOP.

DBG_TIM5_STOP

Bit 18: DBG_TIM5_STOP.

DBG_TIM6_STOP

Bit 19: DBG_TIM6_STOP.

DBG_TIM7_STOP

Bit 20: DBG_TIM7_STOP.

DBG_CAN2_STOP

Bit 21: DBG_CAN2_STOP.

DMA1

0x40020000: DMA controller

69/71 fields covered. Toggle Registers.

CR

DMA channel configuration register (DMA_CCR)

Offset: 0x0, reset: 0x00000000, access: read-write

12/12 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MEM2MEM
rw
PL
rw
MSIZE
rw
PSIZE
rw
MINC
rw
PINC
rw
CIRC
rw
DIR
rw
TEIE
rw
HTIE
rw
TCIE
rw
EN
rw
Toggle Fields.

EN

Bit 0: Channel enable.

Allowed values:
0: Disabled: Channel disabled
1: Enabled: Channel enabled

TCIE

Bit 1: Transfer complete interrupt enable.

Allowed values:
0: Disabled: Transfer Complete interrupt disabled
1: Enabled: Transfer Complete interrupt enabled

HTIE

Bit 2: Half Transfer interrupt enable.

Allowed values:
0: Disabled: Half Transfer interrupt disabled
1: Enabled: Half Transfer interrupt enabled

TEIE

Bit 3: Transfer error interrupt enable.

Allowed values:
0: Disabled: Transfer Error interrupt disabled
1: Enabled: Transfer Error interrupt enabled

DIR

Bit 4: Data transfer direction.

Allowed values:
0: FromPeripheral: Read from peripheral
1: FromMemory: Read from memory

CIRC

Bit 5: Circular mode.

Allowed values:
0: Disabled: Circular buffer disabled
1: Enabled: Circular buffer enabled

PINC

Bit 6: Peripheral increment mode.

Allowed values:
0: Disabled: Increment mode disabled
1: Enabled: Increment mode enabled

MINC

Bit 7: Memory increment mode.

Allowed values:
0: Disabled: Increment mode disabled
1: Enabled: Increment mode enabled

PSIZE

Bits 8-9: Peripheral size.

Allowed values:
0: Bits8: 8-bit size
1: Bits16: 16-bit size
2: Bits32: 32-bit size

MSIZE

Bits 10-11: Memory size.

Allowed values:
0: Bits8: 8-bit size
1: Bits16: 16-bit size
2: Bits32: 32-bit size

PL

Bits 12-13: Channel Priority level.

Allowed values:
0: Low: Low priority
1: Medium: Medium priority
2: High: High priority
3: VeryHigh: Very high priority

MEM2MEM

Bit 14: Memory to memory mode.

Allowed values:
0: Disabled: Memory to memory mode disabled
1: Enabled: Memory to memory mode enabled

NDTR

DMA channel 1 number of data register

Offset: 0x4, reset: 0x00000000, access: read-write

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
NDT
rw
Toggle Fields.

NDT

Bits 0-15: Number of data to transfer.

Allowed values: 0-65535

PAR

DMA channel 1 peripheral address register

Offset: 0x8, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
PA
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PA
rw
Toggle Fields.

PA

Bits 0-31: Peripheral address.

MAR

DMA channel 1 memory address register

Offset: 0xC, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
MA
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MA
rw
Toggle Fields.

MA

Bits 0-31: Memory address.

DMA2

0x40020400: DMA controller

69/71 fields covered. Toggle Registers.

CR

DMA channel configuration register (DMA_CCR)

Offset: 0x0, reset: 0x00000000, access: read-write

12/12 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MEM2MEM
rw
PL
rw
MSIZE
rw
PSIZE
rw
MINC
rw
PINC
rw
CIRC
rw
DIR
rw
TEIE
rw
HTIE
rw
TCIE
rw
EN
rw
Toggle Fields.

EN

Bit 0: Channel enable.

Allowed values:
0: Disabled: Channel disabled
1: Enabled: Channel enabled

TCIE

Bit 1: Transfer complete interrupt enable.

Allowed values:
0: Disabled: Transfer Complete interrupt disabled
1: Enabled: Transfer Complete interrupt enabled

HTIE

Bit 2: Half Transfer interrupt enable.

Allowed values:
0: Disabled: Half Transfer interrupt disabled
1: Enabled: Half Transfer interrupt enabled

TEIE

Bit 3: Transfer error interrupt enable.

Allowed values:
0: Disabled: Transfer Error interrupt disabled
1: Enabled: Transfer Error interrupt enabled

DIR

Bit 4: Data transfer direction.

Allowed values:
0: FromPeripheral: Read from peripheral
1: FromMemory: Read from memory

CIRC

Bit 5: Circular mode.

Allowed values:
0: Disabled: Circular buffer disabled
1: Enabled: Circular buffer enabled

PINC

Bit 6: Peripheral increment mode.

Allowed values:
0: Disabled: Increment mode disabled
1: Enabled: Increment mode enabled

MINC

Bit 7: Memory increment mode.

Allowed values:
0: Disabled: Increment mode disabled
1: Enabled: Increment mode enabled

PSIZE

Bits 8-9: Peripheral size.

Allowed values:
0: Bits8: 8-bit size
1: Bits16: 16-bit size
2: Bits32: 32-bit size

MSIZE

Bits 10-11: Memory size.

Allowed values:
0: Bits8: 8-bit size
1: Bits16: 16-bit size
2: Bits32: 32-bit size

PL

Bits 12-13: Channel Priority level.

Allowed values:
0: Low: Low priority
1: Medium: Medium priority
2: High: High priority
3: VeryHigh: Very high priority

MEM2MEM

Bit 14: Memory to memory mode.

Allowed values:
0: Disabled: Memory to memory mode disabled
1: Enabled: Memory to memory mode enabled

NDTR

DMA channel 1 number of data register

Offset: 0x4, reset: 0x00000000, access: read-write

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
NDT
rw
Toggle Fields.

NDT

Bits 0-15: Number of data to transfer.

Allowed values: 0-65535

PAR

DMA channel 1 peripheral address register

Offset: 0x8, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
PA
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PA
rw
Toggle Fields.

PA

Bits 0-31: Peripheral address.

MAR

DMA channel 1 memory address register

Offset: 0xC, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
MA
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MA
rw
Toggle Fields.

MA

Bits 0-31: Memory address.

Ethernet_DMA

0x40029000: Ethernet: DMA controller operation

14/70 fields covered. Toggle Registers.

DMABMR

Ethernet DMA bus mode register

Offset: 0x0, reset: 0x20101, access: read-write

0/10 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
AAB
rw
FPM
rw
USP
rw
RDP
rw
FB
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RTPR
rw
PBL
rw
DSL
rw
DA
rw
SR
rw
Toggle Fields.

SR

Bit 0: Software reset.

DA

Bit 1: DMA Arbitration.

DSL

Bits 2-6: Descriptor skip length.

PBL

Bits 8-13: Programmable burst length.

RTPR

Bits 14-15: Rx Tx priority ratio.

FB

Bit 16: Fixed burst.

RDP

Bits 17-22: Rx DMA PBL.

USP

Bit 23: Use separate PBL.

FPM

Bit 24: 4xPBL mode.

AAB

Bit 25: Address-aligned beats.

DMATPDR

Ethernet DMA transmit poll demand register

Offset: 0x4, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
TPD
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TPD
rw
Toggle Fields.

TPD

Bits 0-31: Transmit poll demand.

DMARPDR

EHERNET DMA receive poll demand register

Offset: 0x8, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
RPD
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RPD
rw
Toggle Fields.

RPD

Bits 0-31: Receive poll demand.

DMARDLAR

Ethernet DMA receive descriptor list address register

Offset: 0xC, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
SRL
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SRL
rw
Toggle Fields.

SRL

Bits 0-31: Start of receive list.

DMATDLAR

Ethernet DMA transmit descriptor list address register

Offset: 0x10, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
STL
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
STL
rw
Toggle Fields.

STL

Bits 0-31: Start of transmit list.

DMASR

Ethernet DMA status register

Offset: 0x14, reset: 0x00000000, access: Unspecified

6/21 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
TSTS
r
PMTS
r
MMCS
r
EBS
r
TPS
r
RPS
r
NIS
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
AIS
rw
ERS
rw
FBES
rw
ETS
rw
PWTS
rw
RPSS
rw
RBUS
rw
RS
rw
TUS
rw
ROS
rw
TJTS
rw
TBUS
rw
TPSS
rw
TS
rw
Toggle Fields.

TS

Bit 0: Transmit status.

TPSS

Bit 1: Transmit process stopped status.

TBUS

Bit 2: Transmit buffer unavailable status.

TJTS

Bit 3: Transmit jabber timeout status.

ROS

Bit 4: Receive overflow status.

TUS

Bit 5: Transmit underflow status.

RS

Bit 6: Receive status.

RBUS

Bit 7: Receive buffer unavailable status.

RPSS

Bit 8: Receive process stopped status.

PWTS

Bit 9: Receive watchdog timeout status.

ETS

Bit 10: Early transmit status.

FBES

Bit 13: Fatal bus error status.

ERS

Bit 14: Early receive status.

AIS

Bit 15: Abnormal interrupt summary.

NIS

Bit 16: Normal interrupt summary.

RPS

Bits 17-19: Receive process state.

TPS

Bits 20-22: Transmit process state.

EBS

Bits 23-25: Error bits status.

MMCS

Bit 27: MMC status.

PMTS

Bit 28: PMT status.

TSTS

Bit 29: Time stamp trigger status.

DMAOMR

Ethernet DMA operation mode register

Offset: 0x18, reset: 0x00000000, access: read-write

0/12 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DTCEFD
rw
RSF
rw
DFRF
rw
TSF
rw
FTF
rw
TTC
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TTC
rw
ST
rw
FEF
rw
FUGF
rw
RTC
rw
OSF
rw
SR
rw
Toggle Fields.

SR

Bit 1: SR.

OSF

Bit 2: OSF.

RTC

Bits 3-4: RTC.

FUGF

Bit 6: FUGF.

FEF

Bit 7: FEF.

ST

Bit 13: ST.

TTC

Bits 14-16: TTC.

FTF

Bit 20: FTF.

TSF

Bit 21: TSF.

DFRF

Bit 24: DFRF.

RSF

Bit 25: RSF.

DTCEFD

Bit 26: DTCEFD.

DMAIER

Ethernet DMA interrupt enable register

Offset: 0x1C, reset: 0x00000000, access: read-write

0/15 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
NISE
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
AISE
rw
ERIE
rw
FBEIE
rw
ETIE
rw
RWTIE
rw
RPSIE
rw
RBUIE
rw
RIE
rw
TUIE
rw
ROIE
rw
TJTIE
rw
TBUIE
rw
TPSIE
rw
TIE
rw
Toggle Fields.

TIE

Bit 0: Transmit interrupt enable.

TPSIE

Bit 1: Transmit process stopped interrupt enable.

TBUIE

Bit 2: Transmit buffer unavailable interrupt enable.

TJTIE

Bit 3: Transmit jabber timeout interrupt enable.

ROIE

Bit 4: Overflow interrupt enable.

TUIE

Bit 5: Underflow interrupt enable.

RIE

Bit 6: Receive interrupt enable.

RBUIE

Bit 7: Receive buffer unavailable interrupt enable.

RPSIE

Bit 8: Receive process stopped interrupt enable.

RWTIE

Bit 9: receive watchdog timeout interrupt enable.

ETIE

Bit 10: Early transmit interrupt enable.

FBEIE

Bit 13: Fatal bus error interrupt enable.

ERIE

Bit 14: Early receive interrupt enable.

AISE

Bit 15: Abnormal interrupt summary enable.

NISE

Bit 16: Normal interrupt summary enable.

DMAMFBOCR

Ethernet DMA missed frame and buffer overflow counter register

Offset: 0x20, reset: 0x00000000, access: read-only

4/4 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
OFOC
r
MFA
r
OMFC
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MFC
r
Toggle Fields.

MFC

Bits 0-15: Missed frames by the controller.

OMFC

Bit 16: Overflow bit for missed frame counter.

MFA

Bits 17-27: Missed frames by the application.

OFOC

Bit 28: Overflow bit for FIFO overflow counter.

DMACHTDR

Ethernet DMA current host transmit descriptor register

Offset: 0x48, reset: 0x00000000, access: read-only

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
HTDAP
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
HTDAP
r
Toggle Fields.

HTDAP

Bits 0-31: Host transmit descriptor address pointer.

DMACHRDR

Ethernet DMA current host receive descriptor register

Offset: 0x4C, reset: 0x00000000, access: read-only

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
HRDAP
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
HRDAP
r
Toggle Fields.

HRDAP

Bits 0-31: Host receive descriptor address pointer.

DMACHTBAR

Ethernet DMA current host transmit buffer address register

Offset: 0x50, reset: 0x00000000, access: read-only

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
HTBAP
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
HTBAP
r
Toggle Fields.

HTBAP

Bits 0-31: Host transmit buffer address pointer.

DMACHRBAR

Ethernet DMA current host receive buffer address register

Offset: 0x54, reset: 0x00000000, access: read-only

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
HRBAP
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
HRBAP
r
Toggle Fields.

HRBAP

Bits 0-31: Host receive buffer address pointer.

Ethernet_MAC

0x40028000: Ethernet: media access control

1/76 fields covered. Toggle Registers.

MACCR

Ethernet MAC configuration register (ETH_MACCR)

Offset: 0x0, reset: 0x00008000, access: read-write

0/15 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
WD
rw
JD
rw
IFG
rw
CSD
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FES
rw
ROD
rw
LM
rw
DM
rw
IPCO
rw
RD
rw
APCS
rw
BL
rw
DC
rw
TE
rw
RE
rw
Toggle Fields.

RE

Bit 2: Receiver enable.

TE

Bit 3: Transmitter enable.

DC

Bit 4: Deferral check.

BL

Bits 5-6: Back-off limit.

APCS

Bit 7: Automatic pad/CRC stripping.

RD

Bit 9: Retry disable.

IPCO

Bit 10: IPv4 checksum offload.

DM

Bit 11: Duplex mode.

LM

Bit 12: Loopback mode.

ROD

Bit 13: Receive own disable.

FES

Bit 14: Fast Ethernet speed.

CSD

Bit 16: Carrier sense disable.

IFG

Bits 17-19: Interframe gap.

JD

Bit 22: Jabber disable.

WD

Bit 23: Watchdog disable.

MACFFR

Ethernet MAC frame filter register (ETH_MACCFFR)

Offset: 0x4, reset: 0x00000000, access: read-write

0/11 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
RA
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
HPF
rw
SAF
rw
SAIF
rw
PCF
rw
BFD
rw
PAM
rw
DAIF
rw
HM
rw
HU
rw
PM
rw
Toggle Fields.

PM

Bit 0: Promiscuous mode.

HU

Bit 1: Hash unicast.

HM

Bit 2: Hash multicast.

DAIF

Bit 3: Destination address inverse filtering.

PAM

Bit 4: Pass all multicast.

BFD

Bit 5: Broadcast frames disable.

PCF

Bits 6-7: Pass control frames.

SAIF

Bit 8: Source address inverse filtering.

SAF

Bit 9: Source address filter.

HPF

Bit 10: Hash or perfect filter.

RA

Bit 31: Receive all.

MACHTHR

Ethernet MAC hash table high register

Offset: 0x8, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
HTH
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
HTH
rw
Toggle Fields.

HTH

Bits 0-31: Hash table high.

MACHTLR

Ethernet MAC hash table low register

Offset: 0xC, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
HTL
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
HTL
rw
Toggle Fields.

HTL

Bits 0-31: Hash table low.

MACMIIAR

Ethernet MAC MII address register (ETH_MACMIIAR)

Offset: 0x10, reset: 0x00000000, access: read-write

0/5 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PA
rw
MR
rw
CR
rw
MW
rw
MB
rw
Toggle Fields.

MB

Bit 0: MII busy.

MW

Bit 1: MII write.

CR

Bits 2-4: Clock range.

MR

Bits 6-10: MII register.

PA

Bits 11-15: PHY address.

MACMIIDR

Ethernet MAC MII data register (ETH_MACMIIDR)

Offset: 0x14, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MD
rw
Toggle Fields.

MD

Bits 0-15: MII data.

MACFCR

Ethernet MAC flow control register (ETH_MACFCR)

Offset: 0x18, reset: 0x00000000, access: read-write

0/7 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
PT
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ZQPD
rw
PLT
rw
UPFD
rw
RFCE
rw
TFCE
rw
FCB_BPA
rw
Toggle Fields.

FCB_BPA

Bit 0: Flow control busy/back pressure activate.

TFCE

Bit 1: Transmit flow control enable.

RFCE

Bit 2: Receive flow control enable.

UPFD

Bit 3: Unicast pause frame detect.

PLT

Bits 4-5: Pause low threshold.

ZQPD

Bit 7: Zero-quanta pause disable.

PT

Bits 16-31: Pass control frames.

MACVLANTR

Ethernet MAC VLAN tag register (ETH_MACVLANTR)

Offset: 0x1C, reset: 0x00000000, access: read-write

0/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
VLANTC
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
VLANTI
rw
Toggle Fields.

VLANTI

Bits 0-15: VLAN tag identifier (for receive frames).

VLANTC

Bit 16: 12-bit VLAN tag comparison.

MACRWUFFR

Ethernet MAC remote wakeup frame filter register (ETH_MACRWUFFR)

Offset: 0x28, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Toggle Fields.

MACPMTCSR

Ethernet MAC PMT control and status register (ETH_MACPMTCSR)

Offset: 0x2C, reset: 0x00000000, access: read-write

0/7 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
WFFRPR
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
GU
rw
WFR
rw
MPR
rw
WFE
rw
MPE
rw
PD
rw
Toggle Fields.

PD

Bit 0: Power down.

MPE

Bit 1: Magic Packet enable.

WFE

Bit 2: Wakeup frame enable.

MPR

Bit 5: Magic packet received.

WFR

Bit 6: Wakeup frame received.

GU

Bit 9: Global unicast.

WFFRPR

Bit 31: Wakeup frame filter register pointer reset.

MACSR

Ethernet MAC interrupt status register (ETH_MACSR)

Offset: 0x38, reset: 0x00000000, access: read-write

0/5 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TSTS
rw
MMCTS
rw
MMCRS
rw
MMCS
rw
PMTS
rw
Toggle Fields.

PMTS

Bit 3: PMT status.

MMCS

Bit 4: MMC status.

MMCRS

Bit 5: MMC receive status.

MMCTS

Bit 6: MMC transmit status.

TSTS

Bit 9: Time stamp trigger status.

MACIMR

Ethernet MAC interrupt mask register (ETH_MACIMR)

Offset: 0x3C, reset: 0x00000000, access: read-write

0/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TSTIM
rw
PMTIM
rw
Toggle Fields.

PMTIM

Bit 3: PMT interrupt mask.

TSTIM

Bit 9: Time stamp trigger interrupt mask.

MACA0HR

Ethernet MAC address 0 high register (ETH_MACA0HR)

Offset: 0x40, reset: 0x0010FFFF, access: Unspecified

1/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
MO
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MACA0H
rw
Toggle Fields.

MACA0H

Bits 0-15: MAC address0 high.

MO

Bit 31: Always 1.

MACA0LR

Ethernet MAC address 0 low register

Offset: 0x44, reset: 0xFFFFFFFF, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
MACA0L
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MACA0L
rw
Toggle Fields.

MACA0L

Bits 0-31: MAC address0 low.

MACA1HR

Ethernet MAC address 1 high register (ETH_MACA1HR)

Offset: 0x48, reset: 0x0000FFFF, access: read-write

0/4 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
AE
rw
SA
rw
MBC
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MACA1H
rw
Toggle Fields.

MACA1H

Bits 0-15: MAC address1 high.

MBC

Bits 24-29: Mask byte control.

SA

Bit 30: Source address.

AE

Bit 31: Address enable.

MACA1LR

Ethernet MAC address1 low register

Offset: 0x4C, reset: 0xFFFFFFFF, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
MACA1L
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MACA1L
rw
Toggle Fields.

MACA1L

Bits 0-31: MAC address1 low.

MACA2HR

Ethernet MAC address 2 high register (ETH_MACA2HR)

Offset: 0x50, reset: 0x0050, access: read-write

0/4 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
AE
rw
SA
rw
MBC
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ETH_MACA2HR
rw
Toggle Fields.

ETH_MACA2HR

Bits 0-15: Ethernet MAC address 2 high register.

MBC

Bits 24-29: Mask byte control.

SA

Bit 30: Source address.

AE

Bit 31: Address enable.

MACA2LR

Ethernet MAC address 2 low register

Offset: 0x54, reset: 0xFFFFFFFF, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
MACA2L
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MACA2L
rw
Toggle Fields.

MACA2L

Bits 0-30: MAC address2 low.

MACA3HR

Ethernet MAC address 3 high register (ETH_MACA3HR)

Offset: 0x58, reset: 0x0000FFFF, access: read-write

0/4 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
AE
rw
SA
rw
MBC
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MACA3H
rw
Toggle Fields.

MACA3H

Bits 0-15: MAC address3 high.

MBC

Bits 24-29: Mask byte control.

SA

Bit 30: Source address.

AE

Bit 31: Address enable.

MACA3LR

Ethernet MAC address 3 low register

Offset: 0x5C, reset: 0xFFFFFFFF, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
MBCA3L
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MBCA3L
rw
Toggle Fields.

MBCA3L

Bits 0-31: MAC address3 low.

Ethernet_MMC

0x40028100: Ethernet: MAC management counters

6/22 fields covered. Toggle Registers.

MMCCR

Ethernet MMC control register (ETH_MMCCR)

Offset: 0x0, reset: 0x00000000, access: read-write

0/4 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
MCF
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ROR
rw
CSR
rw
CR
rw
Toggle Fields.

CR

Bit 0: Counter reset.

CSR

Bit 1: Counter stop rollover.

ROR

Bit 2: Reset on read.

MCF

Bit 31: MMC counter freeze.

MMCRIR

Ethernet MMC receive interrupt register (ETH_MMCRIR)

Offset: 0x4, reset: 0x00000000, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
RGUFS
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RFAES
rw
RFCES
rw
Toggle Fields.

RFCES

Bit 5: Received frames CRC error status.

RFAES

Bit 6: Received frames alignment error status.

RGUFS

Bit 17: Received Good Unicast Frames Status.

MMCTIR

Ethernet MMC transmit interrupt register (ETH_MMCTIR)

Offset: 0x8, reset: 0x00000000, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
TGFS
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TGFMSCS
rw
TGFSCS
rw
Toggle Fields.

TGFSCS

Bit 14: Transmitted good frames single collision status.

TGFMSCS

Bit 15: Transmitted good frames more single collision status.

TGFS

Bit 21: Transmitted good frames status.

MMCRIMR

Ethernet MMC receive interrupt mask register (ETH_MMCRIMR)

Offset: 0xC, reset: 0x00000000, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
RGUFM
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RFAEM
rw
RFCEM
rw
Toggle Fields.

RFCEM

Bit 5: Received frame CRC error mask.

RFAEM

Bit 6: Received frames alignment error mask.

RGUFM

Bit 17: Received good unicast frames mask.

MMCTIMR

Ethernet MMC transmit interrupt mask register (ETH_MMCTIMR)

Offset: 0x10, reset: 0x00000000, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
TGFM
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TGFMSCM
rw
TGFSCM
rw
Toggle Fields.

TGFSCM

Bit 14: Transmitted good frames single collision mask.

TGFMSCM

Bit 15: Transmitted good frames more single collision mask.

TGFM

Bit 21: Transmitted good frames mask.

MMCTGFSCCR

Ethernet MMC transmitted good frames after a single collision counter

Offset: 0x4C, reset: 0x00000000, access: read-only

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
TGFSCC
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TGFSCC
r
Toggle Fields.

TGFSCC

Bits 0-31: Transmitted good frames after a single collision counter.

MMCTGFMSCCR

Ethernet MMC transmitted good frames after more than a single collision

Offset: 0x50, reset: 0x00000000, access: read-only

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
TGFMSCC
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TGFMSCC
r
Toggle Fields.

TGFMSCC

Bits 0-31: Transmitted good frames after more than a single collision counter.

MMCTGFCR

Ethernet MMC transmitted good frames counter register

Offset: 0x68, reset: 0x00000000, access: read-only

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
TGFC
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TGFC
r
Toggle Fields.

TGFC

Bits 0-31: Transmitted good frames counter.

MMCRFCECR

Ethernet MMC received frames with CRC error counter register

Offset: 0x94, reset: 0x00000000, access: read-only

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
RFCFC
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RFCFC
r
Toggle Fields.

RFCFC

Bits 0-31: Received frames with CRC error counter.

MMCRFAECR

Ethernet MMC received frames with alignment error counter register

Offset: 0x98, reset: 0x00000000, access: read-only

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
RFAEC
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RFAEC
r
Toggle Fields.

RFAEC

Bits 0-31: Received frames with alignment error counter.

MMCRGUFCR

MMC received good unicast frames counter register

Offset: 0xC4, reset: 0x00000000, access: read-only

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
RGUFC
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RGUFC
r
Toggle Fields.

RGUFC

Bits 0-31: Received good unicast frames counter.

Ethernet_PTP

0x40028700: Ethernet: Precision time protocol

3/16 fields covered. Toggle Registers.

PTPTSCR

Ethernet PTP time stamp control register (ETH_PTPTSCR)

Offset: 0x0, reset: 0x00000000, access: read-write

0/6 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TSARU
rw
TSITE
rw
TSSTU
rw
TSSTI
rw
TSFCU
rw
TSE
rw
Toggle Fields.

TSE

Bit 0: Time stamp enable.

TSFCU

Bit 1: Time stamp fine or coarse update.

TSSTI

Bit 2: Time stamp system time initialize.

TSSTU

Bit 3: Time stamp system time update.

TSITE

Bit 4: Time stamp interrupt trigger enable.

TSARU

Bit 5: Time stamp addend register update.

PTPSSIR

Ethernet PTP subsecond increment register

Offset: 0x4, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
STSSI
rw
Toggle Fields.

STSSI

Bits 0-7: System time subsecond increment.

PTPTSHR

Ethernet PTP time stamp high register

Offset: 0x8, reset: 0x00000000, access: read-only

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
STS
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
STS
r
Toggle Fields.

STS

Bits 0-31: System time second.

PTPTSLR

Ethernet PTP time stamp low register (ETH_PTPTSLR)

Offset: 0xC, reset: 0x00000000, access: read-only

2/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
STPNS
r
STSS
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
STSS
r
Toggle Fields.

STSS

Bits 0-30: System time subseconds.

STPNS

Bit 31: System time positive or negative sign.

PTPTSHUR

Ethernet PTP time stamp high update register

Offset: 0x10, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
TSUS
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TSUS
rw
Toggle Fields.

TSUS

Bits 0-31: Time stamp update second.

PTPTSLUR

Ethernet PTP time stamp low update register (ETH_PTPTSLUR)

Offset: 0x14, reset: 0x00000000, access: read-write

0/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
TSUPNS
rw
TSUSS
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TSUSS
rw
Toggle Fields.

TSUSS

Bits 0-30: Time stamp update subseconds.

TSUPNS

Bit 31: Time stamp update positive or negative sign.

PTPTSAR

Ethernet PTP time stamp addend register

Offset: 0x18, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
TSA
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TSA
rw
Toggle Fields.

TSA

Bits 0-31: Time stamp addend.

PTPTTHR

Ethernet PTP target time high register

Offset: 0x1C, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
TTSH
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TTSH
rw
Toggle Fields.

TTSH

Bits 0-31: Target time stamp high.

PTPTTLR

Ethernet PTP target time low register

Offset: 0x20, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
TTSL
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TTSL
rw
Toggle Fields.

TTSL

Bits 0-31: Target time stamp low.

EXTI

0x40010400: EXTI

114/114 fields covered. Toggle Registers.

IMR

Interrupt mask register (EXTI_IMR)

Offset: 0x0, reset: 0x00000000, access: read-write

19/19 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
MR18
rw
MR17
rw
MR16
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MR15
rw
MR14
rw
MR13
rw
MR12
rw
MR11
rw
MR10
rw
MR9
rw
MR8
rw
MR7
rw
MR6
rw
MR5
rw
MR4
rw
MR3
rw
MR2
rw
MR1
rw
MR0
rw
Toggle Fields.

MR0

Bit 0: Interrupt Mask on line 0.

Allowed values:
0: Masked: Interrupt request line is masked
1: Unmasked: Interrupt request line is unmasked

MR1

Bit 1: Interrupt Mask on line 1.

Allowed values:
0: Masked: Interrupt request line is masked
1: Unmasked: Interrupt request line is unmasked

MR2

Bit 2: Interrupt Mask on line 2.

Allowed values:
0: Masked: Interrupt request line is masked
1: Unmasked: Interrupt request line is unmasked

MR3

Bit 3: Interrupt Mask on line 3.

Allowed values:
0: Masked: Interrupt request line is masked
1: Unmasked: Interrupt request line is unmasked

MR4

Bit 4: Interrupt Mask on line 4.

Allowed values:
0: Masked: Interrupt request line is masked
1: Unmasked: Interrupt request line is unmasked

MR5

Bit 5: Interrupt Mask on line 5.

Allowed values:
0: Masked: Interrupt request line is masked
1: Unmasked: Interrupt request line is unmasked

MR6

Bit 6: Interrupt Mask on line 6.

Allowed values:
0: Masked: Interrupt request line is masked
1: Unmasked: Interrupt request line is unmasked

MR7

Bit 7: Interrupt Mask on line 7.

Allowed values:
0: Masked: Interrupt request line is masked
1: Unmasked: Interrupt request line is unmasked

MR8

Bit 8: Interrupt Mask on line 8.

Allowed values:
0: Masked: Interrupt request line is masked
1: Unmasked: Interrupt request line is unmasked

MR9

Bit 9: Interrupt Mask on line 9.

Allowed values:
0: Masked: Interrupt request line is masked
1: Unmasked: Interrupt request line is unmasked

MR10

Bit 10: Interrupt Mask on line 10.

Allowed values:
0: Masked: Interrupt request line is masked
1: Unmasked: Interrupt request line is unmasked

MR11

Bit 11: Interrupt Mask on line 11.

Allowed values:
0: Masked: Interrupt request line is masked
1: Unmasked: Interrupt request line is unmasked

MR12

Bit 12: Interrupt Mask on line 12.

Allowed values:
0: Masked: Interrupt request line is masked
1: Unmasked: Interrupt request line is unmasked

MR13

Bit 13: Interrupt Mask on line 13.

Allowed values:
0: Masked: Interrupt request line is masked
1: Unmasked: Interrupt request line is unmasked

MR14

Bit 14: Interrupt Mask on line 14.

Allowed values:
0: Masked: Interrupt request line is masked
1: Unmasked: Interrupt request line is unmasked

MR15

Bit 15: Interrupt Mask on line 15.

Allowed values:
0: Masked: Interrupt request line is masked
1: Unmasked: Interrupt request line is unmasked

MR16

Bit 16: Interrupt Mask on line 16.

Allowed values:
0: Masked: Interrupt request line is masked
1: Unmasked: Interrupt request line is unmasked

MR17

Bit 17: Interrupt Mask on line 17.

Allowed values:
0: Masked: Interrupt request line is masked
1: Unmasked: Interrupt request line is unmasked

MR18

Bit 18: Interrupt Mask on line 18.

Allowed values:
0: Masked: Interrupt request line is masked
1: Unmasked: Interrupt request line is unmasked

EMR

Event mask register (EXTI_EMR)

Offset: 0x4, reset: 0x00000000, access: read-write

19/19 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
MR18
rw
MR17
rw
MR16
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MR15
rw
MR14
rw
MR13
rw
MR12
rw
MR11
rw
MR10
rw
MR9
rw
MR8
rw
MR7
rw
MR6
rw
MR5
rw
MR4
rw
MR3
rw
MR2
rw
MR1
rw
MR0
rw
Toggle Fields.

MR0

Bit 0: Event Mask on line 0.

Allowed values:
0: Masked: Interrupt request line is masked
1: Unmasked: Interrupt request line is unmasked

MR1

Bit 1: Event Mask on line 1.

Allowed values:
0: Masked: Interrupt request line is masked
1: Unmasked: Interrupt request line is unmasked

MR2

Bit 2: Event Mask on line 2.

Allowed values:
0: Masked: Interrupt request line is masked
1: Unmasked: Interrupt request line is unmasked

MR3

Bit 3: Event Mask on line 3.

Allowed values:
0: Masked: Interrupt request line is masked
1: Unmasked: Interrupt request line is unmasked

MR4

Bit 4: Event Mask on line 4.

Allowed values:
0: Masked: Interrupt request line is masked
1: Unmasked: Interrupt request line is unmasked

MR5

Bit 5: Event Mask on line 5.

Allowed values:
0: Masked: Interrupt request line is masked
1: Unmasked: Interrupt request line is unmasked

MR6

Bit 6: Event Mask on line 6.

Allowed values:
0: Masked: Interrupt request line is masked
1: Unmasked: Interrupt request line is unmasked

MR7

Bit 7: Event Mask on line 7.

Allowed values:
0: Masked: Interrupt request line is masked
1: Unmasked: Interrupt request line is unmasked

MR8

Bit 8: Event Mask on line 8.

Allowed values:
0: Masked: Interrupt request line is masked
1: Unmasked: Interrupt request line is unmasked

MR9

Bit 9: Event Mask on line 9.

Allowed values:
0: Masked: Interrupt request line is masked
1: Unmasked: Interrupt request line is unmasked

MR10

Bit 10: Event Mask on line 10.

Allowed values:
0: Masked: Interrupt request line is masked
1: Unmasked: Interrupt request line is unmasked

MR11

Bit 11: Event Mask on line 11.

Allowed values:
0: Masked: Interrupt request line is masked
1: Unmasked: Interrupt request line is unmasked

MR12

Bit 12: Event Mask on line 12.

Allowed values:
0: Masked: Interrupt request line is masked
1: Unmasked: Interrupt request line is unmasked

MR13

Bit 13: Event Mask on line 13.

Allowed values:
0: Masked: Interrupt request line is masked
1: Unmasked: Interrupt request line is unmasked

MR14

Bit 14: Event Mask on line 14.

Allowed values:
0: Masked: Interrupt request line is masked
1: Unmasked: Interrupt request line is unmasked

MR15

Bit 15: Event Mask on line 15.

Allowed values:
0: Masked: Interrupt request line is masked
1: Unmasked: Interrupt request line is unmasked

MR16

Bit 16: Event Mask on line 16.

Allowed values:
0: Masked: Interrupt request line is masked
1: Unmasked: Interrupt request line is unmasked

MR17

Bit 17: Event Mask on line 17.

Allowed values:
0: Masked: Interrupt request line is masked
1: Unmasked: Interrupt request line is unmasked

MR18

Bit 18: Event Mask on line 18.

Allowed values:
0: Masked: Interrupt request line is masked
1: Unmasked: Interrupt request line is unmasked

RTSR

Rising Trigger selection register (EXTI_RTSR)

Offset: 0x8, reset: 0x00000000, access: read-write

19/19 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
TR18
rw
TR17
rw
TR16
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TR15
rw
TR14
rw
TR13
rw
TR12
rw
TR11
rw
TR10
rw
TR9
rw
TR8
rw
TR7
rw
TR6
rw
TR5
rw
TR4
rw
TR3
rw
TR2
rw
TR1
rw
TR0
rw
Toggle Fields.

TR0

Bit 0: Rising trigger event configuration of line 0.

Allowed values:
0: Disabled: Rising edge trigger is disabled
1: Enabled: Rising edge trigger is enabled

TR1

Bit 1: Rising trigger event configuration of line 1.

Allowed values:
0: Disabled: Rising edge trigger is disabled
1: Enabled: Rising edge trigger is enabled

TR2

Bit 2: Rising trigger event configuration of line 2.

Allowed values:
0: Disabled: Rising edge trigger is disabled
1: Enabled: Rising edge trigger is enabled

TR3

Bit 3: Rising trigger event configuration of line 3.

Allowed values:
0: Disabled: Rising edge trigger is disabled
1: Enabled: Rising edge trigger is enabled

TR4

Bit 4: Rising trigger event configuration of line 4.

Allowed values:
0: Disabled: Rising edge trigger is disabled
1: Enabled: Rising edge trigger is enabled

TR5

Bit 5: Rising trigger event configuration of line 5.

Allowed values:
0: Disabled: Rising edge trigger is disabled
1: Enabled: Rising edge trigger is enabled

TR6

Bit 6: Rising trigger event configuration of line 6.

Allowed values:
0: Disabled: Rising edge trigger is disabled
1: Enabled: Rising edge trigger is enabled

TR7

Bit 7: Rising trigger event configuration of line 7.

Allowed values:
0: Disabled: Rising edge trigger is disabled
1: Enabled: Rising edge trigger is enabled

TR8

Bit 8: Rising trigger event configuration of line 8.

Allowed values:
0: Disabled: Rising edge trigger is disabled
1: Enabled: Rising edge trigger is enabled

TR9

Bit 9: Rising trigger event configuration of line 9.

Allowed values:
0: Disabled: Rising edge trigger is disabled
1: Enabled: Rising edge trigger is enabled

TR10

Bit 10: Rising trigger event configuration of line 10.

Allowed values:
0: Disabled: Rising edge trigger is disabled
1: Enabled: Rising edge trigger is enabled

TR11

Bit 11: Rising trigger event configuration of line 11.

Allowed values:
0: Disabled: Rising edge trigger is disabled
1: Enabled: Rising edge trigger is enabled

TR12

Bit 12: Rising trigger event configuration of line 12.

Allowed values:
0: Disabled: Rising edge trigger is disabled
1: Enabled: Rising edge trigger is enabled

TR13

Bit 13: Rising trigger event configuration of line 13.

Allowed values:
0: Disabled: Rising edge trigger is disabled
1: Enabled: Rising edge trigger is enabled

TR14

Bit 14: Rising trigger event configuration of line 14.

Allowed values:
0: Disabled: Rising edge trigger is disabled
1: Enabled: Rising edge trigger is enabled

TR15

Bit 15: Rising trigger event configuration of line 15.

Allowed values:
0: Disabled: Rising edge trigger is disabled
1: Enabled: Rising edge trigger is enabled

TR16

Bit 16: Rising trigger event configuration of line 16.

Allowed values:
0: Disabled: Rising edge trigger is disabled
1: Enabled: Rising edge trigger is enabled

TR17

Bit 17: Rising trigger event configuration of line 17.

Allowed values:
0: Disabled: Rising edge trigger is disabled
1: Enabled: Rising edge trigger is enabled

TR18

Bit 18: Rising trigger event configuration of line 18.

Allowed values:
0: Disabled: Rising edge trigger is disabled
1: Enabled: Rising edge trigger is enabled

FTSR

Falling Trigger selection register (EXTI_FTSR)

Offset: 0xC, reset: 0x00000000, access: read-write

19/19 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
TR18
rw
TR17
rw
TR16
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TR15
rw
TR14
rw
TR13
rw
TR12
rw
TR11
rw
TR10
rw
TR9
rw
TR8
rw
TR7
rw
TR6
rw
TR5
rw
TR4
rw
TR3
rw
TR2
rw
TR1
rw
TR0
rw
Toggle Fields.

TR0

Bit 0: Falling trigger event configuration of line 0.

Allowed values:
0: Disabled: Falling edge trigger is disabled
1: Enabled: Falling edge trigger is enabled

TR1

Bit 1: Falling trigger event configuration of line 1.

Allowed values:
0: Disabled: Falling edge trigger is disabled
1: Enabled: Falling edge trigger is enabled

TR2

Bit 2: Falling trigger event configuration of line 2.

Allowed values:
0: Disabled: Falling edge trigger is disabled
1: Enabled: Falling edge trigger is enabled

TR3

Bit 3: Falling trigger event configuration of line 3.

Allowed values:
0: Disabled: Falling edge trigger is disabled
1: Enabled: Falling edge trigger is enabled

TR4

Bit 4: Falling trigger event configuration of line 4.

Allowed values:
0: Disabled: Falling edge trigger is disabled
1: Enabled: Falling edge trigger is enabled

TR5

Bit 5: Falling trigger event configuration of line 5.

Allowed values:
0: Disabled: Falling edge trigger is disabled
1: Enabled: Falling edge trigger is enabled

TR6

Bit 6: Falling trigger event configuration of line 6.

Allowed values:
0: Disabled: Falling edge trigger is disabled
1: Enabled: Falling edge trigger is enabled

TR7

Bit 7: Falling trigger event configuration of line 7.

Allowed values:
0: Disabled: Falling edge trigger is disabled
1: Enabled: Falling edge trigger is enabled

TR8

Bit 8: Falling trigger event configuration of line 8.

Allowed values:
0: Disabled: Falling edge trigger is disabled
1: Enabled: Falling edge trigger is enabled

TR9

Bit 9: Falling trigger event configuration of line 9.

Allowed values:
0: Disabled: Falling edge trigger is disabled
1: Enabled: Falling edge trigger is enabled

TR10

Bit 10: Falling trigger event configuration of line 10.

Allowed values:
0: Disabled: Falling edge trigger is disabled
1: Enabled: Falling edge trigger is enabled

TR11

Bit 11: Falling trigger event configuration of line 11.

Allowed values:
0: Disabled: Falling edge trigger is disabled
1: Enabled: Falling edge trigger is enabled

TR12

Bit 12: Falling trigger event configuration of line 12.

Allowed values:
0: Disabled: Falling edge trigger is disabled
1: Enabled: Falling edge trigger is enabled

TR13

Bit 13: Falling trigger event configuration of line 13.

Allowed values:
0: Disabled: Falling edge trigger is disabled
1: Enabled: Falling edge trigger is enabled

TR14

Bit 14: Falling trigger event configuration of line 14.

Allowed values:
0: Disabled: Falling edge trigger is disabled
1: Enabled: Falling edge trigger is enabled

TR15

Bit 15: Falling trigger event configuration of line 15.

Allowed values:
0: Disabled: Falling edge trigger is disabled
1: Enabled: Falling edge trigger is enabled

TR16

Bit 16: Falling trigger event configuration of line 16.

Allowed values:
0: Disabled: Falling edge trigger is disabled
1: Enabled: Falling edge trigger is enabled

TR17

Bit 17: Falling trigger event configuration of line 17.

Allowed values:
0: Disabled: Falling edge trigger is disabled
1: Enabled: Falling edge trigger is enabled

TR18

Bit 18: Falling trigger event configuration of line 18.

Allowed values:
0: Disabled: Falling edge trigger is disabled
1: Enabled: Falling edge trigger is enabled

SWIER

Software interrupt event register (EXTI_SWIER)

Offset: 0x10, reset: 0x00000000, access: read-write

19/19 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
SWIER18
rw
SWIER17
rw
SWIER16
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SWIER15
rw
SWIER14
rw
SWIER13
rw
SWIER12
rw
SWIER11
rw
SWIER10
rw
SWIER9
rw
SWIER8
rw
SWIER7
rw
SWIER6
rw
SWIER5
rw
SWIER4
rw
SWIER3
rw
SWIER2
rw
SWIER1
rw
SWIER0
rw
Toggle Fields.

SWIER0

Bit 0: Software Interrupt on line 0.

Allowed values:
1: Pend: Generates an interrupt request

SWIER1

Bit 1: Software Interrupt on line 1.

Allowed values:
1: Pend: Generates an interrupt request

SWIER2

Bit 2: Software Interrupt on line 2.

Allowed values:
1: Pend: Generates an interrupt request

SWIER3

Bit 3: Software Interrupt on line 3.

Allowed values:
1: Pend: Generates an interrupt request

SWIER4

Bit 4: Software Interrupt on line 4.

Allowed values:
1: Pend: Generates an interrupt request

SWIER5

Bit 5: Software Interrupt on line 5.

Allowed values:
1: Pend: Generates an interrupt request

SWIER6

Bit 6: Software Interrupt on line 6.

Allowed values:
1: Pend: Generates an interrupt request

SWIER7

Bit 7: Software Interrupt on line 7.

Allowed values:
1: Pend: Generates an interrupt request

SWIER8

Bit 8: Software Interrupt on line 8.

Allowed values:
1: Pend: Generates an interrupt request

SWIER9

Bit 9: Software Interrupt on line 9.

Allowed values:
1: Pend: Generates an interrupt request

SWIER10

Bit 10: Software Interrupt on line 10.

Allowed values:
1: Pend: Generates an interrupt request

SWIER11

Bit 11: Software Interrupt on line 11.

Allowed values:
1: Pend: Generates an interrupt request

SWIER12

Bit 12: Software Interrupt on line 12.

Allowed values:
1: Pend: Generates an interrupt request

SWIER13

Bit 13: Software Interrupt on line 13.

Allowed values:
1: Pend: Generates an interrupt request

SWIER14

Bit 14: Software Interrupt on line 14.

Allowed values:
1: Pend: Generates an interrupt request

SWIER15

Bit 15: Software Interrupt on line 15.

Allowed values:
1: Pend: Generates an interrupt request

SWIER16

Bit 16: Software Interrupt on line 16.

Allowed values:
1: Pend: Generates an interrupt request

SWIER17

Bit 17: Software Interrupt on line 17.

Allowed values:
1: Pend: Generates an interrupt request

SWIER18

Bit 18: Software Interrupt on line 18.

Allowed values:
1: Pend: Generates an interrupt request

PR

Pending register (EXTI_PR)

Offset: 0x14, reset: 0x00000000, access: read-write

19/19 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
PR18
rw
PR17
rw
PR16
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PR15
rw
PR14
rw
PR13
rw
PR12
rw
PR11
rw
PR10
rw
PR9
rw
PR8
rw
PR7
rw
PR6
rw
PR5
rw
PR4
rw
PR3
rw
PR2
rw
PR1
rw
PR0
rw
Toggle Fields.

PR0

Bit 0: Pending bit 0.

Allowed values:
0: NotPending: No trigger request occurred
1: Pending: Selected trigger request occurred

PR1

Bit 1: Pending bit 1.

Allowed values:
0: NotPending: No trigger request occurred
1: Pending: Selected trigger request occurred

PR2

Bit 2: Pending bit 2.

Allowed values:
0: NotPending: No trigger request occurred
1: Pending: Selected trigger request occurred

PR3

Bit 3: Pending bit 3.

Allowed values:
0: NotPending: No trigger request occurred
1: Pending: Selected trigger request occurred

PR4

Bit 4: Pending bit 4.

Allowed values:
0: NotPending: No trigger request occurred
1: Pending: Selected trigger request occurred

PR5

Bit 5: Pending bit 5.

Allowed values:
0: NotPending: No trigger request occurred
1: Pending: Selected trigger request occurred

PR6

Bit 6: Pending bit 6.

Allowed values:
0: NotPending: No trigger request occurred
1: Pending: Selected trigger request occurred

PR7

Bit 7: Pending bit 7.

Allowed values:
0: NotPending: No trigger request occurred
1: Pending: Selected trigger request occurred

PR8

Bit 8: Pending bit 8.

Allowed values:
0: NotPending: No trigger request occurred
1: Pending: Selected trigger request occurred

PR9

Bit 9: Pending bit 9.

Allowed values:
0: NotPending: No trigger request occurred
1: Pending: Selected trigger request occurred

PR10

Bit 10: Pending bit 10.

Allowed values:
0: NotPending: No trigger request occurred
1: Pending: Selected trigger request occurred

PR11

Bit 11: Pending bit 11.

Allowed values:
0: NotPending: No trigger request occurred
1: Pending: Selected trigger request occurred

PR12

Bit 12: Pending bit 12.

Allowed values:
0: NotPending: No trigger request occurred
1: Pending: Selected trigger request occurred

PR13

Bit 13: Pending bit 13.

Allowed values:
0: NotPending: No trigger request occurred
1: Pending: Selected trigger request occurred

PR14

Bit 14: Pending bit 14.

Allowed values:
0: NotPending: No trigger request occurred
1: Pending: Selected trigger request occurred

PR15

Bit 15: Pending bit 15.

Allowed values:
0: NotPending: No trigger request occurred
1: Pending: Selected trigger request occurred

PR16

Bit 16: Pending bit 16.

Allowed values:
0: NotPending: No trigger request occurred
1: Pending: Selected trigger request occurred

PR17

Bit 17: Pending bit 17.

Allowed values:
0: NotPending: No trigger request occurred
1: Pending: Selected trigger request occurred

PR18

Bit 18: Pending bit 18.

Allowed values:
0: NotPending: No trigger request occurred
1: Pending: Selected trigger request occurred

FLASH

0x40022000: FLASH

11/29 fields covered. Toggle Registers.

ACR

Flash access control register

Offset: 0x0, reset: 0x00000030, access: Unspecified

2/4 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PRFTBS
r
PRFTBE
rw
HLFCYA
rw
LATENCY
rw
Toggle Fields.

LATENCY

Bits 0-2: Latency.

Allowed values:
0: WS0: Zero wait state, if 0 < SYSCLK≤ 24 MHz
1: WS1: One wait state, if 24 MHz < SYSCLK ≤ 48 MHz
2: WS2: Two wait states, if 48 MHz < SYSCLK ≤ 72 MHz

HLFCYA

Bit 3: Flash half cycle access enable.

PRFTBE

Bit 4: Prefetch buffer enable.

PRFTBS

Bit 5: Prefetch buffer status.

KEYR

Flash key register

Offset: 0x4, reset: 0x00000000, access: write-only

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
KEY
w
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
KEY
w
Toggle Fields.

KEY

Bits 0-31: FPEC key.

OPTKEYR

Flash option key register

Offset: 0x8, reset: 0x00000000, access: write-only

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
OPTKEY
w
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
OPTKEY
w
Toggle Fields.

OPTKEY

Bits 0-31: Option byte key.

SR

Status register

Offset: 0xC, reset: 0x00000000, access: Unspecified

1/4 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
EOP
rw
WRPRTERR
rw
PGERR
rw
BSY
r
Toggle Fields.

BSY

Bit 0: Busy.

PGERR

Bit 2: Programming error.

WRPRTERR

Bit 4: Write protection error.

EOP

Bit 5: End of operation.

CR

Control register

Offset: 0x10, reset: 0x00000080, access: read-write

0/10 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
EOPIE
rw
ERRIE
rw
OPTWRE
rw
LOCK
rw
STRT
rw
OPTER
rw
OPTPG
rw
MER
rw
PER
rw
PG
rw
Toggle Fields.

PG

Bit 0: Programming.

PER

Bit 1: Page Erase.

MER

Bit 2: Mass Erase.

OPTPG

Bit 4: Option byte programming.

OPTER

Bit 5: Option byte erase.

STRT

Bit 6: Start.

LOCK

Bit 7: Lock.

OPTWRE

Bit 9: Option bytes write enable.

ERRIE

Bit 10: Error interrupt enable.

EOPIE

Bit 12: End of operation interrupt enable.

AR

Flash address register

Offset: 0x14, reset: 0x00000000, access: write-only

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
FAR
w
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FAR
w
Toggle Fields.

FAR

Bits 0-31: Flash Address.

OBR

Option byte register

Offset: 0x1C, reset: 0x03FFFFFC, access: read-only

7/7 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Data1
r
Data0
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Data0
r
nRST_STDBY
r
nRST_STOP
r
WDG_SW
r
RDPRT
r
OPTERR
r
Toggle Fields.

OPTERR

Bit 0: Option byte error.

RDPRT

Bit 1: Read protection.

WDG_SW

Bit 2: WDG_SW.

nRST_STOP

Bit 3: nRST_STOP.

nRST_STDBY

Bit 4: nRST_STDBY.

Data0

Bits 10-17: Data0.

Data1

Bits 18-25: Data1.

WRPR

Write protection register

Offset: 0x20, reset: 0xFFFFFFFF, access: read-only

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
WRP
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
WRP
r
Toggle Fields.

WRP

Bits 0-31: Write protect.

FSMC

0xA0000000: Flexible static memory controller

45/119 fields covered. Toggle Registers.

BCR1

SRAM/NOR-Flash chip-select control register 1

Offset: 0x0, reset: 0x000030D0, access: read-write

14/15 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CBURSTRW
rw
CPSIZE
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ASYNCWAIT
rw
EXTMOD
rw
WAITEN
rw
WREN
rw
WAITCFG
rw
WRAPMOD
rw
WAITPOL
rw
BURSTEN
rw
FACCEN
rw
MWID
rw
MTYP
rw
MUXEN
rw
MBKEN
rw
Toggle Fields.

MBKEN

Bit 0: MBKEN.

Allowed values:
0: Disabled: Corresponding memory bank is disabled
1: Enabled: Corresponding memory bank is enabled

MUXEN

Bit 1: MUXEN.

Allowed values:
0: Disabled: Address/Data non-multiplexed
1: Enabled: Address/Data multiplexed on databus

MTYP

Bits 2-3: MTYP.

Allowed values:
0: SRAM: SRAM memory type
1: PSRAM: PSRAM (CRAM) memory type
2: Flash: NOR Flash/OneNAND Flash

MWID

Bits 4-5: MWID.

Allowed values:
0: Bits8: Memory data bus width 8 bits
1: Bits16: Memory data bus width 16 bits
2: Bits32: Memory data bus width 32 bits

FACCEN

Bit 6: FACCEN.

Allowed values:
0: Disabled: Corresponding NOR Flash memory access is disabled
1: Enabled: Corresponding NOR Flash memory access is enabled

BURSTEN

Bit 8: BURSTEN.

Allowed values:
0: Disabled: Burst mode disabled
1: Enabled: Burst mode enabled

WAITPOL

Bit 9: WAITPOL.

Allowed values:
0: ActiveLow: NWAIT active low
1: ActiveHigh: NWAIT active high

WRAPMOD

Bit 10: WRAPMOD.

WAITCFG

Bit 11: WAITCFG.

Allowed values:
0: BeforeWaitState: NWAIT signal is active one data cycle before wait state
1: DuringWaitState: NWAIT signal is active during wait state

WREN

Bit 12: WREN.

Allowed values:
0: Disabled: Write operations disabled for the bank by the FMC
1: Enabled: Write operations enabled for the bank by the FMC

WAITEN

Bit 13: WAITEN.

Allowed values:
0: Disabled: Values inside the FMC_BWTR are taken into account
1: Enabled: NWAIT signal enabled

EXTMOD

Bit 14: EXTMOD.

Allowed values:
0: Disabled: Values inside the FMC_BWTR are not taken into account
1: Enabled: Values inside the FMC_BWTR are taken into account

ASYNCWAIT

Bit 15: ASYNCWAIT.

Allowed values:
0: Disabled: Wait signal not used in asynchronous mode
1: Enabled: Wait signal used even in asynchronous mode

CPSIZE

Bits 16-18: CRAM page size.

Allowed values:
0: NoBurstSplit: No burst split when crossing page boundary
1: Bytes128: 128 bytes CRAM page size
2: Bytes256: 256 bytes CRAM page size
3: Bytes512: 512 bytes CRAM page size
4: Bytes1024: 1024 bytes CRAM page size

CBURSTRW

Bit 19: CBURSTRW.

Allowed values:
1: Enabled: Write operations are performed in synchronous mode
0: Disabled: Write operations are always performed in asynchronous mode

BTR%s

SRAM/NOR-Flash chip-select timing register 1

Offset: 0x4, reset: 0xFFFFFFFF, access: read-write

7/7 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
ACCMOD
rw
DATLAT
rw
CLKDIV
rw
BUSTURN
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DATAST
rw
ADDHLD
rw
ADDSET
rw
Toggle Fields.

ADDSET

Bits 0-3: ADDSET.

Allowed values: 0-15

ADDHLD

Bits 4-7: ADDHLD.

Allowed values: 1-15

DATAST

Bits 8-15: DATAST.

Allowed values: 1-255

BUSTURN

Bits 16-19: BUSTURN.

Allowed values: 0-15

CLKDIV

Bits 20-23: CLKDIV.

Allowed values: 1-15

DATLAT

Bits 24-27: DATLAT.

Allowed values: 0-15

ACCMOD

Bits 28-29: ACCMOD.

Allowed values:
0: A: Access mode A
1: B: Access mode B
2: C: Access mode C
3: D: Access mode D

BCR%s

SRAM/NOR-Flash chip-select control register 2

Offset: 0x8, reset: 0x000030D0, access: read-write

14/15 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CBURSTRW
rw
CPSIZE
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ASYNCWAIT
rw
EXTMOD
rw
WAITEN
rw
WREN
rw
WAITCFG
rw
WRAPMOD
rw
WAITPOL
rw
BURSTEN
rw
FACCEN
rw
MWID
rw
MTYP
rw
MUXEN
rw
MBKEN
rw
Toggle Fields.

MBKEN

Bit 0: MBKEN.

Allowed values:
0: Disabled: Corresponding memory bank is disabled
1: Enabled: Corresponding memory bank is enabled

MUXEN

Bit 1: MUXEN.

Allowed values:
0: Disabled: Address/Data non-multiplexed
1: Enabled: Address/Data multiplexed on databus

MTYP

Bits 2-3: MTYP.

Allowed values:
0: SRAM: SRAM memory type
1: PSRAM: PSRAM (CRAM) memory type
2: Flash: NOR Flash/OneNAND Flash

MWID

Bits 4-5: MWID.

Allowed values:
0: Bits8: Memory data bus width 8 bits
1: Bits16: Memory data bus width 16 bits
2: Bits32: Memory data bus width 32 bits

FACCEN

Bit 6: FACCEN.

Allowed values:
0: Disabled: Corresponding NOR Flash memory access is disabled
1: Enabled: Corresponding NOR Flash memory access is enabled

BURSTEN

Bit 8: BURSTEN.

Allowed values:
0: Disabled: Burst mode disabled
1: Enabled: Burst mode enabled

WAITPOL

Bit 9: WAITPOL.

Allowed values:
0: ActiveLow: NWAIT active low
1: ActiveHigh: NWAIT active high

WRAPMOD

Bit 10: WRAPMOD.

WAITCFG

Bit 11: WAITCFG.

Allowed values:
0: BeforeWaitState: NWAIT signal is active one data cycle before wait state
1: DuringWaitState: NWAIT signal is active during wait state

WREN

Bit 12: WREN.

Allowed values:
0: Disabled: Write operations disabled for the bank by the FMC
1: Enabled: Write operations enabled for the bank by the FMC

WAITEN

Bit 13: WAITEN.

Allowed values:
0: Disabled: Values inside the FMC_BWTR are taken into account
1: Enabled: NWAIT signal enabled

EXTMOD

Bit 14: EXTMOD.

Allowed values:
0: Disabled: Values inside the FMC_BWTR are not taken into account
1: Enabled: Values inside the FMC_BWTR are taken into account

ASYNCWAIT

Bit 15: ASYNCWAIT.

Allowed values:
0: Disabled: Wait signal not used in asynchronous mode
1: Enabled: Wait signal used even in asynchronous mode

CPSIZE

Bits 16-18: CRAM page size.

Allowed values:
0: NoBurstSplit: No burst split when crossing page boundary
1: Bytes128: 128 bytes CRAM page size
2: Bytes256: 256 bytes CRAM page size
3: Bytes512: 512 bytes CRAM page size
4: Bytes1024: 1024 bytes CRAM page size

CBURSTRW

Bit 19: CBURSTRW.

Allowed values:
1: Enabled: Write operations are performed in synchronous mode
0: Disabled: Write operations are always performed in asynchronous mode

PCR2

PC Card/NAND Flash control register 2

Offset: 0x60, reset: 0x00000018, access: read-write

0/8 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
ECCPS
rw
TAR
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TAR
rw
TCLR
rw
ECCEN
rw
PWID
rw
PTYP
rw
PBKEN
rw
PWAITEN
rw
Toggle Fields.

PWAITEN

Bit 1: PWAITEN.

PBKEN

Bit 2: PBKEN.

PTYP

Bit 3: PTYP.

PWID

Bits 4-5: PWID.

ECCEN

Bit 6: ECCEN.

TCLR

Bits 9-12: TCLR.

TAR

Bits 13-16: TAR.

ECCPS

Bits 17-19: ECCPS.

SR2

FIFO status and interrupt register 2

Offset: 0x64, reset: 0x00000040, access: Unspecified

1/7 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FEMPT
r
IFEN
rw
ILEN
rw
IREN
rw
IFS
rw
ILS
rw
IRS
rw
Toggle Fields.

IRS

Bit 0: IRS.

ILS

Bit 1: ILS.

IFS

Bit 2: IFS.

IREN

Bit 3: IREN.

ILEN

Bit 4: ILEN.

IFEN

Bit 5: IFEN.

FEMPT

Bit 6: FEMPT.

PMEM2

Common memory space timing register 2

Offset: 0x68, reset: 0xFCFCFCFC, access: read-write

0/4 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
MEMHIZx
rw
MEMHOLDx
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MEMWAITx
rw
MEMSETx
rw
Toggle Fields.

MEMSETx

Bits 0-7: MEMSETx.

MEMWAITx

Bits 8-15: MEMWAITx.

MEMHOLDx

Bits 16-23: MEMHOLDx.

MEMHIZx

Bits 24-31: MEMHIZx.

PATT2

Attribute memory space timing register 2

Offset: 0x6C, reset: 0xFCFCFCFC, access: read-write

0/4 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
ATTHIZx
rw
ATTHOLDx
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ATTWAITx
rw
ATTSETx
rw
Toggle Fields.

ATTSETx

Bits 0-7: Attribute memory x setup time.

ATTWAITx

Bits 8-15: Attribute memory x wait time.

ATTHOLDx

Bits 16-23: Attribute memory x hold time.

ATTHIZx

Bits 24-31: Attribute memory x databus HiZ time.

ECCR2

ECC result register 2

Offset: 0x74, reset: 0x00000000, access: read-only

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
ECCx
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ECCx
r
Toggle Fields.

ECCx

Bits 0-31: ECC result.

PCR3

PC Card/NAND Flash control register 3

Offset: 0x80, reset: 0x00000018, access: read-write

0/8 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
ECCPS
rw
TAR
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TAR
rw
TCLR
rw
ECCEN
rw
PWID
rw
PTYP
rw
PBKEN
rw
PWAITEN
rw
Toggle Fields.

PWAITEN

Bit 1: PWAITEN.

PBKEN

Bit 2: PBKEN.

PTYP

Bit 3: PTYP.

PWID

Bits 4-5: PWID.

ECCEN

Bit 6: ECCEN.

TCLR

Bits 9-12: TCLR.

TAR

Bits 13-16: TAR.

ECCPS

Bits 17-19: ECCPS.

SR3

FIFO status and interrupt register 3

Offset: 0x84, reset: 0x00000040, access: Unspecified

1/7 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FEMPT
r
IFEN
rw
ILEN
rw
IREN
rw
IFS
rw
ILS
rw
IRS
rw
Toggle Fields.

IRS

Bit 0: IRS.

ILS

Bit 1: ILS.

IFS

Bit 2: IFS.

IREN

Bit 3: IREN.

ILEN

Bit 4: ILEN.

IFEN

Bit 5: IFEN.

FEMPT

Bit 6: FEMPT.

PMEM3

Common memory space timing register 3

Offset: 0x88, reset: 0xFCFCFCFC, access: read-write

0/4 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
MEMHIZx
rw
MEMHOLDx
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MEMWAITx
rw
MEMSETx
rw
Toggle Fields.

MEMSETx

Bits 0-7: MEMSETx.

MEMWAITx

Bits 8-15: MEMWAITx.

MEMHOLDx

Bits 16-23: MEMHOLDx.

MEMHIZx

Bits 24-31: MEMHIZx.

PATT3

Attribute memory space timing register 3

Offset: 0x8C, reset: 0xFCFCFCFC, access: read-write

0/4 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
ATTHIZx
rw
ATTHOLDx
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ATTWAITx
rw
ATTSETx
rw
Toggle Fields.

ATTSETx

Bits 0-7: ATTSETx.

ATTWAITx

Bits 8-15: ATTWAITx.

ATTHOLDx

Bits 16-23: ATTHOLDx.

ATTHIZx

Bits 24-31: ATTHIZx.

ECCR3

ECC result register 3

Offset: 0x94, reset: 0x00000000, access: read-only

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
ECCx
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ECCx
r
Toggle Fields.

ECCx

Bits 0-31: ECCx.

PCR4

PC Card/NAND Flash control register 4

Offset: 0xA0, reset: 0x00000018, access: read-write

0/8 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
ECCPS
rw
TAR
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TAR
rw
TCLR
rw
ECCEN
rw
PWID
rw
PTYP
rw
PBKEN
rw
PWAITEN
rw
Toggle Fields.

PWAITEN

Bit 1: PWAITEN.

PBKEN

Bit 2: PBKEN.

PTYP

Bit 3: PTYP.

PWID

Bits 4-5: PWID.

ECCEN

Bit 6: ECCEN.

TCLR

Bits 9-12: TCLR.

TAR

Bits 13-16: TAR.

ECCPS

Bits 17-19: ECCPS.

SR4

FIFO status and interrupt register 4

Offset: 0xA4, reset: 0x00000040, access: Unspecified

1/7 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FEMPT
r
IFEN
rw
ILEN
rw
IREN
rw
IFS
rw
ILS
rw
IRS
rw
Toggle Fields.

IRS

Bit 0: IRS.

ILS

Bit 1: ILS.

IFS

Bit 2: IFS.

IREN

Bit 3: IREN.

ILEN

Bit 4: ILEN.

IFEN

Bit 5: IFEN.

FEMPT

Bit 6: FEMPT.

PMEM4

Common memory space timing register 4

Offset: 0xA8, reset: 0xFCFCFCFC, access: read-write

0/4 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
MEMHIZx
rw
MEMHOLDx
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MEMWAITx
rw
MEMSETx
rw
Toggle Fields.

MEMSETx

Bits 0-7: MEMSETx.

MEMWAITx

Bits 8-15: MEMWAITx.

MEMHOLDx

Bits 16-23: MEMHOLDx.

MEMHIZx

Bits 24-31: MEMHIZx.

PATT4

Attribute memory space timing register 4

Offset: 0xAC, reset: 0xFCFCFCFC, access: read-write

0/4 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
ATTHIZx
rw
ATTHOLDx
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ATTWAITx
rw
ATTSETx
rw
Toggle Fields.

ATTSETx

Bits 0-7: ATTSETx.

ATTWAITx

Bits 8-15: ATTWAITx.

ATTHOLDx

Bits 16-23: ATTHOLDx.

ATTHIZx

Bits 24-31: ATTHIZx.

PIO4

I/O space timing register 4

Offset: 0xB0, reset: 0xFCFCFCFC, access: read-write

0/4 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
IOHIZx
rw
IOHOLDx
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
IOWAITx
rw
IOSETx
rw
Toggle Fields.

IOSETx

Bits 0-7: IOSETx.

IOWAITx

Bits 8-15: IOWAITx.

IOHOLDx

Bits 16-23: IOHOLDx.

IOHIZx

Bits 24-31: IOHIZx.

BWTR%s

SRAM/NOR-Flash write timing registers 1

Offset: 0x104, reset: 0x0FFFFFFF, access: read-write

5/7 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
ACCMOD
rw
DATLAT
rw
CLKDIV
rw
BUSTURN
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DATAST
rw
ADDHLD
rw
ADDSET
rw
Toggle Fields.

ADDSET

Bits 0-3: ADDSET.

Allowed values: 0-15

ADDHLD

Bits 4-7: ADDHLD.

Allowed values: 1-15

DATAST

Bits 8-15: DATAST.

Allowed values: 1-255

BUSTURN

Bits 16-19: Bus turnaround phase duration.

Allowed values: 0-15

CLKDIV

Bits 20-23: CLKDIV.

DATLAT

Bits 24-27: DATLAT.

ACCMOD

Bits 28-29: ACCMOD.

Allowed values:
0: A: Access mode A
1: B: Access mode B
2: C: Access mode C
3: D: Access mode D

GPIOA

0x40010800: General purpose I/O

129/129 fields covered. Toggle Registers.

CRL

Port configuration register low (GPIOn_CRL)

Offset: 0x0, reset: 0x44444444, access: read-write

16/16 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CNF7
rw
MODE7
rw
CNF6
rw
MODE6
rw
CNF5
rw
MODE5
rw
CNF4
rw
MODE4
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CNF3
rw
MODE3
rw
CNF2
rw
MODE2
rw
CNF1
rw
MODE1
rw
CNF0
rw
MODE0
rw
Toggle Fields.

MODE0

Bits 0-1: Port n.0 mode bits.

Allowed values:
0: Input: Input mode (reset state)
1: Output: Output mode 10 MHz
2: Output2: Output mode 2 MHz
3: Output50: Output mode 50 MHz

CNF0

Bits 2-3: Port n.0 configuration bits.

Allowed values:
0: PushPull: Analog mode / Push-Pull mode
1: OpenDrain: Floating input (reset state) / Open Drain-Mode
2: AltPushPull: Input with pull-up/pull-down / Alternate Function Push-Pull Mode
3: AltOpenDrain: Alternate Function Open-Drain Mode

MODE1

Bits 4-5: Port n.1 mode bits.

Allowed values:
0: Input: Input mode (reset state)
1: Output: Output mode 10 MHz
2: Output2: Output mode 2 MHz
3: Output50: Output mode 50 MHz

CNF1

Bits 6-7: Port n.1 configuration bits.

Allowed values:
0: PushPull: Analog mode / Push-Pull mode
1: OpenDrain: Floating input (reset state) / Open Drain-Mode
2: AltPushPull: Input with pull-up/pull-down / Alternate Function Push-Pull Mode
3: AltOpenDrain: Alternate Function Open-Drain Mode

MODE2

Bits 8-9: Port n.2 mode bits.

Allowed values:
0: Input: Input mode (reset state)
1: Output: Output mode 10 MHz
2: Output2: Output mode 2 MHz
3: Output50: Output mode 50 MHz

CNF2

Bits 10-11: Port n.2 configuration bits.

Allowed values:
0: PushPull: Analog mode / Push-Pull mode
1: OpenDrain: Floating input (reset state) / Open Drain-Mode
2: AltPushPull: Input with pull-up/pull-down / Alternate Function Push-Pull Mode
3: AltOpenDrain: Alternate Function Open-Drain Mode

MODE3

Bits 12-13: Port n.3 mode bits.

Allowed values:
0: Input: Input mode (reset state)
1: Output: Output mode 10 MHz
2: Output2: Output mode 2 MHz
3: Output50: Output mode 50 MHz

CNF3

Bits 14-15: Port n.3 configuration bits.

Allowed values:
0: PushPull: Analog mode / Push-Pull mode
1: OpenDrain: Floating input (reset state) / Open Drain-Mode
2: AltPushPull: Input with pull-up/pull-down / Alternate Function Push-Pull Mode
3: AltOpenDrain: Alternate Function Open-Drain Mode

MODE4

Bits 16-17: Port n.4 mode bits.

Allowed values:
0: Input: Input mode (reset state)
1: Output: Output mode 10 MHz
2: Output2: Output mode 2 MHz
3: Output50: Output mode 50 MHz

CNF4

Bits 18-19: Port n.4 configuration bits.

Allowed values:
0: PushPull: Analog mode / Push-Pull mode
1: OpenDrain: Floating input (reset state) / Open Drain-Mode
2: AltPushPull: Input with pull-up/pull-down / Alternate Function Push-Pull Mode
3: AltOpenDrain: Alternate Function Open-Drain Mode

MODE5

Bits 20-21: Port n.5 mode bits.

Allowed values:
0: Input: Input mode (reset state)
1: Output: Output mode 10 MHz
2: Output2: Output mode 2 MHz
3: Output50: Output mode 50 MHz

CNF5

Bits 22-23: Port n.5 configuration bits.

Allowed values:
0: PushPull: Analog mode / Push-Pull mode
1: OpenDrain: Floating input (reset state) / Open Drain-Mode
2: AltPushPull: Input with pull-up/pull-down / Alternate Function Push-Pull Mode
3: AltOpenDrain: Alternate Function Open-Drain Mode

MODE6

Bits 24-25: Port n.6 mode bits.

Allowed values:
0: Input: Input mode (reset state)
1: Output: Output mode 10 MHz
2: Output2: Output mode 2 MHz
3: Output50: Output mode 50 MHz

CNF6

Bits 26-27: Port n.6 configuration bits.

Allowed values:
0: PushPull: Analog mode / Push-Pull mode
1: OpenDrain: Floating input (reset state) / Open Drain-Mode
2: AltPushPull: Input with pull-up/pull-down / Alternate Function Push-Pull Mode
3: AltOpenDrain: Alternate Function Open-Drain Mode

MODE7

Bits 28-29: Port n.7 mode bits.

Allowed values:
0: Input: Input mode (reset state)
1: Output: Output mode 10 MHz
2: Output2: Output mode 2 MHz
3: Output50: Output mode 50 MHz

CNF7

Bits 30-31: Port n.7 configuration bits.

Allowed values:
0: PushPull: Analog mode / Push-Pull mode
1: OpenDrain: Floating input (reset state) / Open Drain-Mode
2: AltPushPull: Input with pull-up/pull-down / Alternate Function Push-Pull Mode
3: AltOpenDrain: Alternate Function Open-Drain Mode

CRH

Port configuration register high (GPIOn_CRL)

Offset: 0x4, reset: 0x44444444, access: read-write

16/16 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CNF15
rw
MODE15
rw
CNF14
rw
MODE14
rw
CNF13
rw
MODE13
rw
CNF12
rw
MODE12
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CNF11
rw
MODE11
rw
CNF10
rw
MODE10
rw
CNF9
rw
MODE9
rw
CNF8
rw
MODE8
rw
Toggle Fields.

MODE8

Bits 0-1: Port n.8 mode bits.

Allowed values:
0: Input: Input mode (reset state)
1: Output: Output mode 10 MHz
2: Output2: Output mode 2 MHz
3: Output50: Output mode 50 MHz

CNF8

Bits 2-3: Port n.8 configuration bits.

Allowed values:
0: PushPull: Analog mode / Push-Pull mode
1: OpenDrain: Floating input (reset state) / Open Drain-Mode
2: AltPushPull: Input with pull-up/pull-down / Alternate Function Push-Pull Mode
3: AltOpenDrain: Alternate Function Open-Drain Mode

MODE9

Bits 4-5: Port n.9 mode bits.

Allowed values:
0: Input: Input mode (reset state)
1: Output: Output mode 10 MHz
2: Output2: Output mode 2 MHz
3: Output50: Output mode 50 MHz

CNF9

Bits 6-7: Port n.9 configuration bits.

Allowed values:
0: PushPull: Analog mode / Push-Pull mode
1: OpenDrain: Floating input (reset state) / Open Drain-Mode
2: AltPushPull: Input with pull-up/pull-down / Alternate Function Push-Pull Mode
3: AltOpenDrain: Alternate Function Open-Drain Mode

MODE10

Bits 8-9: Port n.10 mode bits.

Allowed values:
0: Input: Input mode (reset state)
1: Output: Output mode 10 MHz
2: Output2: Output mode 2 MHz
3: Output50: Output mode 50 MHz

CNF10

Bits 10-11: Port n.10 configuration bits.

Allowed values:
0: PushPull: Analog mode / Push-Pull mode
1: OpenDrain: Floating input (reset state) / Open Drain-Mode
2: AltPushPull: Input with pull-up/pull-down / Alternate Function Push-Pull Mode
3: AltOpenDrain: Alternate Function Open-Drain Mode

MODE11

Bits 12-13: Port n.11 mode bits.

Allowed values:
0: Input: Input mode (reset state)
1: Output: Output mode 10 MHz
2: Output2: Output mode 2 MHz
3: Output50: Output mode 50 MHz

CNF11

Bits 14-15: Port n.11 configuration bits.

Allowed values:
0: PushPull: Analog mode / Push-Pull mode
1: OpenDrain: Floating input (reset state) / Open Drain-Mode
2: AltPushPull: Input with pull-up/pull-down / Alternate Function Push-Pull Mode
3: AltOpenDrain: Alternate Function Open-Drain Mode

MODE12

Bits 16-17: Port n.12 mode bits.

Allowed values:
0: Input: Input mode (reset state)
1: Output: Output mode 10 MHz
2: Output2: Output mode 2 MHz
3: Output50: Output mode 50 MHz

CNF12

Bits 18-19: Port n.12 configuration bits.

Allowed values:
0: PushPull: Analog mode / Push-Pull mode
1: OpenDrain: Floating input (reset state) / Open Drain-Mode
2: AltPushPull: Input with pull-up/pull-down / Alternate Function Push-Pull Mode
3: AltOpenDrain: Alternate Function Open-Drain Mode

MODE13

Bits 20-21: Port n.13 mode bits.

Allowed values:
0: Input: Input mode (reset state)
1: Output: Output mode 10 MHz
2: Output2: Output mode 2 MHz
3: Output50: Output mode 50 MHz

CNF13

Bits 22-23: Port n.13 configuration bits.

Allowed values:
0: PushPull: Analog mode / Push-Pull mode
1: OpenDrain: Floating input (reset state) / Open Drain-Mode
2: AltPushPull: Input with pull-up/pull-down / Alternate Function Push-Pull Mode
3: AltOpenDrain: Alternate Function Open-Drain Mode

MODE14

Bits 24-25: Port n.14 mode bits.

Allowed values:
0: Input: Input mode (reset state)
1: Output: Output mode 10 MHz
2: Output2: Output mode 2 MHz
3: Output50: Output mode 50 MHz

CNF14

Bits 26-27: Port n.14 configuration bits.

Allowed values:
0: PushPull: Analog mode / Push-Pull mode
1: OpenDrain: Floating input (reset state) / Open Drain-Mode
2: AltPushPull: Input with pull-up/pull-down / Alternate Function Push-Pull Mode
3: AltOpenDrain: Alternate Function Open-Drain Mode

MODE15

Bits 28-29: Port n.15 mode bits.

Allowed values:
0: Input: Input mode (reset state)
1: Output: Output mode 10 MHz
2: Output2: Output mode 2 MHz
3: Output50: Output mode 50 MHz

CNF15

Bits 30-31: Port n.15 configuration bits.

Allowed values:
0: PushPull: Analog mode / Push-Pull mode
1: OpenDrain: Floating input (reset state) / Open Drain-Mode
2: AltPushPull: Input with pull-up/pull-down / Alternate Function Push-Pull Mode
3: AltOpenDrain: Alternate Function Open-Drain Mode

IDR

Port input data register (GPIOn_IDR)

Offset: 0x8, reset: 0x00000000, access: read-only

16/16 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
IDR15
r
IDR14
r
IDR13
r
IDR12
r
IDR11
r
IDR10
r
IDR9
r
IDR8
r
IDR7
r
IDR6
r
IDR5
r
IDR4
r
IDR3
r
IDR2
r
IDR1
r
IDR0
r
Toggle Fields.

IDR0

Bit 0: Port input data.

Allowed values:
1: High: Input is logic high
0: Low: Input is logic low

IDR1

Bit 1: Port input data.

Allowed values:
1: High: Input is logic high
0: Low: Input is logic low

IDR2

Bit 2: Port input data.

Allowed values:
1: High: Input is logic high
0: Low: Input is logic low

IDR3

Bit 3: Port input data.

Allowed values:
1: High: Input is logic high
0: Low: Input is logic low

IDR4

Bit 4: Port input data.

Allowed values:
1: High: Input is logic high
0: Low: Input is logic low

IDR5

Bit 5: Port input data.

Allowed values:
1: High: Input is logic high
0: Low: Input is logic low

IDR6

Bit 6: Port input data.

Allowed values:
1: High: Input is logic high
0: Low: Input is logic low

IDR7

Bit 7: Port input data.

Allowed values:
1: High: Input is logic high
0: Low: Input is logic low

IDR8

Bit 8: Port input data.

Allowed values:
1: High: Input is logic high
0: Low: Input is logic low

IDR9

Bit 9: Port input data.

Allowed values:
1: High: Input is logic high
0: Low: Input is logic low

IDR10

Bit 10: Port input data.

Allowed values:
1: High: Input is logic high
0: Low: Input is logic low

IDR11

Bit 11: Port input data.

Allowed values:
1: High: Input is logic high
0: Low: Input is logic low

IDR12

Bit 12: Port input data.

Allowed values:
1: High: Input is logic high
0: Low: Input is logic low

IDR13

Bit 13: Port input data.

Allowed values:
1: High: Input is logic high
0: Low: Input is logic low

IDR14

Bit 14: Port input data.

Allowed values:
1: High: Input is logic high
0: Low: Input is logic low

IDR15

Bit 15: Port input data.

Allowed values:
1: High: Input is logic high
0: Low: Input is logic low

ODR

Port output data register (GPIOn_ODR)

Offset: 0xC, reset: 0x00000000, access: read-write

16/16 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ODR15
rw
ODR14
rw
ODR13
rw
ODR12
rw
ODR11
rw
ODR10
rw
ODR9
rw
ODR8
rw
ODR7
rw
ODR6
rw
ODR5
rw
ODR4
rw
ODR3
rw
ODR2
rw
ODR1
rw
ODR0
rw
Toggle Fields.

ODR0

Bit 0: Port output data.

Allowed values:
1: High: Set output to logic high
0: Low: Set output to logic low

ODR1

Bit 1: Port output data.

Allowed values:
1: High: Set output to logic high
0: Low: Set output to logic low

ODR2

Bit 2: Port output data.

Allowed values:
1: High: Set output to logic high
0: Low: Set output to logic low

ODR3

Bit 3: Port output data.

Allowed values:
1: High: Set output to logic high
0: Low: Set output to logic low

ODR4

Bit 4: Port output data.

Allowed values:
1: High: Set output to logic high
0: Low: Set output to logic low

ODR5

Bit 5: Port output data.

Allowed values:
1: High: Set output to logic high
0: Low: Set output to logic low

ODR6

Bit 6: Port output data.

Allowed values:
1: High: Set output to logic high
0: Low: Set output to logic low

ODR7

Bit 7: Port output data.

Allowed values:
1: High: Set output to logic high
0: Low: Set output to logic low

ODR8

Bit 8: Port output data.

Allowed values:
1: High: Set output to logic high
0: Low: Set output to logic low

ODR9

Bit 9: Port output data.

Allowed values:
1: High: Set output to logic high
0: Low: Set output to logic low

ODR10

Bit 10: Port output data.

Allowed values:
1: High: Set output to logic high
0: Low: Set output to logic low

ODR11

Bit 11: Port output data.

Allowed values:
1: High: Set output to logic high
0: Low: Set output to logic low

ODR12

Bit 12: Port output data.

Allowed values:
1: High: Set output to logic high
0: Low: Set output to logic low

ODR13

Bit 13: Port output data.

Allowed values:
1: High: Set output to logic high
0: Low: Set output to logic low

ODR14

Bit 14: Port output data.

Allowed values:
1: High: Set output to logic high
0: Low: Set output to logic low

ODR15

Bit 15: Port output data.

Allowed values:
1: High: Set output to logic high
0: Low: Set output to logic low

BSRR

Port bit set/reset register (GPIOn_BSRR)

Offset: 0x10, reset: 0x00000000, access: write-only

32/32 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
BR15
w
BR14
w
BR13
w
BR12
w
BR11
w
BR10
w
BR9
w
BR8
w
BR7
w
BR6
w
BR5
w
BR4
w
BR3
w
BR2
w
BR1
w
BR0
w
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
BS15
w
BS14
w
BS13
w
BS12
w
BS11
w
BS10
w
BS9
w
BS8
w
BS7
w
BS6
w
BS5
w
BS4
w
BS3
w
BS2
w
BS1
w
BS0
w
Toggle Fields.

BS0

Bit 0: Set bit 0.

Allowed values:
1: Set: Sets the corresponding ODRx bit

BS1

Bit 1: Set bit 1.

Allowed values:
1: Set: Sets the corresponding ODRx bit

BS2

Bit 2: Set bit 1.

Allowed values:
1: Set: Sets the corresponding ODRx bit

BS3

Bit 3: Set bit 3.

Allowed values:
1: Set: Sets the corresponding ODRx bit

BS4

Bit 4: Set bit 4.

Allowed values:
1: Set: Sets the corresponding ODRx bit

BS5

Bit 5: Set bit 5.

Allowed values:
1: Set: Sets the corresponding ODRx bit

BS6

Bit 6: Set bit 6.

Allowed values:
1: Set: Sets the corresponding ODRx bit

BS7

Bit 7: Set bit 7.

Allowed values:
1: Set: Sets the corresponding ODRx bit

BS8

Bit 8: Set bit 8.

Allowed values:
1: Set: Sets the corresponding ODRx bit

BS9

Bit 9: Set bit 9.

Allowed values:
1: Set: Sets the corresponding ODRx bit

BS10

Bit 10: Set bit 10.

Allowed values:
1: Set: Sets the corresponding ODRx bit

BS11

Bit 11: Set bit 11.

Allowed values:
1: Set: Sets the corresponding ODRx bit

BS12

Bit 12: Set bit 12.

Allowed values:
1: Set: Sets the corresponding ODRx bit

BS13

Bit 13: Set bit 13.

Allowed values:
1: Set: Sets the corresponding ODRx bit

BS14

Bit 14: Set bit 14.

Allowed values:
1: Set: Sets the corresponding ODRx bit

BS15

Bit 15: Set bit 15.

Allowed values:
1: Set: Sets the corresponding ODRx bit

BR0

Bit 16: Reset bit 0.

Allowed values:
1: Reset: Resets the corresponding ODRx bit

BR1

Bit 17: Reset bit 1.

Allowed values:
1: Reset: Resets the corresponding ODRx bit

BR2

Bit 18: Reset bit 2.

Allowed values:
1: Reset: Resets the corresponding ODRx bit

BR3

Bit 19: Reset bit 3.

Allowed values:
1: Reset: Resets the corresponding ODRx bit

BR4

Bit 20: Reset bit 4.

Allowed values:
1: Reset: Resets the corresponding ODRx bit

BR5

Bit 21: Reset bit 5.

Allowed values:
1: Reset: Resets the corresponding ODRx bit

BR6

Bit 22: Reset bit 6.

Allowed values:
1: Reset: Resets the corresponding ODRx bit

BR7

Bit 23: Reset bit 7.

Allowed values:
1: Reset: Resets the corresponding ODRx bit

BR8

Bit 24: Reset bit 8.

Allowed values:
1: Reset: Resets the corresponding ODRx bit

BR9

Bit 25: Reset bit 9.

Allowed values:
1: Reset: Resets the corresponding ODRx bit

BR10

Bit 26: Reset bit 10.

Allowed values:
1: Reset: Resets the corresponding ODRx bit

BR11

Bit 27: Reset bit 11.

Allowed values:
1: Reset: Resets the corresponding ODRx bit

BR12

Bit 28: Reset bit 12.

Allowed values:
1: Reset: Resets the corresponding ODRx bit

BR13

Bit 29: Reset bit 13.

Allowed values:
1: Reset: Resets the corresponding ODRx bit

BR14

Bit 30: Reset bit 14.

Allowed values:
1: Reset: Resets the corresponding ODRx bit

BR15

Bit 31: Reset bit 15.

Allowed values:
1: Reset: Resets the corresponding ODRx bit

BRR

Port bit reset register (GPIOn_BRR)

Offset: 0x14, reset: 0x00000000, access: write-only

16/16 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
BR15
w
BR14
w
BR13
w
BR12
w
BR11
w
BR10
w
BR9
w
BR8
w
BR7
w
BR6
w
BR5
w
BR4
w
BR3
w
BR2
w
BR1
w
BR0
w
Toggle Fields.

BR0

Bit 0: Reset bit 0.

Allowed values:
0: NoAction: No action on the corresponding ODx bit
1: Reset: Reset the ODx bit

BR1

Bit 1: Reset bit 1.

Allowed values:
0: NoAction: No action on the corresponding ODx bit
1: Reset: Reset the ODx bit

BR2

Bit 2: Reset bit 1.

Allowed values:
0: NoAction: No action on the corresponding ODx bit
1: Reset: Reset the ODx bit

BR3

Bit 3: Reset bit 3.

Allowed values:
0: NoAction: No action on the corresponding ODx bit
1: Reset: Reset the ODx bit

BR4

Bit 4: Reset bit 4.

Allowed values:
0: NoAction: No action on the corresponding ODx bit
1: Reset: Reset the ODx bit

BR5

Bit 5: Reset bit 5.

Allowed values:
0: NoAction: No action on the corresponding ODx bit
1: Reset: Reset the ODx bit

BR6

Bit 6: Reset bit 6.

Allowed values:
0: NoAction: No action on the corresponding ODx bit
1: Reset: Reset the ODx bit

BR7

Bit 7: Reset bit 7.

Allowed values:
0: NoAction: No action on the corresponding ODx bit
1: Reset: Reset the ODx bit

BR8

Bit 8: Reset bit 8.

Allowed values:
0: NoAction: No action on the corresponding ODx bit
1: Reset: Reset the ODx bit

BR9

Bit 9: Reset bit 9.

Allowed values:
0: NoAction: No action on the corresponding ODx bit
1: Reset: Reset the ODx bit

BR10

Bit 10: Reset bit 10.

Allowed values:
0: NoAction: No action on the corresponding ODx bit
1: Reset: Reset the ODx bit

BR11

Bit 11: Reset bit 11.

Allowed values:
0: NoAction: No action on the corresponding ODx bit
1: Reset: Reset the ODx bit

BR12

Bit 12: Reset bit 12.

Allowed values:
0: NoAction: No action on the corresponding ODx bit
1: Reset: Reset the ODx bit

BR13

Bit 13: Reset bit 13.

Allowed values:
0: NoAction: No action on the corresponding ODx bit
1: Reset: Reset the ODx bit

BR14

Bit 14: Reset bit 14.

Allowed values:
0: NoAction: No action on the corresponding ODx bit
1: Reset: Reset the ODx bit

BR15

Bit 15: Reset bit 15.

Allowed values:
0: NoAction: No action on the corresponding ODx bit
1: Reset: Reset the ODx bit

LCKR

Port configuration lock register

Offset: 0x18, reset: 0x00000000, access: read-write

17/17 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LCKK
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LCK15
rw
LCK14
rw
LCK13
rw
LCK12
rw
LCK11
rw
LCK10
rw
LCK9
rw
LCK8
rw
LCK7
rw
LCK6
rw
LCK5
rw
LCK4
rw
LCK3
rw
LCK2
rw
LCK1
rw
LCK0
rw
Toggle Fields.

LCK0

Bit 0: Port A Lock bit 0.

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCK1

Bit 1: Port A Lock bit 1.

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCK2

Bit 2: Port A Lock bit 2.

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCK3

Bit 3: Port A Lock bit 3.

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCK4

Bit 4: Port A Lock bit 4.

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCK5

Bit 5: Port A Lock bit 5.

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCK6

Bit 6: Port A Lock bit 6.

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCK7

Bit 7: Port A Lock bit 7.

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCK8

Bit 8: Port A Lock bit 8.

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCK9

Bit 9: Port A Lock bit 9.

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCK10

Bit 10: Port A Lock bit 10.

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCK11

Bit 11: Port A Lock bit 11.

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCK12

Bit 12: Port A Lock bit 12.

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCK13

Bit 13: Port A Lock bit 13.

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCK14

Bit 14: Port A Lock bit 14.

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCK15

Bit 15: Port A Lock bit 15.

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCKK

Bit 16: Lock key.

Allowed values:
0: NotActive: Port configuration lock key not active
1: Active: Port configuration lock key active

GPIOB

0x40010C00: General purpose I/O

129/129 fields covered. Toggle Registers.

CRL

Port configuration register low (GPIOn_CRL)

Offset: 0x0, reset: 0x44444444, access: read-write

16/16 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CNF7
rw
MODE7
rw
CNF6
rw
MODE6
rw
CNF5
rw
MODE5
rw
CNF4
rw
MODE4
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CNF3
rw
MODE3
rw
CNF2
rw
MODE2
rw
CNF1
rw
MODE1
rw
CNF0
rw
MODE0
rw
Toggle Fields.

MODE0

Bits 0-1: Port n.0 mode bits.

Allowed values:
0: Input: Input mode (reset state)
1: Output: Output mode 10 MHz
2: Output2: Output mode 2 MHz
3: Output50: Output mode 50 MHz

CNF0

Bits 2-3: Port n.0 configuration bits.

Allowed values:
0: PushPull: Analog mode / Push-Pull mode
1: OpenDrain: Floating input (reset state) / Open Drain-Mode
2: AltPushPull: Input with pull-up/pull-down / Alternate Function Push-Pull Mode
3: AltOpenDrain: Alternate Function Open-Drain Mode

MODE1

Bits 4-5: Port n.1 mode bits.

Allowed values:
0: Input: Input mode (reset state)
1: Output: Output mode 10 MHz
2: Output2: Output mode 2 MHz
3: Output50: Output mode 50 MHz

CNF1

Bits 6-7: Port n.1 configuration bits.

Allowed values:
0: PushPull: Analog mode / Push-Pull mode
1: OpenDrain: Floating input (reset state) / Open Drain-Mode
2: AltPushPull: Input with pull-up/pull-down / Alternate Function Push-Pull Mode
3: AltOpenDrain: Alternate Function Open-Drain Mode

MODE2

Bits 8-9: Port n.2 mode bits.

Allowed values:
0: Input: Input mode (reset state)
1: Output: Output mode 10 MHz
2: Output2: Output mode 2 MHz
3: Output50: Output mode 50 MHz

CNF2

Bits 10-11: Port n.2 configuration bits.

Allowed values:
0: PushPull: Analog mode / Push-Pull mode
1: OpenDrain: Floating input (reset state) / Open Drain-Mode
2: AltPushPull: Input with pull-up/pull-down / Alternate Function Push-Pull Mode
3: AltOpenDrain: Alternate Function Open-Drain Mode

MODE3

Bits 12-13: Port n.3 mode bits.

Allowed values:
0: Input: Input mode (reset state)
1: Output: Output mode 10 MHz
2: Output2: Output mode 2 MHz
3: Output50: Output mode 50 MHz

CNF3

Bits 14-15: Port n.3 configuration bits.

Allowed values:
0: PushPull: Analog mode / Push-Pull mode
1: OpenDrain: Floating input (reset state) / Open Drain-Mode
2: AltPushPull: Input with pull-up/pull-down / Alternate Function Push-Pull Mode
3: AltOpenDrain: Alternate Function Open-Drain Mode

MODE4

Bits 16-17: Port n.4 mode bits.

Allowed values:
0: Input: Input mode (reset state)
1: Output: Output mode 10 MHz
2: Output2: Output mode 2 MHz
3: Output50: Output mode 50 MHz

CNF4

Bits 18-19: Port n.4 configuration bits.

Allowed values:
0: PushPull: Analog mode / Push-Pull mode
1: OpenDrain: Floating input (reset state) / Open Drain-Mode
2: AltPushPull: Input with pull-up/pull-down / Alternate Function Push-Pull Mode
3: AltOpenDrain: Alternate Function Open-Drain Mode

MODE5

Bits 20-21: Port n.5 mode bits.

Allowed values:
0: Input: Input mode (reset state)
1: Output: Output mode 10 MHz
2: Output2: Output mode 2 MHz
3: Output50: Output mode 50 MHz

CNF5

Bits 22-23: Port n.5 configuration bits.

Allowed values:
0: PushPull: Analog mode / Push-Pull mode
1: OpenDrain: Floating input (reset state) / Open Drain-Mode
2: AltPushPull: Input with pull-up/pull-down / Alternate Function Push-Pull Mode
3: AltOpenDrain: Alternate Function Open-Drain Mode

MODE6

Bits 24-25: Port n.6 mode bits.

Allowed values:
0: Input: Input mode (reset state)
1: Output: Output mode 10 MHz
2: Output2: Output mode 2 MHz
3: Output50: Output mode 50 MHz

CNF6

Bits 26-27: Port n.6 configuration bits.

Allowed values:
0: PushPull: Analog mode / Push-Pull mode
1: OpenDrain: Floating input (reset state) / Open Drain-Mode
2: AltPushPull: Input with pull-up/pull-down / Alternate Function Push-Pull Mode
3: AltOpenDrain: Alternate Function Open-Drain Mode

MODE7

Bits 28-29: Port n.7 mode bits.

Allowed values:
0: Input: Input mode (reset state)
1: Output: Output mode 10 MHz
2: Output2: Output mode 2 MHz
3: Output50: Output mode 50 MHz

CNF7

Bits 30-31: Port n.7 configuration bits.

Allowed values:
0: PushPull: Analog mode / Push-Pull mode
1: OpenDrain: Floating input (reset state) / Open Drain-Mode
2: AltPushPull: Input with pull-up/pull-down / Alternate Function Push-Pull Mode
3: AltOpenDrain: Alternate Function Open-Drain Mode

CRH

Port configuration register high (GPIOn_CRL)

Offset: 0x4, reset: 0x44444444, access: read-write

16/16 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CNF15
rw
MODE15
rw
CNF14
rw
MODE14
rw
CNF13
rw
MODE13
rw
CNF12
rw
MODE12
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CNF11
rw
MODE11
rw
CNF10
rw
MODE10
rw
CNF9
rw
MODE9
rw
CNF8
rw
MODE8
rw
Toggle Fields.

MODE8

Bits 0-1: Port n.8 mode bits.

Allowed values:
0: Input: Input mode (reset state)
1: Output: Output mode 10 MHz
2: Output2: Output mode 2 MHz
3: Output50: Output mode 50 MHz

CNF8

Bits 2-3: Port n.8 configuration bits.

Allowed values:
0: PushPull: Analog mode / Push-Pull mode
1: OpenDrain: Floating input (reset state) / Open Drain-Mode
2: AltPushPull: Input with pull-up/pull-down / Alternate Function Push-Pull Mode
3: AltOpenDrain: Alternate Function Open-Drain Mode

MODE9

Bits 4-5: Port n.9 mode bits.

Allowed values:
0: Input: Input mode (reset state)
1: Output: Output mode 10 MHz
2: Output2: Output mode 2 MHz
3: Output50: Output mode 50 MHz

CNF9

Bits 6-7: Port n.9 configuration bits.

Allowed values:
0: PushPull: Analog mode / Push-Pull mode
1: OpenDrain: Floating input (reset state) / Open Drain-Mode
2: AltPushPull: Input with pull-up/pull-down / Alternate Function Push-Pull Mode
3: AltOpenDrain: Alternate Function Open-Drain Mode

MODE10

Bits 8-9: Port n.10 mode bits.

Allowed values:
0: Input: Input mode (reset state)
1: Output: Output mode 10 MHz
2: Output2: Output mode 2 MHz
3: Output50: Output mode 50 MHz

CNF10

Bits 10-11: Port n.10 configuration bits.

Allowed values:
0: PushPull: Analog mode / Push-Pull mode
1: OpenDrain: Floating input (reset state) / Open Drain-Mode
2: AltPushPull: Input with pull-up/pull-down / Alternate Function Push-Pull Mode
3: AltOpenDrain: Alternate Function Open-Drain Mode

MODE11

Bits 12-13: Port n.11 mode bits.

Allowed values:
0: Input: Input mode (reset state)
1: Output: Output mode 10 MHz
2: Output2: Output mode 2 MHz
3: Output50: Output mode 50 MHz

CNF11

Bits 14-15: Port n.11 configuration bits.

Allowed values:
0: PushPull: Analog mode / Push-Pull mode
1: OpenDrain: Floating input (reset state) / Open Drain-Mode
2: AltPushPull: Input with pull-up/pull-down / Alternate Function Push-Pull Mode
3: AltOpenDrain: Alternate Function Open-Drain Mode

MODE12

Bits 16-17: Port n.12 mode bits.

Allowed values:
0: Input: Input mode (reset state)
1: Output: Output mode 10 MHz
2: Output2: Output mode 2 MHz
3: Output50: Output mode 50 MHz

CNF12

Bits 18-19: Port n.12 configuration bits.

Allowed values:
0: PushPull: Analog mode / Push-Pull mode
1: OpenDrain: Floating input (reset state) / Open Drain-Mode
2: AltPushPull: Input with pull-up/pull-down / Alternate Function Push-Pull Mode
3: AltOpenDrain: Alternate Function Open-Drain Mode

MODE13

Bits 20-21: Port n.13 mode bits.

Allowed values:
0: Input: Input mode (reset state)
1: Output: Output mode 10 MHz
2: Output2: Output mode 2 MHz
3: Output50: Output mode 50 MHz

CNF13

Bits 22-23: Port n.13 configuration bits.

Allowed values:
0: PushPull: Analog mode / Push-Pull mode
1: OpenDrain: Floating input (reset state) / Open Drain-Mode
2: AltPushPull: Input with pull-up/pull-down / Alternate Function Push-Pull Mode
3: AltOpenDrain: Alternate Function Open-Drain Mode

MODE14

Bits 24-25: Port n.14 mode bits.

Allowed values:
0: Input: Input mode (reset state)
1: Output: Output mode 10 MHz
2: Output2: Output mode 2 MHz
3: Output50: Output mode 50 MHz

CNF14

Bits 26-27: Port n.14 configuration bits.

Allowed values:
0: PushPull: Analog mode / Push-Pull mode
1: OpenDrain: Floating input (reset state) / Open Drain-Mode
2: AltPushPull: Input with pull-up/pull-down / Alternate Function Push-Pull Mode
3: AltOpenDrain: Alternate Function Open-Drain Mode

MODE15

Bits 28-29: Port n.15 mode bits.

Allowed values:
0: Input: Input mode (reset state)
1: Output: Output mode 10 MHz
2: Output2: Output mode 2 MHz
3: Output50: Output mode 50 MHz

CNF15

Bits 30-31: Port n.15 configuration bits.

Allowed values:
0: PushPull: Analog mode / Push-Pull mode
1: OpenDrain: Floating input (reset state) / Open Drain-Mode
2: AltPushPull: Input with pull-up/pull-down / Alternate Function Push-Pull Mode
3: AltOpenDrain: Alternate Function Open-Drain Mode

IDR

Port input data register (GPIOn_IDR)

Offset: 0x8, reset: 0x00000000, access: read-only

16/16 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
IDR15
r
IDR14
r
IDR13
r
IDR12
r
IDR11
r
IDR10
r
IDR9
r
IDR8
r
IDR7
r
IDR6
r
IDR5
r
IDR4
r
IDR3
r
IDR2
r
IDR1
r
IDR0
r
Toggle Fields.

IDR0

Bit 0: Port input data.

Allowed values:
1: High: Input is logic high
0: Low: Input is logic low

IDR1

Bit 1: Port input data.

Allowed values:
1: High: Input is logic high
0: Low: Input is logic low

IDR2

Bit 2: Port input data.

Allowed values:
1: High: Input is logic high
0: Low: Input is logic low

IDR3

Bit 3: Port input data.

Allowed values:
1: High: Input is logic high
0: Low: Input is logic low

IDR4

Bit 4: Port input data.

Allowed values:
1: High: Input is logic high
0: Low: Input is logic low

IDR5

Bit 5: Port input data.

Allowed values:
1: High: Input is logic high
0: Low: Input is logic low

IDR6

Bit 6: Port input data.

Allowed values:
1: High: Input is logic high
0: Low: Input is logic low

IDR7

Bit 7: Port input data.

Allowed values:
1: High: Input is logic high
0: Low: Input is logic low

IDR8

Bit 8: Port input data.

Allowed values:
1: High: Input is logic high
0: Low: Input is logic low

IDR9

Bit 9: Port input data.

Allowed values:
1: High: Input is logic high
0: Low: Input is logic low

IDR10

Bit 10: Port input data.

Allowed values:
1: High: Input is logic high
0: Low: Input is logic low

IDR11

Bit 11: Port input data.

Allowed values:
1: High: Input is logic high
0: Low: Input is logic low

IDR12

Bit 12: Port input data.

Allowed values:
1: High: Input is logic high
0: Low: Input is logic low

IDR13

Bit 13: Port input data.

Allowed values:
1: High: Input is logic high
0: Low: Input is logic low

IDR14

Bit 14: Port input data.

Allowed values:
1: High: Input is logic high
0: Low: Input is logic low

IDR15

Bit 15: Port input data.

Allowed values:
1: High: Input is logic high
0: Low: Input is logic low

ODR

Port output data register (GPIOn_ODR)

Offset: 0xC, reset: 0x00000000, access: read-write

16/16 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ODR15
rw
ODR14
rw
ODR13
rw
ODR12
rw
ODR11
rw
ODR10
rw
ODR9
rw
ODR8
rw
ODR7
rw
ODR6
rw
ODR5
rw
ODR4
rw
ODR3
rw
ODR2
rw
ODR1
rw
ODR0
rw
Toggle Fields.

ODR0

Bit 0: Port output data.

Allowed values:
1: High: Set output to logic high
0: Low: Set output to logic low

ODR1

Bit 1: Port output data.

Allowed values:
1: High: Set output to logic high
0: Low: Set output to logic low

ODR2

Bit 2: Port output data.

Allowed values:
1: High: Set output to logic high
0: Low: Set output to logic low

ODR3

Bit 3: Port output data.

Allowed values:
1: High: Set output to logic high
0: Low: Set output to logic low

ODR4

Bit 4: Port output data.

Allowed values:
1: High: Set output to logic high
0: Low: Set output to logic low

ODR5

Bit 5: Port output data.

Allowed values:
1: High: Set output to logic high
0: Low: Set output to logic low

ODR6

Bit 6: Port output data.

Allowed values:
1: High: Set output to logic high
0: Low: Set output to logic low

ODR7

Bit 7: Port output data.

Allowed values:
1: High: Set output to logic high
0: Low: Set output to logic low

ODR8

Bit 8: Port output data.

Allowed values:
1: High: Set output to logic high
0: Low: Set output to logic low

ODR9

Bit 9: Port output data.

Allowed values:
1: High: Set output to logic high
0: Low: Set output to logic low

ODR10

Bit 10: Port output data.

Allowed values:
1: High: Set output to logic high
0: Low: Set output to logic low

ODR11

Bit 11: Port output data.

Allowed values:
1: High: Set output to logic high
0: Low: Set output to logic low

ODR12

Bit 12: Port output data.

Allowed values:
1: High: Set output to logic high
0: Low: Set output to logic low

ODR13

Bit 13: Port output data.

Allowed values:
1: High: Set output to logic high
0: Low: Set output to logic low

ODR14

Bit 14: Port output data.

Allowed values:
1: High: Set output to logic high
0: Low: Set output to logic low

ODR15

Bit 15: Port output data.

Allowed values:
1: High: Set output to logic high
0: Low: Set output to logic low

BSRR

Port bit set/reset register (GPIOn_BSRR)

Offset: 0x10, reset: 0x00000000, access: write-only

32/32 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
BR15
w
BR14
w
BR13
w
BR12
w
BR11
w
BR10
w
BR9
w
BR8
w
BR7
w
BR6
w
BR5
w
BR4
w
BR3
w
BR2
w
BR1
w
BR0
w
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
BS15
w
BS14
w
BS13
w
BS12
w
BS11
w
BS10
w
BS9
w
BS8
w
BS7
w
BS6
w
BS5
w
BS4
w
BS3
w
BS2
w
BS1
w
BS0
w
Toggle Fields.

BS0

Bit 0: Set bit 0.

Allowed values:
1: Set: Sets the corresponding ODRx bit

BS1

Bit 1: Set bit 1.

Allowed values:
1: Set: Sets the corresponding ODRx bit

BS2

Bit 2: Set bit 1.

Allowed values:
1: Set: Sets the corresponding ODRx bit

BS3

Bit 3: Set bit 3.

Allowed values:
1: Set: Sets the corresponding ODRx bit

BS4

Bit 4: Set bit 4.

Allowed values:
1: Set: Sets the corresponding ODRx bit

BS5

Bit 5: Set bit 5.

Allowed values:
1: Set: Sets the corresponding ODRx bit

BS6

Bit 6: Set bit 6.

Allowed values:
1: Set: Sets the corresponding ODRx bit

BS7

Bit 7: Set bit 7.

Allowed values:
1: Set: Sets the corresponding ODRx bit

BS8

Bit 8: Set bit 8.

Allowed values:
1: Set: Sets the corresponding ODRx bit

BS9

Bit 9: Set bit 9.

Allowed values:
1: Set: Sets the corresponding ODRx bit

BS10

Bit 10: Set bit 10.

Allowed values:
1: Set: Sets the corresponding ODRx bit

BS11

Bit 11: Set bit 11.

Allowed values:
1: Set: Sets the corresponding ODRx bit

BS12

Bit 12: Set bit 12.

Allowed values:
1: Set: Sets the corresponding ODRx bit

BS13

Bit 13: Set bit 13.

Allowed values:
1: Set: Sets the corresponding ODRx bit

BS14

Bit 14: Set bit 14.

Allowed values:
1: Set: Sets the corresponding ODRx bit

BS15

Bit 15: Set bit 15.

Allowed values:
1: Set: Sets the corresponding ODRx bit

BR0

Bit 16: Reset bit 0.

Allowed values:
1: Reset: Resets the corresponding ODRx bit

BR1

Bit 17: Reset bit 1.

Allowed values:
1: Reset: Resets the corresponding ODRx bit

BR2

Bit 18: Reset bit 2.

Allowed values:
1: Reset: Resets the corresponding ODRx bit

BR3

Bit 19: Reset bit 3.

Allowed values:
1: Reset: Resets the corresponding ODRx bit

BR4

Bit 20: Reset bit 4.

Allowed values:
1: Reset: Resets the corresponding ODRx bit

BR5

Bit 21: Reset bit 5.

Allowed values:
1: Reset: Resets the corresponding ODRx bit

BR6

Bit 22: Reset bit 6.

Allowed values:
1: Reset: Resets the corresponding ODRx bit

BR7

Bit 23: Reset bit 7.

Allowed values:
1: Reset: Resets the corresponding ODRx bit

BR8

Bit 24: Reset bit 8.

Allowed values:
1: Reset: Resets the corresponding ODRx bit

BR9

Bit 25: Reset bit 9.

Allowed values:
1: Reset: Resets the corresponding ODRx bit

BR10

Bit 26: Reset bit 10.

Allowed values:
1: Reset: Resets the corresponding ODRx bit

BR11

Bit 27: Reset bit 11.

Allowed values:
1: Reset: Resets the corresponding ODRx bit

BR12

Bit 28: Reset bit 12.

Allowed values:
1: Reset: Resets the corresponding ODRx bit

BR13

Bit 29: Reset bit 13.

Allowed values:
1: Reset: Resets the corresponding ODRx bit

BR14

Bit 30: Reset bit 14.

Allowed values:
1: Reset: Resets the corresponding ODRx bit

BR15

Bit 31: Reset bit 15.

Allowed values:
1: Reset: Resets the corresponding ODRx bit

BRR

Port bit reset register (GPIOn_BRR)

Offset: 0x14, reset: 0x00000000, access: write-only

16/16 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
BR15
w
BR14
w
BR13
w
BR12
w
BR11
w
BR10
w
BR9
w
BR8
w
BR7
w
BR6
w
BR5
w
BR4
w
BR3
w
BR2
w
BR1
w
BR0
w
Toggle Fields.

BR0

Bit 0: Reset bit 0.

Allowed values:
0: NoAction: No action on the corresponding ODx bit
1: Reset: Reset the ODx bit

BR1

Bit 1: Reset bit 1.

Allowed values:
0: NoAction: No action on the corresponding ODx bit
1: Reset: Reset the ODx bit

BR2

Bit 2: Reset bit 1.

Allowed values:
0: NoAction: No action on the corresponding ODx bit
1: Reset: Reset the ODx bit

BR3

Bit 3: Reset bit 3.

Allowed values:
0: NoAction: No action on the corresponding ODx bit
1: Reset: Reset the ODx bit

BR4

Bit 4: Reset bit 4.

Allowed values:
0: NoAction: No action on the corresponding ODx bit
1: Reset: Reset the ODx bit

BR5

Bit 5: Reset bit 5.

Allowed values:
0: NoAction: No action on the corresponding ODx bit
1: Reset: Reset the ODx bit

BR6

Bit 6: Reset bit 6.

Allowed values:
0: NoAction: No action on the corresponding ODx bit
1: Reset: Reset the ODx bit

BR7

Bit 7: Reset bit 7.

Allowed values:
0: NoAction: No action on the corresponding ODx bit
1: Reset: Reset the ODx bit

BR8

Bit 8: Reset bit 8.

Allowed values:
0: NoAction: No action on the corresponding ODx bit
1: Reset: Reset the ODx bit

BR9

Bit 9: Reset bit 9.

Allowed values:
0: NoAction: No action on the corresponding ODx bit
1: Reset: Reset the ODx bit

BR10

Bit 10: Reset bit 10.

Allowed values:
0: NoAction: No action on the corresponding ODx bit
1: Reset: Reset the ODx bit

BR11

Bit 11: Reset bit 11.

Allowed values:
0: NoAction: No action on the corresponding ODx bit
1: Reset: Reset the ODx bit

BR12

Bit 12: Reset bit 12.

Allowed values:
0: NoAction: No action on the corresponding ODx bit
1: Reset: Reset the ODx bit

BR13

Bit 13: Reset bit 13.

Allowed values:
0: NoAction: No action on the corresponding ODx bit
1: Reset: Reset the ODx bit

BR14

Bit 14: Reset bit 14.

Allowed values:
0: NoAction: No action on the corresponding ODx bit
1: Reset: Reset the ODx bit

BR15

Bit 15: Reset bit 15.

Allowed values:
0: NoAction: No action on the corresponding ODx bit
1: Reset: Reset the ODx bit

LCKR

Port configuration lock register

Offset: 0x18, reset: 0x00000000, access: read-write

17/17 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LCKK
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LCK15
rw
LCK14
rw
LCK13
rw
LCK12
rw
LCK11
rw
LCK10
rw
LCK9
rw
LCK8
rw
LCK7
rw
LCK6
rw
LCK5
rw
LCK4
rw
LCK3
rw
LCK2
rw
LCK1
rw
LCK0
rw
Toggle Fields.

LCK0

Bit 0: Port A Lock bit 0.

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCK1

Bit 1: Port A Lock bit 1.

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCK2

Bit 2: Port A Lock bit 2.

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCK3

Bit 3: Port A Lock bit 3.

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCK4

Bit 4: Port A Lock bit 4.

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCK5

Bit 5: Port A Lock bit 5.

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCK6

Bit 6: Port A Lock bit 6.

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCK7

Bit 7: Port A Lock bit 7.

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCK8

Bit 8: Port A Lock bit 8.

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCK9

Bit 9: Port A Lock bit 9.

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCK10

Bit 10: Port A Lock bit 10.

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCK11

Bit 11: Port A Lock bit 11.

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCK12

Bit 12: Port A Lock bit 12.

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCK13

Bit 13: Port A Lock bit 13.

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCK14

Bit 14: Port A Lock bit 14.

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCK15

Bit 15: Port A Lock bit 15.

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCKK

Bit 16: Lock key.

Allowed values:
0: NotActive: Port configuration lock key not active
1: Active: Port configuration lock key active

GPIOC

0x40011000: General purpose I/O

129/129 fields covered. Toggle Registers.

CRL

Port configuration register low (GPIOn_CRL)

Offset: 0x0, reset: 0x44444444, access: read-write

16/16 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CNF7
rw
MODE7
rw
CNF6
rw
MODE6
rw
CNF5
rw
MODE5
rw
CNF4
rw
MODE4
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CNF3
rw
MODE3
rw
CNF2
rw
MODE2
rw
CNF1
rw
MODE1
rw
CNF0
rw
MODE0
rw
Toggle Fields.

MODE0

Bits 0-1: Port n.0 mode bits.

Allowed values:
0: Input: Input mode (reset state)
1: Output: Output mode 10 MHz
2: Output2: Output mode 2 MHz
3: Output50: Output mode 50 MHz

CNF0

Bits 2-3: Port n.0 configuration bits.

Allowed values:
0: PushPull: Analog mode / Push-Pull mode
1: OpenDrain: Floating input (reset state) / Open Drain-Mode
2: AltPushPull: Input with pull-up/pull-down / Alternate Function Push-Pull Mode
3: AltOpenDrain: Alternate Function Open-Drain Mode

MODE1

Bits 4-5: Port n.1 mode bits.

Allowed values:
0: Input: Input mode (reset state)
1: Output: Output mode 10 MHz
2: Output2: Output mode 2 MHz
3: Output50: Output mode 50 MHz

CNF1

Bits 6-7: Port n.1 configuration bits.

Allowed values:
0: PushPull: Analog mode / Push-Pull mode
1: OpenDrain: Floating input (reset state) / Open Drain-Mode
2: AltPushPull: Input with pull-up/pull-down / Alternate Function Push-Pull Mode
3: AltOpenDrain: Alternate Function Open-Drain Mode

MODE2

Bits 8-9: Port n.2 mode bits.

Allowed values:
0: Input: Input mode (reset state)
1: Output: Output mode 10 MHz
2: Output2: Output mode 2 MHz
3: Output50: Output mode 50 MHz

CNF2

Bits 10-11: Port n.2 configuration bits.

Allowed values:
0: PushPull: Analog mode / Push-Pull mode
1: OpenDrain: Floating input (reset state) / Open Drain-Mode
2: AltPushPull: Input with pull-up/pull-down / Alternate Function Push-Pull Mode
3: AltOpenDrain: Alternate Function Open-Drain Mode

MODE3

Bits 12-13: Port n.3 mode bits.

Allowed values:
0: Input: Input mode (reset state)
1: Output: Output mode 10 MHz
2: Output2: Output mode 2 MHz
3: Output50: Output mode 50 MHz

CNF3

Bits 14-15: Port n.3 configuration bits.

Allowed values:
0: PushPull: Analog mode / Push-Pull mode
1: OpenDrain: Floating input (reset state) / Open Drain-Mode
2: AltPushPull: Input with pull-up/pull-down / Alternate Function Push-Pull Mode
3: AltOpenDrain: Alternate Function Open-Drain Mode

MODE4

Bits 16-17: Port n.4 mode bits.

Allowed values:
0: Input: Input mode (reset state)
1: Output: Output mode 10 MHz
2: Output2: Output mode 2 MHz
3: Output50: Output mode 50 MHz

CNF4

Bits 18-19: Port n.4 configuration bits.

Allowed values:
0: PushPull: Analog mode / Push-Pull mode
1: OpenDrain: Floating input (reset state) / Open Drain-Mode
2: AltPushPull: Input with pull-up/pull-down / Alternate Function Push-Pull Mode
3: AltOpenDrain: Alternate Function Open-Drain Mode

MODE5

Bits 20-21: Port n.5 mode bits.

Allowed values:
0: Input: Input mode (reset state)
1: Output: Output mode 10 MHz
2: Output2: Output mode 2 MHz
3: Output50: Output mode 50 MHz

CNF5

Bits 22-23: Port n.5 configuration bits.

Allowed values:
0: PushPull: Analog mode / Push-Pull mode
1: OpenDrain: Floating input (reset state) / Open Drain-Mode
2: AltPushPull: Input with pull-up/pull-down / Alternate Function Push-Pull Mode
3: AltOpenDrain: Alternate Function Open-Drain Mode

MODE6

Bits 24-25: Port n.6 mode bits.

Allowed values:
0: Input: Input mode (reset state)
1: Output: Output mode 10 MHz
2: Output2: Output mode 2 MHz
3: Output50: Output mode 50 MHz

CNF6

Bits 26-27: Port n.6 configuration bits.

Allowed values:
0: PushPull: Analog mode / Push-Pull mode
1: OpenDrain: Floating input (reset state) / Open Drain-Mode
2: AltPushPull: Input with pull-up/pull-down / Alternate Function Push-Pull Mode
3: AltOpenDrain: Alternate Function Open-Drain Mode

MODE7

Bits 28-29: Port n.7 mode bits.

Allowed values:
0: Input: Input mode (reset state)
1: Output: Output mode 10 MHz
2: Output2: Output mode 2 MHz
3: Output50: Output mode 50 MHz

CNF7

Bits 30-31: Port n.7 configuration bits.

Allowed values:
0: PushPull: Analog mode / Push-Pull mode
1: OpenDrain: Floating input (reset state) / Open Drain-Mode
2: AltPushPull: Input with pull-up/pull-down / Alternate Function Push-Pull Mode
3: AltOpenDrain: Alternate Function Open-Drain Mode

CRH

Port configuration register high (GPIOn_CRL)

Offset: 0x4, reset: 0x44444444, access: read-write

16/16 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CNF15
rw
MODE15
rw
CNF14
rw
MODE14
rw
CNF13
rw
MODE13
rw
CNF12
rw
MODE12
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CNF11
rw
MODE11
rw
CNF10
rw
MODE10
rw
CNF9
rw
MODE9
rw
CNF8
rw
MODE8
rw
Toggle Fields.

MODE8

Bits 0-1: Port n.8 mode bits.

Allowed values:
0: Input: Input mode (reset state)
1: Output: Output mode 10 MHz
2: Output2: Output mode 2 MHz
3: Output50: Output mode 50 MHz

CNF8

Bits 2-3: Port n.8 configuration bits.

Allowed values:
0: PushPull: Analog mode / Push-Pull mode
1: OpenDrain: Floating input (reset state) / Open Drain-Mode
2: AltPushPull: Input with pull-up/pull-down / Alternate Function Push-Pull Mode
3: AltOpenDrain: Alternate Function Open-Drain Mode

MODE9

Bits 4-5: Port n.9 mode bits.

Allowed values:
0: Input: Input mode (reset state)
1: Output: Output mode 10 MHz
2: Output2: Output mode 2 MHz
3: Output50: Output mode 50 MHz

CNF9

Bits 6-7: Port n.9 configuration bits.

Allowed values:
0: PushPull: Analog mode / Push-Pull mode
1: OpenDrain: Floating input (reset state) / Open Drain-Mode
2: AltPushPull: Input with pull-up/pull-down / Alternate Function Push-Pull Mode
3: AltOpenDrain: Alternate Function Open-Drain Mode

MODE10

Bits 8-9: Port n.10 mode bits.

Allowed values:
0: Input: Input mode (reset state)
1: Output: Output mode 10 MHz
2: Output2: Output mode 2 MHz
3: Output50: Output mode 50 MHz

CNF10

Bits 10-11: Port n.10 configuration bits.

Allowed values:
0: PushPull: Analog mode / Push-Pull mode
1: OpenDrain: Floating input (reset state) / Open Drain-Mode
2: AltPushPull: Input with pull-up/pull-down / Alternate Function Push-Pull Mode
3: AltOpenDrain: Alternate Function Open-Drain Mode

MODE11

Bits 12-13: Port n.11 mode bits.

Allowed values:
0: Input: Input mode (reset state)
1: Output: Output mode 10 MHz
2: Output2: Output mode 2 MHz
3: Output50: Output mode 50 MHz

CNF11

Bits 14-15: Port n.11 configuration bits.

Allowed values:
0: PushPull: Analog mode / Push-Pull mode
1: OpenDrain: Floating input (reset state) / Open Drain-Mode
2: AltPushPull: Input with pull-up/pull-down / Alternate Function Push-Pull Mode
3: AltOpenDrain: Alternate Function Open-Drain Mode

MODE12

Bits 16-17: Port n.12 mode bits.

Allowed values:
0: Input: Input mode (reset state)
1: Output: Output mode 10 MHz
2: Output2: Output mode 2 MHz
3: Output50: Output mode 50 MHz

CNF12

Bits 18-19: Port n.12 configuration bits.

Allowed values:
0: PushPull: Analog mode / Push-Pull mode
1: OpenDrain: Floating input (reset state) / Open Drain-Mode
2: AltPushPull: Input with pull-up/pull-down / Alternate Function Push-Pull Mode
3: AltOpenDrain: Alternate Function Open-Drain Mode

MODE13

Bits 20-21: Port n.13 mode bits.

Allowed values:
0: Input: Input mode (reset state)
1: Output: Output mode 10 MHz
2: Output2: Output mode 2 MHz
3: Output50: Output mode 50 MHz

CNF13

Bits 22-23: Port n.13 configuration bits.

Allowed values:
0: PushPull: Analog mode / Push-Pull mode
1: OpenDrain: Floating input (reset state) / Open Drain-Mode
2: AltPushPull: Input with pull-up/pull-down / Alternate Function Push-Pull Mode
3: AltOpenDrain: Alternate Function Open-Drain Mode

MODE14

Bits 24-25: Port n.14 mode bits.

Allowed values:
0: Input: Input mode (reset state)
1: Output: Output mode 10 MHz
2: Output2: Output mode 2 MHz
3: Output50: Output mode 50 MHz

CNF14

Bits 26-27: Port n.14 configuration bits.

Allowed values:
0: PushPull: Analog mode / Push-Pull mode
1: OpenDrain: Floating input (reset state) / Open Drain-Mode
2: AltPushPull: Input with pull-up/pull-down / Alternate Function Push-Pull Mode
3: AltOpenDrain: Alternate Function Open-Drain Mode

MODE15

Bits 28-29: Port n.15 mode bits.

Allowed values:
0: Input: Input mode (reset state)
1: Output: Output mode 10 MHz
2: Output2: Output mode 2 MHz
3: Output50: Output mode 50 MHz

CNF15

Bits 30-31: Port n.15 configuration bits.

Allowed values:
0: PushPull: Analog mode / Push-Pull mode
1: OpenDrain: Floating input (reset state) / Open Drain-Mode
2: AltPushPull: Input with pull-up/pull-down / Alternate Function Push-Pull Mode
3: AltOpenDrain: Alternate Function Open-Drain Mode

IDR

Port input data register (GPIOn_IDR)

Offset: 0x8, reset: 0x00000000, access: read-only

16/16 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
IDR15
r
IDR14
r
IDR13
r
IDR12
r
IDR11
r
IDR10
r
IDR9
r
IDR8
r
IDR7
r
IDR6
r
IDR5
r
IDR4
r
IDR3
r
IDR2
r
IDR1
r
IDR0
r
Toggle Fields.

IDR0

Bit 0: Port input data.

Allowed values:
1: High: Input is logic high
0: Low: Input is logic low

IDR1

Bit 1: Port input data.

Allowed values:
1: High: Input is logic high
0: Low: Input is logic low

IDR2

Bit 2: Port input data.

Allowed values:
1: High: Input is logic high
0: Low: Input is logic low

IDR3

Bit 3: Port input data.

Allowed values:
1: High: Input is logic high
0: Low: Input is logic low

IDR4

Bit 4: Port input data.

Allowed values:
1: High: Input is logic high
0: Low: Input is logic low

IDR5

Bit 5: Port input data.

Allowed values:
1: High: Input is logic high
0: Low: Input is logic low

IDR6

Bit 6: Port input data.

Allowed values:
1: High: Input is logic high
0: Low: Input is logic low

IDR7

Bit 7: Port input data.

Allowed values:
1: High: Input is logic high
0: Low: Input is logic low

IDR8

Bit 8: Port input data.

Allowed values:
1: High: Input is logic high
0: Low: Input is logic low

IDR9

Bit 9: Port input data.

Allowed values:
1: High: Input is logic high
0: Low: Input is logic low

IDR10

Bit 10: Port input data.

Allowed values:
1: High: Input is logic high
0: Low: Input is logic low

IDR11

Bit 11: Port input data.

Allowed values:
1: High: Input is logic high
0: Low: Input is logic low

IDR12

Bit 12: Port input data.

Allowed values:
1: High: Input is logic high
0: Low: Input is logic low

IDR13

Bit 13: Port input data.

Allowed values:
1: High: Input is logic high
0: Low: Input is logic low

IDR14

Bit 14: Port input data.

Allowed values:
1: High: Input is logic high
0: Low: Input is logic low

IDR15

Bit 15: Port input data.

Allowed values:
1: High: Input is logic high
0: Low: Input is logic low

ODR

Port output data register (GPIOn_ODR)

Offset: 0xC, reset: 0x00000000, access: read-write

16/16 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ODR15
rw
ODR14
rw
ODR13
rw
ODR12
rw
ODR11
rw
ODR10
rw
ODR9
rw
ODR8
rw
ODR7
rw
ODR6
rw
ODR5
rw
ODR4
rw
ODR3
rw
ODR2
rw
ODR1
rw
ODR0
rw
Toggle Fields.

ODR0

Bit 0: Port output data.

Allowed values:
1: High: Set output to logic high
0: Low: Set output to logic low

ODR1

Bit 1: Port output data.

Allowed values:
1: High: Set output to logic high
0: Low: Set output to logic low

ODR2

Bit 2: Port output data.

Allowed values:
1: High: Set output to logic high
0: Low: Set output to logic low

ODR3

Bit 3: Port output data.

Allowed values:
1: High: Set output to logic high
0: Low: Set output to logic low

ODR4

Bit 4: Port output data.

Allowed values:
1: High: Set output to logic high
0: Low: Set output to logic low

ODR5

Bit 5: Port output data.

Allowed values:
1: High: Set output to logic high
0: Low: Set output to logic low

ODR6

Bit 6: Port output data.

Allowed values:
1: High: Set output to logic high
0: Low: Set output to logic low

ODR7

Bit 7: Port output data.

Allowed values:
1: High: Set output to logic high
0: Low: Set output to logic low

ODR8

Bit 8: Port output data.

Allowed values:
1: High: Set output to logic high
0: Low: Set output to logic low

ODR9

Bit 9: Port output data.

Allowed values:
1: High: Set output to logic high
0: Low: Set output to logic low

ODR10

Bit 10: Port output data.

Allowed values:
1: High: Set output to logic high
0: Low: Set output to logic low

ODR11

Bit 11: Port output data.

Allowed values:
1: High: Set output to logic high
0: Low: Set output to logic low

ODR12

Bit 12: Port output data.

Allowed values:
1: High: Set output to logic high
0: Low: Set output to logic low

ODR13

Bit 13: Port output data.

Allowed values:
1: High: Set output to logic high
0: Low: Set output to logic low

ODR14

Bit 14: Port output data.

Allowed values:
1: High: Set output to logic high
0: Low: Set output to logic low

ODR15

Bit 15: Port output data.

Allowed values:
1: High: Set output to logic high
0: Low: Set output to logic low

BSRR

Port bit set/reset register (GPIOn_BSRR)

Offset: 0x10, reset: 0x00000000, access: write-only

32/32 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
BR15
w
BR14
w
BR13
w
BR12
w
BR11
w
BR10
w
BR9
w
BR8
w
BR7
w
BR6
w
BR5
w
BR4
w
BR3
w
BR2
w
BR1
w
BR0
w
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
BS15
w
BS14
w
BS13
w
BS12
w
BS11
w
BS10
w
BS9
w
BS8
w
BS7
w
BS6
w
BS5
w
BS4
w
BS3
w
BS2
w
BS1
w
BS0
w
Toggle Fields.

BS0

Bit 0: Set bit 0.

Allowed values:
1: Set: Sets the corresponding ODRx bit

BS1

Bit 1: Set bit 1.

Allowed values:
1: Set: Sets the corresponding ODRx bit

BS2

Bit 2: Set bit 1.

Allowed values:
1: Set: Sets the corresponding ODRx bit

BS3

Bit 3: Set bit 3.

Allowed values:
1: Set: Sets the corresponding ODRx bit

BS4

Bit 4: Set bit 4.

Allowed values:
1: Set: Sets the corresponding ODRx bit

BS5

Bit 5: Set bit 5.

Allowed values:
1: Set: Sets the corresponding ODRx bit

BS6

Bit 6: Set bit 6.

Allowed values:
1: Set: Sets the corresponding ODRx bit

BS7

Bit 7: Set bit 7.

Allowed values:
1: Set: Sets the corresponding ODRx bit

BS8

Bit 8: Set bit 8.

Allowed values:
1: Set: Sets the corresponding ODRx bit

BS9

Bit 9: Set bit 9.

Allowed values:
1: Set: Sets the corresponding ODRx bit

BS10

Bit 10: Set bit 10.

Allowed values:
1: Set: Sets the corresponding ODRx bit

BS11

Bit 11: Set bit 11.

Allowed values:
1: Set: Sets the corresponding ODRx bit

BS12

Bit 12: Set bit 12.

Allowed values:
1: Set: Sets the corresponding ODRx bit

BS13

Bit 13: Set bit 13.

Allowed values:
1: Set: Sets the corresponding ODRx bit

BS14

Bit 14: Set bit 14.

Allowed values:
1: Set: Sets the corresponding ODRx bit

BS15

Bit 15: Set bit 15.

Allowed values:
1: Set: Sets the corresponding ODRx bit

BR0

Bit 16: Reset bit 0.

Allowed values:
1: Reset: Resets the corresponding ODRx bit

BR1

Bit 17: Reset bit 1.

Allowed values:
1: Reset: Resets the corresponding ODRx bit

BR2

Bit 18: Reset bit 2.

Allowed values:
1: Reset: Resets the corresponding ODRx bit

BR3

Bit 19: Reset bit 3.

Allowed values:
1: Reset: Resets the corresponding ODRx bit

BR4

Bit 20: Reset bit 4.

Allowed values:
1: Reset: Resets the corresponding ODRx bit

BR5

Bit 21: Reset bit 5.

Allowed values:
1: Reset: Resets the corresponding ODRx bit

BR6

Bit 22: Reset bit 6.

Allowed values:
1: Reset: Resets the corresponding ODRx bit

BR7

Bit 23: Reset bit 7.

Allowed values:
1: Reset: Resets the corresponding ODRx bit

BR8

Bit 24: Reset bit 8.

Allowed values:
1: Reset: Resets the corresponding ODRx bit

BR9

Bit 25: Reset bit 9.

Allowed values:
1: Reset: Resets the corresponding ODRx bit

BR10

Bit 26: Reset bit 10.

Allowed values:
1: Reset: Resets the corresponding ODRx bit

BR11

Bit 27: Reset bit 11.

Allowed values:
1: Reset: Resets the corresponding ODRx bit

BR12

Bit 28: Reset bit 12.

Allowed values:
1: Reset: Resets the corresponding ODRx bit

BR13

Bit 29: Reset bit 13.

Allowed values:
1: Reset: Resets the corresponding ODRx bit

BR14

Bit 30: Reset bit 14.

Allowed values:
1: Reset: Resets the corresponding ODRx bit

BR15

Bit 31: Reset bit 15.

Allowed values:
1: Reset: Resets the corresponding ODRx bit

BRR

Port bit reset register (GPIOn_BRR)

Offset: 0x14, reset: 0x00000000, access: write-only

16/16 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
BR15
w
BR14
w
BR13
w
BR12
w
BR11
w
BR10
w
BR9
w
BR8
w
BR7
w
BR6
w
BR5
w
BR4
w
BR3
w
BR2
w
BR1
w
BR0
w
Toggle Fields.

BR0

Bit 0: Reset bit 0.

Allowed values:
0: NoAction: No action on the corresponding ODx bit
1: Reset: Reset the ODx bit

BR1

Bit 1: Reset bit 1.

Allowed values:
0: NoAction: No action on the corresponding ODx bit
1: Reset: Reset the ODx bit

BR2

Bit 2: Reset bit 1.

Allowed values:
0: NoAction: No action on the corresponding ODx bit
1: Reset: Reset the ODx bit

BR3

Bit 3: Reset bit 3.

Allowed values:
0: NoAction: No action on the corresponding ODx bit
1: Reset: Reset the ODx bit

BR4

Bit 4: Reset bit 4.

Allowed values:
0: NoAction: No action on the corresponding ODx bit
1: Reset: Reset the ODx bit

BR5

Bit 5: Reset bit 5.

Allowed values:
0: NoAction: No action on the corresponding ODx bit
1: Reset: Reset the ODx bit

BR6

Bit 6: Reset bit 6.

Allowed values:
0: NoAction: No action on the corresponding ODx bit
1: Reset: Reset the ODx bit

BR7

Bit 7: Reset bit 7.

Allowed values:
0: NoAction: No action on the corresponding ODx bit
1: Reset: Reset the ODx bit

BR8

Bit 8: Reset bit 8.

Allowed values:
0: NoAction: No action on the corresponding ODx bit
1: Reset: Reset the ODx bit

BR9

Bit 9: Reset bit 9.

Allowed values:
0: NoAction: No action on the corresponding ODx bit
1: Reset: Reset the ODx bit

BR10

Bit 10: Reset bit 10.

Allowed values:
0: NoAction: No action on the corresponding ODx bit
1: Reset: Reset the ODx bit

BR11

Bit 11: Reset bit 11.

Allowed values:
0: NoAction: No action on the corresponding ODx bit
1: Reset: Reset the ODx bit

BR12

Bit 12: Reset bit 12.

Allowed values:
0: NoAction: No action on the corresponding ODx bit
1: Reset: Reset the ODx bit

BR13

Bit 13: Reset bit 13.

Allowed values:
0: NoAction: No action on the corresponding ODx bit
1: Reset: Reset the ODx bit

BR14

Bit 14: Reset bit 14.

Allowed values:
0: NoAction: No action on the corresponding ODx bit
1: Reset: Reset the ODx bit

BR15

Bit 15: Reset bit 15.

Allowed values:
0: NoAction: No action on the corresponding ODx bit
1: Reset: Reset the ODx bit

LCKR

Port configuration lock register

Offset: 0x18, reset: 0x00000000, access: read-write

17/17 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LCKK
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LCK15
rw
LCK14
rw
LCK13
rw
LCK12
rw
LCK11
rw
LCK10
rw
LCK9
rw
LCK8
rw
LCK7
rw
LCK6
rw
LCK5
rw
LCK4
rw
LCK3
rw
LCK2
rw
LCK1
rw
LCK0
rw
Toggle Fields.

LCK0

Bit 0: Port A Lock bit 0.

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCK1

Bit 1: Port A Lock bit 1.

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCK2

Bit 2: Port A Lock bit 2.

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCK3

Bit 3: Port A Lock bit 3.

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCK4

Bit 4: Port A Lock bit 4.

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCK5

Bit 5: Port A Lock bit 5.

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCK6

Bit 6: Port A Lock bit 6.

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCK7

Bit 7: Port A Lock bit 7.

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCK8

Bit 8: Port A Lock bit 8.

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCK9

Bit 9: Port A Lock bit 9.

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCK10

Bit 10: Port A Lock bit 10.

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCK11

Bit 11: Port A Lock bit 11.

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCK12

Bit 12: Port A Lock bit 12.

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCK13

Bit 13: Port A Lock bit 13.

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCK14

Bit 14: Port A Lock bit 14.

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCK15

Bit 15: Port A Lock bit 15.

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCKK

Bit 16: Lock key.

Allowed values:
0: NotActive: Port configuration lock key not active
1: Active: Port configuration lock key active

GPIOD

0x40011400: General purpose I/O

129/129 fields covered. Toggle Registers.

CRL

Port configuration register low (GPIOn_CRL)

Offset: 0x0, reset: 0x44444444, access: read-write

16/16 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CNF7
rw
MODE7
rw
CNF6
rw
MODE6
rw
CNF5
rw
MODE5
rw
CNF4
rw
MODE4
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CNF3
rw
MODE3
rw
CNF2
rw
MODE2
rw
CNF1
rw
MODE1
rw
CNF0
rw
MODE0
rw
Toggle Fields.

MODE0

Bits 0-1: Port n.0 mode bits.

Allowed values:
0: Input: Input mode (reset state)
1: Output: Output mode 10 MHz
2: Output2: Output mode 2 MHz
3: Output50: Output mode 50 MHz

CNF0

Bits 2-3: Port n.0 configuration bits.

Allowed values:
0: PushPull: Analog mode / Push-Pull mode
1: OpenDrain: Floating input (reset state) / Open Drain-Mode
2: AltPushPull: Input with pull-up/pull-down / Alternate Function Push-Pull Mode
3: AltOpenDrain: Alternate Function Open-Drain Mode

MODE1

Bits 4-5: Port n.1 mode bits.

Allowed values:
0: Input: Input mode (reset state)
1: Output: Output mode 10 MHz
2: Output2: Output mode 2 MHz
3: Output50: Output mode 50 MHz

CNF1

Bits 6-7: Port n.1 configuration bits.

Allowed values:
0: PushPull: Analog mode / Push-Pull mode
1: OpenDrain: Floating input (reset state) / Open Drain-Mode
2: AltPushPull: Input with pull-up/pull-down / Alternate Function Push-Pull Mode
3: AltOpenDrain: Alternate Function Open-Drain Mode

MODE2

Bits 8-9: Port n.2 mode bits.

Allowed values:
0: Input: Input mode (reset state)
1: Output: Output mode 10 MHz
2: Output2: Output mode 2 MHz
3: Output50: Output mode 50 MHz

CNF2

Bits 10-11: Port n.2 configuration bits.

Allowed values:
0: PushPull: Analog mode / Push-Pull mode
1: OpenDrain: Floating input (reset state) / Open Drain-Mode
2: AltPushPull: Input with pull-up/pull-down / Alternate Function Push-Pull Mode
3: AltOpenDrain: Alternate Function Open-Drain Mode

MODE3

Bits 12-13: Port n.3 mode bits.

Allowed values:
0: Input: Input mode (reset state)
1: Output: Output mode 10 MHz
2: Output2: Output mode 2 MHz
3: Output50: Output mode 50 MHz

CNF3

Bits 14-15: Port n.3 configuration bits.

Allowed values:
0: PushPull: Analog mode / Push-Pull mode
1: OpenDrain: Floating input (reset state) / Open Drain-Mode
2: AltPushPull: Input with pull-up/pull-down / Alternate Function Push-Pull Mode
3: AltOpenDrain: Alternate Function Open-Drain Mode

MODE4

Bits 16-17: Port n.4 mode bits.

Allowed values:
0: Input: Input mode (reset state)
1: Output: Output mode 10 MHz
2: Output2: Output mode 2 MHz
3: Output50: Output mode 50 MHz

CNF4

Bits 18-19: Port n.4 configuration bits.

Allowed values:
0: PushPull: Analog mode / Push-Pull mode
1: OpenDrain: Floating input (reset state) / Open Drain-Mode
2: AltPushPull: Input with pull-up/pull-down / Alternate Function Push-Pull Mode
3: AltOpenDrain: Alternate Function Open-Drain Mode

MODE5

Bits 20-21: Port n.5 mode bits.

Allowed values:
0: Input: Input mode (reset state)
1: Output: Output mode 10 MHz
2: Output2: Output mode 2 MHz
3: Output50: Output mode 50 MHz

CNF5

Bits 22-23: Port n.5 configuration bits.

Allowed values:
0: PushPull: Analog mode / Push-Pull mode
1: OpenDrain: Floating input (reset state) / Open Drain-Mode
2: AltPushPull: Input with pull-up/pull-down / Alternate Function Push-Pull Mode
3: AltOpenDrain: Alternate Function Open-Drain Mode

MODE6

Bits 24-25: Port n.6 mode bits.

Allowed values:
0: Input: Input mode (reset state)
1: Output: Output mode 10 MHz
2: Output2: Output mode 2 MHz
3: Output50: Output mode 50 MHz

CNF6

Bits 26-27: Port n.6 configuration bits.

Allowed values:
0: PushPull: Analog mode / Push-Pull mode
1: OpenDrain: Floating input (reset state) / Open Drain-Mode
2: AltPushPull: Input with pull-up/pull-down / Alternate Function Push-Pull Mode
3: AltOpenDrain: Alternate Function Open-Drain Mode

MODE7

Bits 28-29: Port n.7 mode bits.

Allowed values:
0: Input: Input mode (reset state)
1: Output: Output mode 10 MHz
2: Output2: Output mode 2 MHz
3: Output50: Output mode 50 MHz

CNF7

Bits 30-31: Port n.7 configuration bits.

Allowed values:
0: PushPull: Analog mode / Push-Pull mode
1: OpenDrain: Floating input (reset state) / Open Drain-Mode
2: AltPushPull: Input with pull-up/pull-down / Alternate Function Push-Pull Mode
3: AltOpenDrain: Alternate Function Open-Drain Mode

CRH

Port configuration register high (GPIOn_CRL)

Offset: 0x4, reset: 0x44444444, access: read-write

16/16 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CNF15
rw
MODE15
rw
CNF14
rw
MODE14
rw
CNF13
rw
MODE13
rw
CNF12
rw
MODE12
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CNF11
rw
MODE11
rw
CNF10
rw
MODE10
rw
CNF9
rw
MODE9
rw
CNF8
rw
MODE8
rw
Toggle Fields.

MODE8

Bits 0-1: Port n.8 mode bits.

Allowed values:
0: Input: Input mode (reset state)
1: Output: Output mode 10 MHz
2: Output2: Output mode 2 MHz
3: Output50: Output mode 50 MHz

CNF8

Bits 2-3: Port n.8 configuration bits.

Allowed values:
0: PushPull: Analog mode / Push-Pull mode
1: OpenDrain: Floating input (reset state) / Open Drain-Mode
2: AltPushPull: Input with pull-up/pull-down / Alternate Function Push-Pull Mode
3: AltOpenDrain: Alternate Function Open-Drain Mode

MODE9

Bits 4-5: Port n.9 mode bits.

Allowed values:
0: Input: Input mode (reset state)
1: Output: Output mode 10 MHz
2: Output2: Output mode 2 MHz
3: Output50: Output mode 50 MHz

CNF9

Bits 6-7: Port n.9 configuration bits.

Allowed values:
0: PushPull: Analog mode / Push-Pull mode
1: OpenDrain: Floating input (reset state) / Open Drain-Mode
2: AltPushPull: Input with pull-up/pull-down / Alternate Function Push-Pull Mode
3: AltOpenDrain: Alternate Function Open-Drain Mode

MODE10

Bits 8-9: Port n.10 mode bits.

Allowed values:
0: Input: Input mode (reset state)
1: Output: Output mode 10 MHz
2: Output2: Output mode 2 MHz
3: Output50: Output mode 50 MHz

CNF10

Bits 10-11: Port n.10 configuration bits.

Allowed values:
0: PushPull: Analog mode / Push-Pull mode
1: OpenDrain: Floating input (reset state) / Open Drain-Mode
2: AltPushPull: Input with pull-up/pull-down / Alternate Function Push-Pull Mode
3: AltOpenDrain: Alternate Function Open-Drain Mode

MODE11

Bits 12-13: Port n.11 mode bits.

Allowed values:
0: Input: Input mode (reset state)
1: Output: Output mode 10 MHz
2: Output2: Output mode 2 MHz
3: Output50: Output mode 50 MHz

CNF11

Bits 14-15: Port n.11 configuration bits.

Allowed values:
0: PushPull: Analog mode / Push-Pull mode
1: OpenDrain: Floating input (reset state) / Open Drain-Mode
2: AltPushPull: Input with pull-up/pull-down / Alternate Function Push-Pull Mode
3: AltOpenDrain: Alternate Function Open-Drain Mode

MODE12

Bits 16-17: Port n.12 mode bits.

Allowed values:
0: Input: Input mode (reset state)
1: Output: Output mode 10 MHz
2: Output2: Output mode 2 MHz
3: Output50: Output mode 50 MHz

CNF12

Bits 18-19: Port n.12 configuration bits.

Allowed values:
0: PushPull: Analog mode / Push-Pull mode
1: OpenDrain: Floating input (reset state) / Open Drain-Mode
2: AltPushPull: Input with pull-up/pull-down / Alternate Function Push-Pull Mode
3: AltOpenDrain: Alternate Function Open-Drain Mode

MODE13

Bits 20-21: Port n.13 mode bits.

Allowed values:
0: Input: Input mode (reset state)
1: Output: Output mode 10 MHz
2: Output2: Output mode 2 MHz
3: Output50: Output mode 50 MHz

CNF13

Bits 22-23: Port n.13 configuration bits.

Allowed values:
0: PushPull: Analog mode / Push-Pull mode
1: OpenDrain: Floating input (reset state) / Open Drain-Mode
2: AltPushPull: Input with pull-up/pull-down / Alternate Function Push-Pull Mode
3: AltOpenDrain: Alternate Function Open-Drain Mode

MODE14

Bits 24-25: Port n.14 mode bits.

Allowed values:
0: Input: Input mode (reset state)
1: Output: Output mode 10 MHz
2: Output2: Output mode 2 MHz
3: Output50: Output mode 50 MHz

CNF14

Bits 26-27: Port n.14 configuration bits.

Allowed values:
0: PushPull: Analog mode / Push-Pull mode
1: OpenDrain: Floating input (reset state) / Open Drain-Mode
2: AltPushPull: Input with pull-up/pull-down / Alternate Function Push-Pull Mode
3: AltOpenDrain: Alternate Function Open-Drain Mode

MODE15

Bits 28-29: Port n.15 mode bits.

Allowed values:
0: Input: Input mode (reset state)
1: Output: Output mode 10 MHz
2: Output2: Output mode 2 MHz
3: Output50: Output mode 50 MHz

CNF15

Bits 30-31: Port n.15 configuration bits.

Allowed values:
0: PushPull: Analog mode / Push-Pull mode
1: OpenDrain: Floating input (reset state) / Open Drain-Mode
2: AltPushPull: Input with pull-up/pull-down / Alternate Function Push-Pull Mode
3: AltOpenDrain: Alternate Function Open-Drain Mode

IDR

Port input data register (GPIOn_IDR)

Offset: 0x8, reset: 0x00000000, access: read-only

16/16 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
IDR15
r
IDR14
r
IDR13
r
IDR12
r
IDR11
r
IDR10
r
IDR9
r
IDR8
r
IDR7
r
IDR6
r
IDR5
r
IDR4
r
IDR3
r
IDR2
r
IDR1
r
IDR0
r
Toggle Fields.

IDR0

Bit 0: Port input data.

Allowed values:
1: High: Input is logic high
0: Low: Input is logic low

IDR1

Bit 1: Port input data.

Allowed values:
1: High: Input is logic high
0: Low: Input is logic low

IDR2

Bit 2: Port input data.

Allowed values:
1: High: Input is logic high
0: Low: Input is logic low

IDR3

Bit 3: Port input data.

Allowed values:
1: High: Input is logic high
0: Low: Input is logic low

IDR4

Bit 4: Port input data.

Allowed values:
1: High: Input is logic high
0: Low: Input is logic low

IDR5

Bit 5: Port input data.

Allowed values:
1: High: Input is logic high
0: Low: Input is logic low

IDR6

Bit 6: Port input data.

Allowed values:
1: High: Input is logic high
0: Low: Input is logic low

IDR7

Bit 7: Port input data.

Allowed values:
1: High: Input is logic high
0: Low: Input is logic low

IDR8

Bit 8: Port input data.

Allowed values:
1: High: Input is logic high
0: Low: Input is logic low

IDR9

Bit 9: Port input data.

Allowed values:
1: High: Input is logic high
0: Low: Input is logic low

IDR10

Bit 10: Port input data.

Allowed values:
1: High: Input is logic high
0: Low: Input is logic low

IDR11

Bit 11: Port input data.

Allowed values:
1: High: Input is logic high
0: Low: Input is logic low

IDR12

Bit 12: Port input data.

Allowed values:
1: High: Input is logic high
0: Low: Input is logic low

IDR13

Bit 13: Port input data.

Allowed values:
1: High: Input is logic high
0: Low: Input is logic low

IDR14

Bit 14: Port input data.

Allowed values:
1: High: Input is logic high
0: Low: Input is logic low

IDR15

Bit 15: Port input data.

Allowed values:
1: High: Input is logic high
0: Low: Input is logic low

ODR

Port output data register (GPIOn_ODR)

Offset: 0xC, reset: 0x00000000, access: read-write

16/16 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ODR15
rw
ODR14
rw
ODR13
rw
ODR12
rw
ODR11
rw
ODR10
rw
ODR9
rw
ODR8
rw
ODR7
rw
ODR6
rw
ODR5
rw
ODR4
rw
ODR3
rw
ODR2
rw
ODR1
rw
ODR0
rw
Toggle Fields.

ODR0

Bit 0: Port output data.

Allowed values:
1: High: Set output to logic high
0: Low: Set output to logic low

ODR1

Bit 1: Port output data.

Allowed values:
1: High: Set output to logic high
0: Low: Set output to logic low

ODR2

Bit 2: Port output data.

Allowed values:
1: High: Set output to logic high
0: Low: Set output to logic low

ODR3

Bit 3: Port output data.

Allowed values:
1: High: Set output to logic high
0: Low: Set output to logic low

ODR4

Bit 4: Port output data.

Allowed values:
1: High: Set output to logic high
0: Low: Set output to logic low

ODR5

Bit 5: Port output data.

Allowed values:
1: High: Set output to logic high
0: Low: Set output to logic low

ODR6

Bit 6: Port output data.

Allowed values:
1: High: Set output to logic high
0: Low: Set output to logic low

ODR7

Bit 7: Port output data.

Allowed values:
1: High: Set output to logic high
0: Low: Set output to logic low

ODR8

Bit 8: Port output data.

Allowed values:
1: High: Set output to logic high
0: Low: Set output to logic low

ODR9

Bit 9: Port output data.

Allowed values:
1: High: Set output to logic high
0: Low: Set output to logic low

ODR10

Bit 10: Port output data.

Allowed values:
1: High: Set output to logic high
0: Low: Set output to logic low

ODR11

Bit 11: Port output data.

Allowed values:
1: High: Set output to logic high
0: Low: Set output to logic low

ODR12

Bit 12: Port output data.

Allowed values:
1: High: Set output to logic high
0: Low: Set output to logic low

ODR13

Bit 13: Port output data.

Allowed values:
1: High: Set output to logic high
0: Low: Set output to logic low

ODR14

Bit 14: Port output data.

Allowed values:
1: High: Set output to logic high
0: Low: Set output to logic low

ODR15

Bit 15: Port output data.

Allowed values:
1: High: Set output to logic high
0: Low: Set output to logic low

BSRR

Port bit set/reset register (GPIOn_BSRR)

Offset: 0x10, reset: 0x00000000, access: write-only

32/32 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
BR15
w
BR14
w
BR13
w
BR12
w
BR11
w
BR10
w
BR9
w
BR8
w
BR7
w
BR6
w
BR5
w
BR4
w
BR3
w
BR2
w
BR1
w
BR0
w
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
BS15
w
BS14
w
BS13
w
BS12
w
BS11
w
BS10
w
BS9
w
BS8
w
BS7
w
BS6
w
BS5
w
BS4
w
BS3
w
BS2
w
BS1
w
BS0
w
Toggle Fields.

BS0

Bit 0: Set bit 0.

Allowed values:
1: Set: Sets the corresponding ODRx bit

BS1

Bit 1: Set bit 1.

Allowed values:
1: Set: Sets the corresponding ODRx bit

BS2

Bit 2: Set bit 1.

Allowed values:
1: Set: Sets the corresponding ODRx bit

BS3

Bit 3: Set bit 3.

Allowed values:
1: Set: Sets the corresponding ODRx bit

BS4

Bit 4: Set bit 4.

Allowed values:
1: Set: Sets the corresponding ODRx bit

BS5

Bit 5: Set bit 5.

Allowed values:
1: Set: Sets the corresponding ODRx bit

BS6

Bit 6: Set bit 6.

Allowed values:
1: Set: Sets the corresponding ODRx bit

BS7

Bit 7: Set bit 7.

Allowed values:
1: Set: Sets the corresponding ODRx bit

BS8

Bit 8: Set bit 8.

Allowed values:
1: Set: Sets the corresponding ODRx bit

BS9

Bit 9: Set bit 9.

Allowed values:
1: Set: Sets the corresponding ODRx bit

BS10

Bit 10: Set bit 10.

Allowed values:
1: Set: Sets the corresponding ODRx bit

BS11

Bit 11: Set bit 11.

Allowed values:
1: Set: Sets the corresponding ODRx bit

BS12

Bit 12: Set bit 12.

Allowed values:
1: Set: Sets the corresponding ODRx bit

BS13

Bit 13: Set bit 13.

Allowed values:
1: Set: Sets the corresponding ODRx bit

BS14

Bit 14: Set bit 14.

Allowed values:
1: Set: Sets the corresponding ODRx bit

BS15

Bit 15: Set bit 15.

Allowed values:
1: Set: Sets the corresponding ODRx bit

BR0

Bit 16: Reset bit 0.

Allowed values:
1: Reset: Resets the corresponding ODRx bit

BR1

Bit 17: Reset bit 1.

Allowed values:
1: Reset: Resets the corresponding ODRx bit

BR2

Bit 18: Reset bit 2.

Allowed values:
1: Reset: Resets the corresponding ODRx bit

BR3

Bit 19: Reset bit 3.

Allowed values:
1: Reset: Resets the corresponding ODRx bit

BR4

Bit 20: Reset bit 4.

Allowed values:
1: Reset: Resets the corresponding ODRx bit

BR5

Bit 21: Reset bit 5.

Allowed values:
1: Reset: Resets the corresponding ODRx bit

BR6

Bit 22: Reset bit 6.

Allowed values:
1: Reset: Resets the corresponding ODRx bit

BR7

Bit 23: Reset bit 7.

Allowed values:
1: Reset: Resets the corresponding ODRx bit

BR8

Bit 24: Reset bit 8.

Allowed values:
1: Reset: Resets the corresponding ODRx bit

BR9

Bit 25: Reset bit 9.

Allowed values:
1: Reset: Resets the corresponding ODRx bit

BR10

Bit 26: Reset bit 10.

Allowed values:
1: Reset: Resets the corresponding ODRx bit

BR11

Bit 27: Reset bit 11.

Allowed values:
1: Reset: Resets the corresponding ODRx bit

BR12

Bit 28: Reset bit 12.

Allowed values:
1: Reset: Resets the corresponding ODRx bit

BR13

Bit 29: Reset bit 13.

Allowed values:
1: Reset: Resets the corresponding ODRx bit

BR14

Bit 30: Reset bit 14.

Allowed values:
1: Reset: Resets the corresponding ODRx bit

BR15

Bit 31: Reset bit 15.

Allowed values:
1: Reset: Resets the corresponding ODRx bit

BRR

Port bit reset register (GPIOn_BRR)

Offset: 0x14, reset: 0x00000000, access: write-only

16/16 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
BR15
w
BR14
w
BR13
w
BR12
w
BR11
w
BR10
w
BR9
w
BR8
w
BR7
w
BR6
w
BR5
w
BR4
w
BR3
w
BR2
w
BR1
w
BR0
w
Toggle Fields.

BR0

Bit 0: Reset bit 0.

Allowed values:
0: NoAction: No action on the corresponding ODx bit
1: Reset: Reset the ODx bit

BR1

Bit 1: Reset bit 1.

Allowed values:
0: NoAction: No action on the corresponding ODx bit
1: Reset: Reset the ODx bit

BR2

Bit 2: Reset bit 1.

Allowed values:
0: NoAction: No action on the corresponding ODx bit
1: Reset: Reset the ODx bit

BR3

Bit 3: Reset bit 3.

Allowed values:
0: NoAction: No action on the corresponding ODx bit
1: Reset: Reset the ODx bit

BR4

Bit 4: Reset bit 4.

Allowed values:
0: NoAction: No action on the corresponding ODx bit
1: Reset: Reset the ODx bit

BR5

Bit 5: Reset bit 5.

Allowed values:
0: NoAction: No action on the corresponding ODx bit
1: Reset: Reset the ODx bit

BR6

Bit 6: Reset bit 6.

Allowed values:
0: NoAction: No action on the corresponding ODx bit
1: Reset: Reset the ODx bit

BR7

Bit 7: Reset bit 7.

Allowed values:
0: NoAction: No action on the corresponding ODx bit
1: Reset: Reset the ODx bit

BR8

Bit 8: Reset bit 8.

Allowed values:
0: NoAction: No action on the corresponding ODx bit
1: Reset: Reset the ODx bit

BR9

Bit 9: Reset bit 9.

Allowed values:
0: NoAction: No action on the corresponding ODx bit
1: Reset: Reset the ODx bit

BR10

Bit 10: Reset bit 10.

Allowed values:
0: NoAction: No action on the corresponding ODx bit
1: Reset: Reset the ODx bit

BR11

Bit 11: Reset bit 11.

Allowed values:
0: NoAction: No action on the corresponding ODx bit
1: Reset: Reset the ODx bit

BR12

Bit 12: Reset bit 12.

Allowed values:
0: NoAction: No action on the corresponding ODx bit
1: Reset: Reset the ODx bit

BR13

Bit 13: Reset bit 13.

Allowed values:
0: NoAction: No action on the corresponding ODx bit
1: Reset: Reset the ODx bit

BR14

Bit 14: Reset bit 14.

Allowed values:
0: NoAction: No action on the corresponding ODx bit
1: Reset: Reset the ODx bit

BR15

Bit 15: Reset bit 15.

Allowed values:
0: NoAction: No action on the corresponding ODx bit
1: Reset: Reset the ODx bit

LCKR

Port configuration lock register

Offset: 0x18, reset: 0x00000000, access: read-write

17/17 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LCKK
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LCK15
rw
LCK14
rw
LCK13
rw
LCK12
rw
LCK11
rw
LCK10
rw
LCK9
rw
LCK8
rw
LCK7
rw
LCK6
rw
LCK5
rw
LCK4
rw
LCK3
rw
LCK2
rw
LCK1
rw
LCK0
rw
Toggle Fields.

LCK0

Bit 0: Port A Lock bit 0.

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCK1

Bit 1: Port A Lock bit 1.

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCK2

Bit 2: Port A Lock bit 2.

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCK3

Bit 3: Port A Lock bit 3.

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCK4

Bit 4: Port A Lock bit 4.

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCK5

Bit 5: Port A Lock bit 5.

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCK6

Bit 6: Port A Lock bit 6.

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCK7

Bit 7: Port A Lock bit 7.

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCK8

Bit 8: Port A Lock bit 8.

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCK9

Bit 9: Port A Lock bit 9.

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCK10

Bit 10: Port A Lock bit 10.

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCK11

Bit 11: Port A Lock bit 11.

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCK12

Bit 12: Port A Lock bit 12.

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCK13

Bit 13: Port A Lock bit 13.

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCK14

Bit 14: Port A Lock bit 14.

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCK15

Bit 15: Port A Lock bit 15.

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCKK

Bit 16: Lock key.

Allowed values:
0: NotActive: Port configuration lock key not active
1: Active: Port configuration lock key active

GPIOE

0x40011800: General purpose I/O

129/129 fields covered. Toggle Registers.

CRL

Port configuration register low (GPIOn_CRL)

Offset: 0x0, reset: 0x44444444, access: read-write

16/16 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CNF7
rw
MODE7
rw
CNF6
rw
MODE6
rw
CNF5
rw
MODE5
rw
CNF4
rw
MODE4
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CNF3
rw
MODE3
rw
CNF2
rw
MODE2
rw
CNF1
rw
MODE1
rw
CNF0
rw
MODE0
rw
Toggle Fields.

MODE0

Bits 0-1: Port n.0 mode bits.

Allowed values:
0: Input: Input mode (reset state)
1: Output: Output mode 10 MHz
2: Output2: Output mode 2 MHz
3: Output50: Output mode 50 MHz

CNF0

Bits 2-3: Port n.0 configuration bits.

Allowed values:
0: PushPull: Analog mode / Push-Pull mode
1: OpenDrain: Floating input (reset state) / Open Drain-Mode
2: AltPushPull: Input with pull-up/pull-down / Alternate Function Push-Pull Mode
3: AltOpenDrain: Alternate Function Open-Drain Mode

MODE1

Bits 4-5: Port n.1 mode bits.

Allowed values:
0: Input: Input mode (reset state)
1: Output: Output mode 10 MHz
2: Output2: Output mode 2 MHz
3: Output50: Output mode 50 MHz

CNF1

Bits 6-7: Port n.1 configuration bits.

Allowed values:
0: PushPull: Analog mode / Push-Pull mode
1: OpenDrain: Floating input (reset state) / Open Drain-Mode
2: AltPushPull: Input with pull-up/pull-down / Alternate Function Push-Pull Mode
3: AltOpenDrain: Alternate Function Open-Drain Mode

MODE2

Bits 8-9: Port n.2 mode bits.

Allowed values:
0: Input: Input mode (reset state)
1: Output: Output mode 10 MHz
2: Output2: Output mode 2 MHz
3: Output50: Output mode 50 MHz

CNF2

Bits 10-11: Port n.2 configuration bits.

Allowed values:
0: PushPull: Analog mode / Push-Pull mode
1: OpenDrain: Floating input (reset state) / Open Drain-Mode
2: AltPushPull: Input with pull-up/pull-down / Alternate Function Push-Pull Mode
3: AltOpenDrain: Alternate Function Open-Drain Mode

MODE3

Bits 12-13: Port n.3 mode bits.

Allowed values:
0: Input: Input mode (reset state)
1: Output: Output mode 10 MHz
2: Output2: Output mode 2 MHz
3: Output50: Output mode 50 MHz

CNF3

Bits 14-15: Port n.3 configuration bits.

Allowed values:
0: PushPull: Analog mode / Push-Pull mode
1: OpenDrain: Floating input (reset state) / Open Drain-Mode
2: AltPushPull: Input with pull-up/pull-down / Alternate Function Push-Pull Mode
3: AltOpenDrain: Alternate Function Open-Drain Mode

MODE4

Bits 16-17: Port n.4 mode bits.

Allowed values:
0: Input: Input mode (reset state)
1: Output: Output mode 10 MHz
2: Output2: Output mode 2 MHz
3: Output50: Output mode 50 MHz

CNF4

Bits 18-19: Port n.4 configuration bits.

Allowed values:
0: PushPull: Analog mode / Push-Pull mode
1: OpenDrain: Floating input (reset state) / Open Drain-Mode
2: AltPushPull: Input with pull-up/pull-down / Alternate Function Push-Pull Mode
3: AltOpenDrain: Alternate Function Open-Drain Mode

MODE5

Bits 20-21: Port n.5 mode bits.

Allowed values:
0: Input: Input mode (reset state)
1: Output: Output mode 10 MHz
2: Output2: Output mode 2 MHz
3: Output50: Output mode 50 MHz

CNF5

Bits 22-23: Port n.5 configuration bits.

Allowed values:
0: PushPull: Analog mode / Push-Pull mode
1: OpenDrain: Floating input (reset state) / Open Drain-Mode
2: AltPushPull: Input with pull-up/pull-down / Alternate Function Push-Pull Mode
3: AltOpenDrain: Alternate Function Open-Drain Mode

MODE6

Bits 24-25: Port n.6 mode bits.

Allowed values:
0: Input: Input mode (reset state)
1: Output: Output mode 10 MHz
2: Output2: Output mode 2 MHz
3: Output50: Output mode 50 MHz

CNF6

Bits 26-27: Port n.6 configuration bits.

Allowed values:
0: PushPull: Analog mode / Push-Pull mode
1: OpenDrain: Floating input (reset state) / Open Drain-Mode
2: AltPushPull: Input with pull-up/pull-down / Alternate Function Push-Pull Mode
3: AltOpenDrain: Alternate Function Open-Drain Mode

MODE7

Bits 28-29: Port n.7 mode bits.

Allowed values:
0: Input: Input mode (reset state)
1: Output: Output mode 10 MHz
2: Output2: Output mode 2 MHz
3: Output50: Output mode 50 MHz

CNF7

Bits 30-31: Port n.7 configuration bits.

Allowed values:
0: PushPull: Analog mode / Push-Pull mode
1: OpenDrain: Floating input (reset state) / Open Drain-Mode
2: AltPushPull: Input with pull-up/pull-down / Alternate Function Push-Pull Mode
3: AltOpenDrain: Alternate Function Open-Drain Mode

CRH

Port configuration register high (GPIOn_CRL)

Offset: 0x4, reset: 0x44444444, access: read-write

16/16 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CNF15
rw
MODE15
rw
CNF14
rw
MODE14
rw
CNF13
rw
MODE13
rw
CNF12
rw
MODE12
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CNF11
rw
MODE11
rw
CNF10
rw
MODE10
rw
CNF9
rw
MODE9
rw
CNF8
rw
MODE8
rw
Toggle Fields.

MODE8

Bits 0-1: Port n.8 mode bits.

Allowed values:
0: Input: Input mode (reset state)
1: Output: Output mode 10 MHz
2: Output2: Output mode 2 MHz
3: Output50: Output mode 50 MHz

CNF8

Bits 2-3: Port n.8 configuration bits.

Allowed values:
0: PushPull: Analog mode / Push-Pull mode
1: OpenDrain: Floating input (reset state) / Open Drain-Mode
2: AltPushPull: Input with pull-up/pull-down / Alternate Function Push-Pull Mode
3: AltOpenDrain: Alternate Function Open-Drain Mode

MODE9

Bits 4-5: Port n.9 mode bits.

Allowed values:
0: Input: Input mode (reset state)
1: Output: Output mode 10 MHz
2: Output2: Output mode 2 MHz
3: Output50: Output mode 50 MHz

CNF9

Bits 6-7: Port n.9 configuration bits.

Allowed values:
0: PushPull: Analog mode / Push-Pull mode
1: OpenDrain: Floating input (reset state) / Open Drain-Mode
2: AltPushPull: Input with pull-up/pull-down / Alternate Function Push-Pull Mode
3: AltOpenDrain: Alternate Function Open-Drain Mode

MODE10

Bits 8-9: Port n.10 mode bits.

Allowed values:
0: Input: Input mode (reset state)
1: Output: Output mode 10 MHz
2: Output2: Output mode 2 MHz
3: Output50: Output mode 50 MHz

CNF10

Bits 10-11: Port n.10 configuration bits.

Allowed values:
0: PushPull: Analog mode / Push-Pull mode
1: OpenDrain: Floating input (reset state) / Open Drain-Mode
2: AltPushPull: Input with pull-up/pull-down / Alternate Function Push-Pull Mode
3: AltOpenDrain: Alternate Function Open-Drain Mode

MODE11

Bits 12-13: Port n.11 mode bits.

Allowed values:
0: Input: Input mode (reset state)
1: Output: Output mode 10 MHz
2: Output2: Output mode 2 MHz
3: Output50: Output mode 50 MHz

CNF11

Bits 14-15: Port n.11 configuration bits.

Allowed values:
0: PushPull: Analog mode / Push-Pull mode
1: OpenDrain: Floating input (reset state) / Open Drain-Mode
2: AltPushPull: Input with pull-up/pull-down / Alternate Function Push-Pull Mode
3: AltOpenDrain: Alternate Function Open-Drain Mode

MODE12

Bits 16-17: Port n.12 mode bits.

Allowed values:
0: Input: Input mode (reset state)
1: Output: Output mode 10 MHz
2: Output2: Output mode 2 MHz
3: Output50: Output mode 50 MHz

CNF12

Bits 18-19: Port n.12 configuration bits.

Allowed values:
0: PushPull: Analog mode / Push-Pull mode
1: OpenDrain: Floating input (reset state) / Open Drain-Mode
2: AltPushPull: Input with pull-up/pull-down / Alternate Function Push-Pull Mode
3: AltOpenDrain: Alternate Function Open-Drain Mode

MODE13

Bits 20-21: Port n.13 mode bits.

Allowed values:
0: Input: Input mode (reset state)
1: Output: Output mode 10 MHz
2: Output2: Output mode 2 MHz
3: Output50: Output mode 50 MHz

CNF13

Bits 22-23: Port n.13 configuration bits.

Allowed values:
0: PushPull: Analog mode / Push-Pull mode
1: OpenDrain: Floating input (reset state) / Open Drain-Mode
2: AltPushPull: Input with pull-up/pull-down / Alternate Function Push-Pull Mode
3: AltOpenDrain: Alternate Function Open-Drain Mode

MODE14

Bits 24-25: Port n.14 mode bits.

Allowed values:
0: Input: Input mode (reset state)
1: Output: Output mode 10 MHz
2: Output2: Output mode 2 MHz
3: Output50: Output mode 50 MHz

CNF14

Bits 26-27: Port n.14 configuration bits.

Allowed values:
0: PushPull: Analog mode / Push-Pull mode
1: OpenDrain: Floating input (reset state) / Open Drain-Mode
2: AltPushPull: Input with pull-up/pull-down / Alternate Function Push-Pull Mode
3: AltOpenDrain: Alternate Function Open-Drain Mode

MODE15

Bits 28-29: Port n.15 mode bits.

Allowed values:
0: Input: Input mode (reset state)
1: Output: Output mode 10 MHz
2: Output2: Output mode 2 MHz
3: Output50: Output mode 50 MHz

CNF15

Bits 30-31: Port n.15 configuration bits.

Allowed values:
0: PushPull: Analog mode / Push-Pull mode
1: OpenDrain: Floating input (reset state) / Open Drain-Mode
2: AltPushPull: Input with pull-up/pull-down / Alternate Function Push-Pull Mode
3: AltOpenDrain: Alternate Function Open-Drain Mode

IDR

Port input data register (GPIOn_IDR)

Offset: 0x8, reset: 0x00000000, access: read-only

16/16 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
IDR15
r
IDR14
r
IDR13
r
IDR12
r
IDR11
r
IDR10
r
IDR9
r
IDR8
r
IDR7
r
IDR6
r
IDR5
r
IDR4
r
IDR3
r
IDR2
r
IDR1
r
IDR0
r
Toggle Fields.

IDR0

Bit 0: Port input data.

Allowed values:
1: High: Input is logic high
0: Low: Input is logic low

IDR1

Bit 1: Port input data.

Allowed values:
1: High: Input is logic high
0: Low: Input is logic low

IDR2

Bit 2: Port input data.

Allowed values:
1: High: Input is logic high
0: Low: Input is logic low

IDR3

Bit 3: Port input data.

Allowed values:
1: High: Input is logic high
0: Low: Input is logic low

IDR4

Bit 4: Port input data.

Allowed values:
1: High: Input is logic high
0: Low: Input is logic low

IDR5

Bit 5: Port input data.

Allowed values:
1: High: Input is logic high
0: Low: Input is logic low

IDR6

Bit 6: Port input data.

Allowed values:
1: High: Input is logic high
0: Low: Input is logic low

IDR7

Bit 7: Port input data.

Allowed values:
1: High: Input is logic high
0: Low: Input is logic low

IDR8

Bit 8: Port input data.

Allowed values:
1: High: Input is logic high
0: Low: Input is logic low

IDR9

Bit 9: Port input data.

Allowed values:
1: High: Input is logic high
0: Low: Input is logic low

IDR10

Bit 10: Port input data.

Allowed values:
1: High: Input is logic high
0: Low: Input is logic low

IDR11

Bit 11: Port input data.

Allowed values:
1: High: Input is logic high
0: Low: Input is logic low

IDR12

Bit 12: Port input data.

Allowed values:
1: High: Input is logic high
0: Low: Input is logic low

IDR13

Bit 13: Port input data.

Allowed values:
1: High: Input is logic high
0: Low: Input is logic low

IDR14

Bit 14: Port input data.

Allowed values:
1: High: Input is logic high
0: Low: Input is logic low

IDR15

Bit 15: Port input data.

Allowed values:
1: High: Input is logic high
0: Low: Input is logic low

ODR

Port output data register (GPIOn_ODR)

Offset: 0xC, reset: 0x00000000, access: read-write

16/16 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ODR15
rw
ODR14
rw
ODR13
rw
ODR12
rw
ODR11
rw
ODR10
rw
ODR9
rw
ODR8
rw
ODR7
rw
ODR6
rw
ODR5
rw
ODR4
rw
ODR3
rw
ODR2
rw
ODR1
rw
ODR0
rw
Toggle Fields.

ODR0

Bit 0: Port output data.

Allowed values:
1: High: Set output to logic high
0: Low: Set output to logic low

ODR1

Bit 1: Port output data.

Allowed values:
1: High: Set output to logic high
0: Low: Set output to logic low

ODR2

Bit 2: Port output data.

Allowed values:
1: High: Set output to logic high
0: Low: Set output to logic low

ODR3

Bit 3: Port output data.

Allowed values:
1: High: Set output to logic high
0: Low: Set output to logic low

ODR4

Bit 4: Port output data.

Allowed values:
1: High: Set output to logic high
0: Low: Set output to logic low

ODR5

Bit 5: Port output data.

Allowed values:
1: High: Set output to logic high
0: Low: Set output to logic low

ODR6

Bit 6: Port output data.

Allowed values:
1: High: Set output to logic high
0: Low: Set output to logic low

ODR7

Bit 7: Port output data.

Allowed values:
1: High: Set output to logic high
0: Low: Set output to logic low

ODR8

Bit 8: Port output data.

Allowed values:
1: High: Set output to logic high
0: Low: Set output to logic low

ODR9

Bit 9: Port output data.

Allowed values:
1: High: Set output to logic high
0: Low: Set output to logic low

ODR10

Bit 10: Port output data.

Allowed values:
1: High: Set output to logic high
0: Low: Set output to logic low

ODR11

Bit 11: Port output data.

Allowed values:
1: High: Set output to logic high
0: Low: Set output to logic low

ODR12

Bit 12: Port output data.

Allowed values:
1: High: Set output to logic high
0: Low: Set output to logic low

ODR13

Bit 13: Port output data.

Allowed values:
1: High: Set output to logic high
0: Low: Set output to logic low

ODR14

Bit 14: Port output data.

Allowed values:
1: High: Set output to logic high
0: Low: Set output to logic low

ODR15

Bit 15: Port output data.

Allowed values:
1: High: Set output to logic high
0: Low: Set output to logic low

BSRR

Port bit set/reset register (GPIOn_BSRR)

Offset: 0x10, reset: 0x00000000, access: write-only

32/32 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
BR15
w
BR14
w
BR13
w
BR12
w
BR11
w
BR10
w
BR9
w
BR8
w
BR7
w
BR6
w
BR5
w
BR4
w
BR3
w
BR2
w
BR1
w
BR0
w
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
BS15
w
BS14
w
BS13
w
BS12
w
BS11
w
BS10
w
BS9
w
BS8
w
BS7
w
BS6
w
BS5
w
BS4
w
BS3
w
BS2
w
BS1
w
BS0
w
Toggle Fields.

BS0

Bit 0: Set bit 0.

Allowed values:
1: Set: Sets the corresponding ODRx bit

BS1

Bit 1: Set bit 1.

Allowed values:
1: Set: Sets the corresponding ODRx bit

BS2

Bit 2: Set bit 1.

Allowed values:
1: Set: Sets the corresponding ODRx bit

BS3

Bit 3: Set bit 3.

Allowed values:
1: Set: Sets the corresponding ODRx bit

BS4

Bit 4: Set bit 4.

Allowed values:
1: Set: Sets the corresponding ODRx bit

BS5

Bit 5: Set bit 5.

Allowed values:
1: Set: Sets the corresponding ODRx bit

BS6

Bit 6: Set bit 6.

Allowed values:
1: Set: Sets the corresponding ODRx bit

BS7

Bit 7: Set bit 7.

Allowed values:
1: Set: Sets the corresponding ODRx bit

BS8

Bit 8: Set bit 8.

Allowed values:
1: Set: Sets the corresponding ODRx bit

BS9

Bit 9: Set bit 9.

Allowed values:
1: Set: Sets the corresponding ODRx bit

BS10

Bit 10: Set bit 10.

Allowed values:
1: Set: Sets the corresponding ODRx bit

BS11

Bit 11: Set bit 11.

Allowed values:
1: Set: Sets the corresponding ODRx bit

BS12

Bit 12: Set bit 12.

Allowed values:
1: Set: Sets the corresponding ODRx bit

BS13

Bit 13: Set bit 13.

Allowed values:
1: Set: Sets the corresponding ODRx bit

BS14

Bit 14: Set bit 14.

Allowed values:
1: Set: Sets the corresponding ODRx bit

BS15

Bit 15: Set bit 15.

Allowed values:
1: Set: Sets the corresponding ODRx bit

BR0

Bit 16: Reset bit 0.

Allowed values:
1: Reset: Resets the corresponding ODRx bit

BR1

Bit 17: Reset bit 1.

Allowed values:
1: Reset: Resets the corresponding ODRx bit

BR2

Bit 18: Reset bit 2.

Allowed values:
1: Reset: Resets the corresponding ODRx bit

BR3

Bit 19: Reset bit 3.

Allowed values:
1: Reset: Resets the corresponding ODRx bit

BR4

Bit 20: Reset bit 4.

Allowed values:
1: Reset: Resets the corresponding ODRx bit

BR5

Bit 21: Reset bit 5.

Allowed values:
1: Reset: Resets the corresponding ODRx bit

BR6

Bit 22: Reset bit 6.

Allowed values:
1: Reset: Resets the corresponding ODRx bit

BR7

Bit 23: Reset bit 7.

Allowed values:
1: Reset: Resets the corresponding ODRx bit

BR8

Bit 24: Reset bit 8.

Allowed values:
1: Reset: Resets the corresponding ODRx bit

BR9

Bit 25: Reset bit 9.

Allowed values:
1: Reset: Resets the corresponding ODRx bit

BR10

Bit 26: Reset bit 10.

Allowed values:
1: Reset: Resets the corresponding ODRx bit

BR11

Bit 27: Reset bit 11.

Allowed values:
1: Reset: Resets the corresponding ODRx bit

BR12

Bit 28: Reset bit 12.

Allowed values:
1: Reset: Resets the corresponding ODRx bit

BR13

Bit 29: Reset bit 13.

Allowed values:
1: Reset: Resets the corresponding ODRx bit

BR14

Bit 30: Reset bit 14.

Allowed values:
1: Reset: Resets the corresponding ODRx bit

BR15

Bit 31: Reset bit 15.

Allowed values:
1: Reset: Resets the corresponding ODRx bit

BRR

Port bit reset register (GPIOn_BRR)

Offset: 0x14, reset: 0x00000000, access: write-only

16/16 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
BR15
w
BR14
w
BR13
w
BR12
w
BR11
w
BR10
w
BR9
w
BR8
w
BR7
w
BR6
w
BR5
w
BR4
w
BR3
w
BR2
w
BR1
w
BR0
w
Toggle Fields.

BR0

Bit 0: Reset bit 0.

Allowed values:
0: NoAction: No action on the corresponding ODx bit
1: Reset: Reset the ODx bit

BR1

Bit 1: Reset bit 1.

Allowed values:
0: NoAction: No action on the corresponding ODx bit
1: Reset: Reset the ODx bit

BR2

Bit 2: Reset bit 1.

Allowed values:
0: NoAction: No action on the corresponding ODx bit
1: Reset: Reset the ODx bit

BR3

Bit 3: Reset bit 3.

Allowed values:
0: NoAction: No action on the corresponding ODx bit
1: Reset: Reset the ODx bit

BR4

Bit 4: Reset bit 4.

Allowed values:
0: NoAction: No action on the corresponding ODx bit
1: Reset: Reset the ODx bit

BR5

Bit 5: Reset bit 5.

Allowed values:
0: NoAction: No action on the corresponding ODx bit
1: Reset: Reset the ODx bit

BR6

Bit 6: Reset bit 6.

Allowed values:
0: NoAction: No action on the corresponding ODx bit
1: Reset: Reset the ODx bit

BR7

Bit 7: Reset bit 7.

Allowed values:
0: NoAction: No action on the corresponding ODx bit
1: Reset: Reset the ODx bit

BR8

Bit 8: Reset bit 8.

Allowed values:
0: NoAction: No action on the corresponding ODx bit
1: Reset: Reset the ODx bit

BR9

Bit 9: Reset bit 9.

Allowed values:
0: NoAction: No action on the corresponding ODx bit
1: Reset: Reset the ODx bit

BR10

Bit 10: Reset bit 10.

Allowed values:
0: NoAction: No action on the corresponding ODx bit
1: Reset: Reset the ODx bit

BR11

Bit 11: Reset bit 11.

Allowed values:
0: NoAction: No action on the corresponding ODx bit
1: Reset: Reset the ODx bit

BR12

Bit 12: Reset bit 12.

Allowed values:
0: NoAction: No action on the corresponding ODx bit
1: Reset: Reset the ODx bit

BR13

Bit 13: Reset bit 13.

Allowed values:
0: NoAction: No action on the corresponding ODx bit
1: Reset: Reset the ODx bit

BR14

Bit 14: Reset bit 14.

Allowed values:
0: NoAction: No action on the corresponding ODx bit
1: Reset: Reset the ODx bit

BR15

Bit 15: Reset bit 15.

Allowed values:
0: NoAction: No action on the corresponding ODx bit
1: Reset: Reset the ODx bit

LCKR

Port configuration lock register

Offset: 0x18, reset: 0x00000000, access: read-write

17/17 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LCKK
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LCK15
rw
LCK14
rw
LCK13
rw
LCK12
rw
LCK11
rw
LCK10
rw
LCK9
rw
LCK8
rw
LCK7
rw
LCK6
rw
LCK5
rw
LCK4
rw
LCK3
rw
LCK2
rw
LCK1
rw
LCK0
rw
Toggle Fields.

LCK0

Bit 0: Port A Lock bit 0.

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCK1

Bit 1: Port A Lock bit 1.

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCK2

Bit 2: Port A Lock bit 2.

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCK3

Bit 3: Port A Lock bit 3.

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCK4

Bit 4: Port A Lock bit 4.

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCK5

Bit 5: Port A Lock bit 5.

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCK6

Bit 6: Port A Lock bit 6.

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCK7

Bit 7: Port A Lock bit 7.

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCK8

Bit 8: Port A Lock bit 8.

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCK9

Bit 9: Port A Lock bit 9.

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCK10

Bit 10: Port A Lock bit 10.

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCK11

Bit 11: Port A Lock bit 11.

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCK12

Bit 12: Port A Lock bit 12.

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCK13

Bit 13: Port A Lock bit 13.

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCK14

Bit 14: Port A Lock bit 14.

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCK15

Bit 15: Port A Lock bit 15.

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCKK

Bit 16: Lock key.

Allowed values:
0: NotActive: Port configuration lock key not active
1: Active: Port configuration lock key active

GPIOF

0x40011C00: General purpose I/O

129/129 fields covered. Toggle Registers.

CRL

Port configuration register low (GPIOn_CRL)

Offset: 0x0, reset: 0x44444444, access: read-write

16/16 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CNF7
rw
MODE7
rw
CNF6
rw
MODE6
rw
CNF5
rw
MODE5
rw
CNF4
rw
MODE4
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CNF3
rw
MODE3
rw
CNF2
rw
MODE2
rw
CNF1
rw
MODE1
rw
CNF0
rw
MODE0
rw
Toggle Fields.

MODE0

Bits 0-1: Port n.0 mode bits.

Allowed values:
0: Input: Input mode (reset state)
1: Output: Output mode 10 MHz
2: Output2: Output mode 2 MHz
3: Output50: Output mode 50 MHz

CNF0

Bits 2-3: Port n.0 configuration bits.

Allowed values:
0: PushPull: Analog mode / Push-Pull mode
1: OpenDrain: Floating input (reset state) / Open Drain-Mode
2: AltPushPull: Input with pull-up/pull-down / Alternate Function Push-Pull Mode
3: AltOpenDrain: Alternate Function Open-Drain Mode

MODE1

Bits 4-5: Port n.1 mode bits.

Allowed values:
0: Input: Input mode (reset state)
1: Output: Output mode 10 MHz
2: Output2: Output mode 2 MHz
3: Output50: Output mode 50 MHz

CNF1

Bits 6-7: Port n.1 configuration bits.

Allowed values:
0: PushPull: Analog mode / Push-Pull mode
1: OpenDrain: Floating input (reset state) / Open Drain-Mode
2: AltPushPull: Input with pull-up/pull-down / Alternate Function Push-Pull Mode
3: AltOpenDrain: Alternate Function Open-Drain Mode

MODE2

Bits 8-9: Port n.2 mode bits.

Allowed values:
0: Input: Input mode (reset state)
1: Output: Output mode 10 MHz
2: Output2: Output mode 2 MHz
3: Output50: Output mode 50 MHz

CNF2

Bits 10-11: Port n.2 configuration bits.

Allowed values:
0: PushPull: Analog mode / Push-Pull mode
1: OpenDrain: Floating input (reset state) / Open Drain-Mode
2: AltPushPull: Input with pull-up/pull-down / Alternate Function Push-Pull Mode
3: AltOpenDrain: Alternate Function Open-Drain Mode

MODE3

Bits 12-13: Port n.3 mode bits.

Allowed values:
0: Input: Input mode (reset state)
1: Output: Output mode 10 MHz
2: Output2: Output mode 2 MHz
3: Output50: Output mode 50 MHz

CNF3

Bits 14-15: Port n.3 configuration bits.

Allowed values:
0: PushPull: Analog mode / Push-Pull mode
1: OpenDrain: Floating input (reset state) / Open Drain-Mode
2: AltPushPull: Input with pull-up/pull-down / Alternate Function Push-Pull Mode
3: AltOpenDrain: Alternate Function Open-Drain Mode

MODE4

Bits 16-17: Port n.4 mode bits.

Allowed values:
0: Input: Input mode (reset state)
1: Output: Output mode 10 MHz
2: Output2: Output mode 2 MHz
3: Output50: Output mode 50 MHz

CNF4

Bits 18-19: Port n.4 configuration bits.

Allowed values:
0: PushPull: Analog mode / Push-Pull mode
1: OpenDrain: Floating input (reset state) / Open Drain-Mode
2: AltPushPull: Input with pull-up/pull-down / Alternate Function Push-Pull Mode
3: AltOpenDrain: Alternate Function Open-Drain Mode

MODE5

Bits 20-21: Port n.5 mode bits.

Allowed values:
0: Input: Input mode (reset state)
1: Output: Output mode 10 MHz
2: Output2: Output mode 2 MHz
3: Output50: Output mode 50 MHz

CNF5

Bits 22-23: Port n.5 configuration bits.

Allowed values:
0: PushPull: Analog mode / Push-Pull mode
1: OpenDrain: Floating input (reset state) / Open Drain-Mode
2: AltPushPull: Input with pull-up/pull-down / Alternate Function Push-Pull Mode
3: AltOpenDrain: Alternate Function Open-Drain Mode

MODE6

Bits 24-25: Port n.6 mode bits.

Allowed values:
0: Input: Input mode (reset state)
1: Output: Output mode 10 MHz
2: Output2: Output mode 2 MHz
3: Output50: Output mode 50 MHz

CNF6

Bits 26-27: Port n.6 configuration bits.

Allowed values:
0: PushPull: Analog mode / Push-Pull mode
1: OpenDrain: Floating input (reset state) / Open Drain-Mode
2: AltPushPull: Input with pull-up/pull-down / Alternate Function Push-Pull Mode
3: AltOpenDrain: Alternate Function Open-Drain Mode

MODE7

Bits 28-29: Port n.7 mode bits.

Allowed values:
0: Input: Input mode (reset state)
1: Output: Output mode 10 MHz
2: Output2: Output mode 2 MHz
3: Output50: Output mode 50 MHz

CNF7

Bits 30-31: Port n.7 configuration bits.

Allowed values:
0: PushPull: Analog mode / Push-Pull mode
1: OpenDrain: Floating input (reset state) / Open Drain-Mode
2: AltPushPull: Input with pull-up/pull-down / Alternate Function Push-Pull Mode
3: AltOpenDrain: Alternate Function Open-Drain Mode

CRH

Port configuration register high (GPIOn_CRL)

Offset: 0x4, reset: 0x44444444, access: read-write

16/16 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CNF15
rw
MODE15
rw
CNF14
rw
MODE14
rw
CNF13
rw
MODE13
rw
CNF12
rw
MODE12
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CNF11
rw
MODE11
rw
CNF10
rw
MODE10
rw
CNF9
rw
MODE9
rw
CNF8
rw
MODE8
rw
Toggle Fields.

MODE8

Bits 0-1: Port n.8 mode bits.

Allowed values:
0: Input: Input mode (reset state)
1: Output: Output mode 10 MHz
2: Output2: Output mode 2 MHz
3: Output50: Output mode 50 MHz

CNF8

Bits 2-3: Port n.8 configuration bits.

Allowed values:
0: PushPull: Analog mode / Push-Pull mode
1: OpenDrain: Floating input (reset state) / Open Drain-Mode
2: AltPushPull: Input with pull-up/pull-down / Alternate Function Push-Pull Mode
3: AltOpenDrain: Alternate Function Open-Drain Mode

MODE9

Bits 4-5: Port n.9 mode bits.

Allowed values:
0: Input: Input mode (reset state)
1: Output: Output mode 10 MHz
2: Output2: Output mode 2 MHz
3: Output50: Output mode 50 MHz

CNF9

Bits 6-7: Port n.9 configuration bits.

Allowed values:
0: PushPull: Analog mode / Push-Pull mode
1: OpenDrain: Floating input (reset state) / Open Drain-Mode
2: AltPushPull: Input with pull-up/pull-down / Alternate Function Push-Pull Mode
3: AltOpenDrain: Alternate Function Open-Drain Mode

MODE10

Bits 8-9: Port n.10 mode bits.

Allowed values:
0: Input: Input mode (reset state)
1: Output: Output mode 10 MHz
2: Output2: Output mode 2 MHz
3: Output50: Output mode 50 MHz

CNF10

Bits 10-11: Port n.10 configuration bits.

Allowed values:
0: PushPull: Analog mode / Push-Pull mode
1: OpenDrain: Floating input (reset state) / Open Drain-Mode
2: AltPushPull: Input with pull-up/pull-down / Alternate Function Push-Pull Mode
3: AltOpenDrain: Alternate Function Open-Drain Mode

MODE11

Bits 12-13: Port n.11 mode bits.

Allowed values:
0: Input: Input mode (reset state)
1: Output: Output mode 10 MHz
2: Output2: Output mode 2 MHz
3: Output50: Output mode 50 MHz

CNF11

Bits 14-15: Port n.11 configuration bits.

Allowed values:
0: PushPull: Analog mode / Push-Pull mode
1: OpenDrain: Floating input (reset state) / Open Drain-Mode
2: AltPushPull: Input with pull-up/pull-down / Alternate Function Push-Pull Mode
3: AltOpenDrain: Alternate Function Open-Drain Mode

MODE12

Bits 16-17: Port n.12 mode bits.

Allowed values:
0: Input: Input mode (reset state)
1: Output: Output mode 10 MHz
2: Output2: Output mode 2 MHz
3: Output50: Output mode 50 MHz

CNF12

Bits 18-19: Port n.12 configuration bits.

Allowed values:
0: PushPull: Analog mode / Push-Pull mode
1: OpenDrain: Floating input (reset state) / Open Drain-Mode
2: AltPushPull: Input with pull-up/pull-down / Alternate Function Push-Pull Mode
3: AltOpenDrain: Alternate Function Open-Drain Mode

MODE13

Bits 20-21: Port n.13 mode bits.

Allowed values:
0: Input: Input mode (reset state)
1: Output: Output mode 10 MHz
2: Output2: Output mode 2 MHz
3: Output50: Output mode 50 MHz

CNF13

Bits 22-23: Port n.13 configuration bits.

Allowed values:
0: PushPull: Analog mode / Push-Pull mode
1: OpenDrain: Floating input (reset state) / Open Drain-Mode
2: AltPushPull: Input with pull-up/pull-down / Alternate Function Push-Pull Mode
3: AltOpenDrain: Alternate Function Open-Drain Mode

MODE14

Bits 24-25: Port n.14 mode bits.

Allowed values:
0: Input: Input mode (reset state)
1: Output: Output mode 10 MHz
2: Output2: Output mode 2 MHz
3: Output50: Output mode 50 MHz

CNF14

Bits 26-27: Port n.14 configuration bits.

Allowed values:
0: PushPull: Analog mode / Push-Pull mode
1: OpenDrain: Floating input (reset state) / Open Drain-Mode
2: AltPushPull: Input with pull-up/pull-down / Alternate Function Push-Pull Mode
3: AltOpenDrain: Alternate Function Open-Drain Mode

MODE15

Bits 28-29: Port n.15 mode bits.

Allowed values:
0: Input: Input mode (reset state)
1: Output: Output mode 10 MHz
2: Output2: Output mode 2 MHz
3: Output50: Output mode 50 MHz

CNF15

Bits 30-31: Port n.15 configuration bits.

Allowed values:
0: PushPull: Analog mode / Push-Pull mode
1: OpenDrain: Floating input (reset state) / Open Drain-Mode
2: AltPushPull: Input with pull-up/pull-down / Alternate Function Push-Pull Mode
3: AltOpenDrain: Alternate Function Open-Drain Mode

IDR

Port input data register (GPIOn_IDR)

Offset: 0x8, reset: 0x00000000, access: read-only

16/16 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
IDR15
r
IDR14
r
IDR13
r
IDR12
r
IDR11
r
IDR10
r
IDR9
r
IDR8
r
IDR7
r
IDR6
r
IDR5
r
IDR4
r
IDR3
r
IDR2
r
IDR1
r
IDR0
r
Toggle Fields.

IDR0

Bit 0: Port input data.

Allowed values:
1: High: Input is logic high
0: Low: Input is logic low

IDR1

Bit 1: Port input data.

Allowed values:
1: High: Input is logic high
0: Low: Input is logic low

IDR2

Bit 2: Port input data.

Allowed values:
1: High: Input is logic high
0: Low: Input is logic low

IDR3

Bit 3: Port input data.

Allowed values:
1: High: Input is logic high
0: Low: Input is logic low

IDR4

Bit 4: Port input data.

Allowed values:
1: High: Input is logic high
0: Low: Input is logic low

IDR5

Bit 5: Port input data.

Allowed values:
1: High: Input is logic high
0: Low: Input is logic low

IDR6

Bit 6: Port input data.

Allowed values:
1: High: Input is logic high
0: Low: Input is logic low

IDR7

Bit 7: Port input data.

Allowed values:
1: High: Input is logic high
0: Low: Input is logic low

IDR8

Bit 8: Port input data.

Allowed values:
1: High: Input is logic high
0: Low: Input is logic low

IDR9

Bit 9: Port input data.

Allowed values:
1: High: Input is logic high
0: Low: Input is logic low

IDR10

Bit 10: Port input data.

Allowed values:
1: High: Input is logic high
0: Low: Input is logic low

IDR11

Bit 11: Port input data.

Allowed values:
1: High: Input is logic high
0: Low: Input is logic low

IDR12

Bit 12: Port input data.

Allowed values:
1: High: Input is logic high
0: Low: Input is logic low

IDR13

Bit 13: Port input data.

Allowed values:
1: High: Input is logic high
0: Low: Input is logic low

IDR14

Bit 14: Port input data.

Allowed values:
1: High: Input is logic high
0: Low: Input is logic low

IDR15

Bit 15: Port input data.

Allowed values:
1: High: Input is logic high
0: Low: Input is logic low

ODR

Port output data register (GPIOn_ODR)

Offset: 0xC, reset: 0x00000000, access: read-write

16/16 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ODR15
rw
ODR14
rw
ODR13
rw
ODR12
rw
ODR11
rw
ODR10
rw
ODR9
rw
ODR8
rw
ODR7
rw
ODR6
rw
ODR5
rw
ODR4
rw
ODR3
rw
ODR2
rw
ODR1
rw
ODR0
rw
Toggle Fields.

ODR0

Bit 0: Port output data.

Allowed values:
1: High: Set output to logic high
0: Low: Set output to logic low

ODR1

Bit 1: Port output data.

Allowed values:
1: High: Set output to logic high
0: Low: Set output to logic low

ODR2

Bit 2: Port output data.

Allowed values:
1: High: Set output to logic high
0: Low: Set output to logic low

ODR3

Bit 3: Port output data.

Allowed values:
1: High: Set output to logic high
0: Low: Set output to logic low

ODR4

Bit 4: Port output data.

Allowed values:
1: High: Set output to logic high
0: Low: Set output to logic low

ODR5

Bit 5: Port output data.

Allowed values:
1: High: Set output to logic high
0: Low: Set output to logic low

ODR6

Bit 6: Port output data.

Allowed values:
1: High: Set output to logic high
0: Low: Set output to logic low

ODR7

Bit 7: Port output data.

Allowed values:
1: High: Set output to logic high
0: Low: Set output to logic low

ODR8

Bit 8: Port output data.

Allowed values:
1: High: Set output to logic high
0: Low: Set output to logic low

ODR9

Bit 9: Port output data.

Allowed values:
1: High: Set output to logic high
0: Low: Set output to logic low

ODR10

Bit 10: Port output data.

Allowed values:
1: High: Set output to logic high
0: Low: Set output to logic low

ODR11

Bit 11: Port output data.

Allowed values:
1: High: Set output to logic high
0: Low: Set output to logic low

ODR12

Bit 12: Port output data.

Allowed values:
1: High: Set output to logic high
0: Low: Set output to logic low

ODR13

Bit 13: Port output data.

Allowed values:
1: High: Set output to logic high
0: Low: Set output to logic low

ODR14

Bit 14: Port output data.

Allowed values:
1: High: Set output to logic high
0: Low: Set output to logic low

ODR15

Bit 15: Port output data.

Allowed values:
1: High: Set output to logic high
0: Low: Set output to logic low

BSRR

Port bit set/reset register (GPIOn_BSRR)

Offset: 0x10, reset: 0x00000000, access: write-only

32/32 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
BR15
w
BR14
w
BR13
w
BR12
w
BR11
w
BR10
w
BR9
w
BR8
w
BR7
w
BR6
w
BR5
w
BR4
w
BR3
w
BR2
w
BR1
w
BR0
w
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
BS15
w
BS14
w
BS13
w
BS12
w
BS11
w
BS10
w
BS9
w
BS8
w
BS7
w
BS6
w
BS5
w
BS4
w
BS3
w
BS2
w
BS1
w
BS0
w
Toggle Fields.

BS0

Bit 0: Set bit 0.

Allowed values:
1: Set: Sets the corresponding ODRx bit

BS1

Bit 1: Set bit 1.

Allowed values:
1: Set: Sets the corresponding ODRx bit

BS2

Bit 2: Set bit 1.

Allowed values:
1: Set: Sets the corresponding ODRx bit

BS3

Bit 3: Set bit 3.

Allowed values:
1: Set: Sets the corresponding ODRx bit

BS4

Bit 4: Set bit 4.

Allowed values:
1: Set: Sets the corresponding ODRx bit

BS5

Bit 5: Set bit 5.

Allowed values:
1: Set: Sets the corresponding ODRx bit

BS6

Bit 6: Set bit 6.

Allowed values:
1: Set: Sets the corresponding ODRx bit

BS7

Bit 7: Set bit 7.

Allowed values:
1: Set: Sets the corresponding ODRx bit

BS8

Bit 8: Set bit 8.

Allowed values:
1: Set: Sets the corresponding ODRx bit

BS9

Bit 9: Set bit 9.

Allowed values:
1: Set: Sets the corresponding ODRx bit

BS10

Bit 10: Set bit 10.

Allowed values:
1: Set: Sets the corresponding ODRx bit

BS11

Bit 11: Set bit 11.

Allowed values:
1: Set: Sets the corresponding ODRx bit

BS12

Bit 12: Set bit 12.

Allowed values:
1: Set: Sets the corresponding ODRx bit

BS13

Bit 13: Set bit 13.

Allowed values:
1: Set: Sets the corresponding ODRx bit

BS14

Bit 14: Set bit 14.

Allowed values:
1: Set: Sets the corresponding ODRx bit

BS15

Bit 15: Set bit 15.

Allowed values:
1: Set: Sets the corresponding ODRx bit

BR0

Bit 16: Reset bit 0.

Allowed values:
1: Reset: Resets the corresponding ODRx bit

BR1

Bit 17: Reset bit 1.

Allowed values:
1: Reset: Resets the corresponding ODRx bit

BR2

Bit 18: Reset bit 2.

Allowed values:
1: Reset: Resets the corresponding ODRx bit

BR3

Bit 19: Reset bit 3.

Allowed values:
1: Reset: Resets the corresponding ODRx bit

BR4

Bit 20: Reset bit 4.

Allowed values:
1: Reset: Resets the corresponding ODRx bit

BR5

Bit 21: Reset bit 5.

Allowed values:
1: Reset: Resets the corresponding ODRx bit

BR6

Bit 22: Reset bit 6.

Allowed values:
1: Reset: Resets the corresponding ODRx bit

BR7

Bit 23: Reset bit 7.

Allowed values:
1: Reset: Resets the corresponding ODRx bit

BR8

Bit 24: Reset bit 8.

Allowed values:
1: Reset: Resets the corresponding ODRx bit

BR9

Bit 25: Reset bit 9.

Allowed values:
1: Reset: Resets the corresponding ODRx bit

BR10

Bit 26: Reset bit 10.

Allowed values:
1: Reset: Resets the corresponding ODRx bit

BR11

Bit 27: Reset bit 11.

Allowed values:
1: Reset: Resets the corresponding ODRx bit

BR12

Bit 28: Reset bit 12.

Allowed values:
1: Reset: Resets the corresponding ODRx bit

BR13

Bit 29: Reset bit 13.

Allowed values:
1: Reset: Resets the corresponding ODRx bit

BR14

Bit 30: Reset bit 14.

Allowed values:
1: Reset: Resets the corresponding ODRx bit

BR15

Bit 31: Reset bit 15.

Allowed values:
1: Reset: Resets the corresponding ODRx bit

BRR

Port bit reset register (GPIOn_BRR)

Offset: 0x14, reset: 0x00000000, access: write-only

16/16 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
BR15
w
BR14
w
BR13
w
BR12
w
BR11
w
BR10
w
BR9
w
BR8
w
BR7
w
BR6
w
BR5
w
BR4
w
BR3
w
BR2
w
BR1
w
BR0
w
Toggle Fields.

BR0

Bit 0: Reset bit 0.

Allowed values:
0: NoAction: No action on the corresponding ODx bit
1: Reset: Reset the ODx bit

BR1

Bit 1: Reset bit 1.

Allowed values:
0: NoAction: No action on the corresponding ODx bit
1: Reset: Reset the ODx bit

BR2

Bit 2: Reset bit 1.

Allowed values:
0: NoAction: No action on the corresponding ODx bit
1: Reset: Reset the ODx bit

BR3

Bit 3: Reset bit 3.

Allowed values:
0: NoAction: No action on the corresponding ODx bit
1: Reset: Reset the ODx bit

BR4

Bit 4: Reset bit 4.

Allowed values:
0: NoAction: No action on the corresponding ODx bit
1: Reset: Reset the ODx bit

BR5

Bit 5: Reset bit 5.

Allowed values:
0: NoAction: No action on the corresponding ODx bit
1: Reset: Reset the ODx bit

BR6

Bit 6: Reset bit 6.

Allowed values:
0: NoAction: No action on the corresponding ODx bit
1: Reset: Reset the ODx bit

BR7

Bit 7: Reset bit 7.

Allowed values:
0: NoAction: No action on the corresponding ODx bit
1: Reset: Reset the ODx bit

BR8

Bit 8: Reset bit 8.

Allowed values:
0: NoAction: No action on the corresponding ODx bit
1: Reset: Reset the ODx bit

BR9

Bit 9: Reset bit 9.

Allowed values:
0: NoAction: No action on the corresponding ODx bit
1: Reset: Reset the ODx bit

BR10

Bit 10: Reset bit 10.

Allowed values:
0: NoAction: No action on the corresponding ODx bit
1: Reset: Reset the ODx bit

BR11

Bit 11: Reset bit 11.

Allowed values:
0: NoAction: No action on the corresponding ODx bit
1: Reset: Reset the ODx bit

BR12

Bit 12: Reset bit 12.

Allowed values:
0: NoAction: No action on the corresponding ODx bit
1: Reset: Reset the ODx bit

BR13

Bit 13: Reset bit 13.

Allowed values:
0: NoAction: No action on the corresponding ODx bit
1: Reset: Reset the ODx bit

BR14

Bit 14: Reset bit 14.

Allowed values:
0: NoAction: No action on the corresponding ODx bit
1: Reset: Reset the ODx bit

BR15

Bit 15: Reset bit 15.

Allowed values:
0: NoAction: No action on the corresponding ODx bit
1: Reset: Reset the ODx bit

LCKR

Port configuration lock register

Offset: 0x18, reset: 0x00000000, access: read-write

17/17 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LCKK
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LCK15
rw
LCK14
rw
LCK13
rw
LCK12
rw
LCK11
rw
LCK10
rw
LCK9
rw
LCK8
rw
LCK7
rw
LCK6
rw
LCK5
rw
LCK4
rw
LCK3
rw
LCK2
rw
LCK1
rw
LCK0
rw
Toggle Fields.

LCK0

Bit 0: Port A Lock bit 0.

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCK1

Bit 1: Port A Lock bit 1.

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCK2

Bit 2: Port A Lock bit 2.

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCK3

Bit 3: Port A Lock bit 3.

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCK4

Bit 4: Port A Lock bit 4.

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCK5

Bit 5: Port A Lock bit 5.

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCK6

Bit 6: Port A Lock bit 6.

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCK7

Bit 7: Port A Lock bit 7.

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCK8

Bit 8: Port A Lock bit 8.

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCK9

Bit 9: Port A Lock bit 9.

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCK10

Bit 10: Port A Lock bit 10.

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCK11

Bit 11: Port A Lock bit 11.

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCK12

Bit 12: Port A Lock bit 12.

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCK13

Bit 13: Port A Lock bit 13.

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCK14

Bit 14: Port A Lock bit 14.

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCK15

Bit 15: Port A Lock bit 15.

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCKK

Bit 16: Lock key.

Allowed values:
0: NotActive: Port configuration lock key not active
1: Active: Port configuration lock key active

GPIOG

0x40012000: General purpose I/O

129/129 fields covered. Toggle Registers.

CRL

Port configuration register low (GPIOn_CRL)

Offset: 0x0, reset: 0x44444444, access: read-write

16/16 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CNF7
rw
MODE7
rw
CNF6
rw
MODE6
rw
CNF5
rw
MODE5
rw
CNF4
rw
MODE4
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CNF3
rw
MODE3
rw
CNF2
rw
MODE2
rw
CNF1
rw
MODE1
rw
CNF0
rw
MODE0
rw
Toggle Fields.

MODE0

Bits 0-1: Port n.0 mode bits.

Allowed values:
0: Input: Input mode (reset state)
1: Output: Output mode 10 MHz
2: Output2: Output mode 2 MHz
3: Output50: Output mode 50 MHz

CNF0

Bits 2-3: Port n.0 configuration bits.

Allowed values:
0: PushPull: Analog mode / Push-Pull mode
1: OpenDrain: Floating input (reset state) / Open Drain-Mode
2: AltPushPull: Input with pull-up/pull-down / Alternate Function Push-Pull Mode
3: AltOpenDrain: Alternate Function Open-Drain Mode

MODE1

Bits 4-5: Port n.1 mode bits.

Allowed values:
0: Input: Input mode (reset state)
1: Output: Output mode 10 MHz
2: Output2: Output mode 2 MHz
3: Output50: Output mode 50 MHz

CNF1

Bits 6-7: Port n.1 configuration bits.

Allowed values:
0: PushPull: Analog mode / Push-Pull mode
1: OpenDrain: Floating input (reset state) / Open Drain-Mode
2: AltPushPull: Input with pull-up/pull-down / Alternate Function Push-Pull Mode
3: AltOpenDrain: Alternate Function Open-Drain Mode

MODE2

Bits 8-9: Port n.2 mode bits.

Allowed values:
0: Input: Input mode (reset state)
1: Output: Output mode 10 MHz
2: Output2: Output mode 2 MHz
3: Output50: Output mode 50 MHz

CNF2

Bits 10-11: Port n.2 configuration bits.

Allowed values:
0: PushPull: Analog mode / Push-Pull mode
1: OpenDrain: Floating input (reset state) / Open Drain-Mode
2: AltPushPull: Input with pull-up/pull-down / Alternate Function Push-Pull Mode
3: AltOpenDrain: Alternate Function Open-Drain Mode

MODE3

Bits 12-13: Port n.3 mode bits.

Allowed values:
0: Input: Input mode (reset state)
1: Output: Output mode 10 MHz
2: Output2: Output mode 2 MHz
3: Output50: Output mode 50 MHz

CNF3

Bits 14-15: Port n.3 configuration bits.

Allowed values:
0: PushPull: Analog mode / Push-Pull mode
1: OpenDrain: Floating input (reset state) / Open Drain-Mode
2: AltPushPull: Input with pull-up/pull-down / Alternate Function Push-Pull Mode
3: AltOpenDrain: Alternate Function Open-Drain Mode

MODE4

Bits 16-17: Port n.4 mode bits.

Allowed values:
0: Input: Input mode (reset state)
1: Output: Output mode 10 MHz
2: Output2: Output mode 2 MHz
3: Output50: Output mode 50 MHz

CNF4

Bits 18-19: Port n.4 configuration bits.

Allowed values:
0: PushPull: Analog mode / Push-Pull mode
1: OpenDrain: Floating input (reset state) / Open Drain-Mode
2: AltPushPull: Input with pull-up/pull-down / Alternate Function Push-Pull Mode
3: AltOpenDrain: Alternate Function Open-Drain Mode

MODE5

Bits 20-21: Port n.5 mode bits.

Allowed values:
0: Input: Input mode (reset state)
1: Output: Output mode 10 MHz
2: Output2: Output mode 2 MHz
3: Output50: Output mode 50 MHz

CNF5

Bits 22-23: Port n.5 configuration bits.

Allowed values:
0: PushPull: Analog mode / Push-Pull mode
1: OpenDrain: Floating input (reset state) / Open Drain-Mode
2: AltPushPull: Input with pull-up/pull-down / Alternate Function Push-Pull Mode
3: AltOpenDrain: Alternate Function Open-Drain Mode

MODE6

Bits 24-25: Port n.6 mode bits.

Allowed values:
0: Input: Input mode (reset state)
1: Output: Output mode 10 MHz
2: Output2: Output mode 2 MHz
3: Output50: Output mode 50 MHz

CNF6

Bits 26-27: Port n.6 configuration bits.

Allowed values:
0: PushPull: Analog mode / Push-Pull mode
1: OpenDrain: Floating input (reset state) / Open Drain-Mode
2: AltPushPull: Input with pull-up/pull-down / Alternate Function Push-Pull Mode
3: AltOpenDrain: Alternate Function Open-Drain Mode

MODE7

Bits 28-29: Port n.7 mode bits.

Allowed values:
0: Input: Input mode (reset state)
1: Output: Output mode 10 MHz
2: Output2: Output mode 2 MHz
3: Output50: Output mode 50 MHz

CNF7

Bits 30-31: Port n.7 configuration bits.

Allowed values:
0: PushPull: Analog mode / Push-Pull mode
1: OpenDrain: Floating input (reset state) / Open Drain-Mode
2: AltPushPull: Input with pull-up/pull-down / Alternate Function Push-Pull Mode
3: AltOpenDrain: Alternate Function Open-Drain Mode

CRH

Port configuration register high (GPIOn_CRL)

Offset: 0x4, reset: 0x44444444, access: read-write

16/16 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CNF15
rw
MODE15
rw
CNF14
rw
MODE14
rw
CNF13
rw
MODE13
rw
CNF12
rw
MODE12
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CNF11
rw
MODE11
rw
CNF10
rw
MODE10
rw
CNF9
rw
MODE9
rw
CNF8
rw
MODE8
rw
Toggle Fields.

MODE8

Bits 0-1: Port n.8 mode bits.

Allowed values:
0: Input: Input mode (reset state)
1: Output: Output mode 10 MHz
2: Output2: Output mode 2 MHz
3: Output50: Output mode 50 MHz

CNF8

Bits 2-3: Port n.8 configuration bits.

Allowed values:
0: PushPull: Analog mode / Push-Pull mode
1: OpenDrain: Floating input (reset state) / Open Drain-Mode
2: AltPushPull: Input with pull-up/pull-down / Alternate Function Push-Pull Mode
3: AltOpenDrain: Alternate Function Open-Drain Mode

MODE9

Bits 4-5: Port n.9 mode bits.

Allowed values:
0: Input: Input mode (reset state)
1: Output: Output mode 10 MHz
2: Output2: Output mode 2 MHz
3: Output50: Output mode 50 MHz

CNF9

Bits 6-7: Port n.9 configuration bits.

Allowed values:
0: PushPull: Analog mode / Push-Pull mode
1: OpenDrain: Floating input (reset state) / Open Drain-Mode
2: AltPushPull: Input with pull-up/pull-down / Alternate Function Push-Pull Mode
3: AltOpenDrain: Alternate Function Open-Drain Mode

MODE10

Bits 8-9: Port n.10 mode bits.

Allowed values:
0: Input: Input mode (reset state)
1: Output: Output mode 10 MHz
2: Output2: Output mode 2 MHz
3: Output50: Output mode 50 MHz

CNF10

Bits 10-11: Port n.10 configuration bits.

Allowed values:
0: PushPull: Analog mode / Push-Pull mode
1: OpenDrain: Floating input (reset state) / Open Drain-Mode
2: AltPushPull: Input with pull-up/pull-down / Alternate Function Push-Pull Mode
3: AltOpenDrain: Alternate Function Open-Drain Mode

MODE11

Bits 12-13: Port n.11 mode bits.

Allowed values:
0: Input: Input mode (reset state)
1: Output: Output mode 10 MHz
2: Output2: Output mode 2 MHz
3: Output50: Output mode 50 MHz

CNF11

Bits 14-15: Port n.11 configuration bits.

Allowed values:
0: PushPull: Analog mode / Push-Pull mode
1: OpenDrain: Floating input (reset state) / Open Drain-Mode
2: AltPushPull: Input with pull-up/pull-down / Alternate Function Push-Pull Mode
3: AltOpenDrain: Alternate Function Open-Drain Mode

MODE12

Bits 16-17: Port n.12 mode bits.

Allowed values:
0: Input: Input mode (reset state)
1: Output: Output mode 10 MHz
2: Output2: Output mode 2 MHz
3: Output50: Output mode 50 MHz

CNF12

Bits 18-19: Port n.12 configuration bits.

Allowed values:
0: PushPull: Analog mode / Push-Pull mode
1: OpenDrain: Floating input (reset state) / Open Drain-Mode
2: AltPushPull: Input with pull-up/pull-down / Alternate Function Push-Pull Mode
3: AltOpenDrain: Alternate Function Open-Drain Mode

MODE13

Bits 20-21: Port n.13 mode bits.

Allowed values:
0: Input: Input mode (reset state)
1: Output: Output mode 10 MHz
2: Output2: Output mode 2 MHz
3: Output50: Output mode 50 MHz

CNF13

Bits 22-23: Port n.13 configuration bits.

Allowed values:
0: PushPull: Analog mode / Push-Pull mode
1: OpenDrain: Floating input (reset state) / Open Drain-Mode
2: AltPushPull: Input with pull-up/pull-down / Alternate Function Push-Pull Mode
3: AltOpenDrain: Alternate Function Open-Drain Mode

MODE14

Bits 24-25: Port n.14 mode bits.

Allowed values:
0: Input: Input mode (reset state)
1: Output: Output mode 10 MHz
2: Output2: Output mode 2 MHz
3: Output50: Output mode 50 MHz

CNF14

Bits 26-27: Port n.14 configuration bits.

Allowed values:
0: PushPull: Analog mode / Push-Pull mode
1: OpenDrain: Floating input (reset state) / Open Drain-Mode
2: AltPushPull: Input with pull-up/pull-down / Alternate Function Push-Pull Mode
3: AltOpenDrain: Alternate Function Open-Drain Mode

MODE15

Bits 28-29: Port n.15 mode bits.

Allowed values:
0: Input: Input mode (reset state)
1: Output: Output mode 10 MHz
2: Output2: Output mode 2 MHz
3: Output50: Output mode 50 MHz

CNF15

Bits 30-31: Port n.15 configuration bits.

Allowed values:
0: PushPull: Analog mode / Push-Pull mode
1: OpenDrain: Floating input (reset state) / Open Drain-Mode
2: AltPushPull: Input with pull-up/pull-down / Alternate Function Push-Pull Mode
3: AltOpenDrain: Alternate Function Open-Drain Mode

IDR

Port input data register (GPIOn_IDR)

Offset: 0x8, reset: 0x00000000, access: read-only

16/16 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
IDR15
r
IDR14
r
IDR13
r
IDR12
r
IDR11
r
IDR10
r
IDR9
r
IDR8
r
IDR7
r
IDR6
r
IDR5
r
IDR4
r
IDR3
r
IDR2
r
IDR1
r
IDR0
r
Toggle Fields.

IDR0

Bit 0: Port input data.

Allowed values:
1: High: Input is logic high
0: Low: Input is logic low

IDR1

Bit 1: Port input data.

Allowed values:
1: High: Input is logic high
0: Low: Input is logic low

IDR2

Bit 2: Port input data.

Allowed values:
1: High: Input is logic high
0: Low: Input is logic low

IDR3

Bit 3: Port input data.

Allowed values:
1: High: Input is logic high
0: Low: Input is logic low

IDR4

Bit 4: Port input data.

Allowed values:
1: High: Input is logic high
0: Low: Input is logic low

IDR5

Bit 5: Port input data.

Allowed values:
1: High: Input is logic high
0: Low: Input is logic low

IDR6

Bit 6: Port input data.

Allowed values:
1: High: Input is logic high
0: Low: Input is logic low

IDR7

Bit 7: Port input data.

Allowed values:
1: High: Input is logic high
0: Low: Input is logic low

IDR8

Bit 8: Port input data.

Allowed values:
1: High: Input is logic high
0: Low: Input is logic low

IDR9

Bit 9: Port input data.

Allowed values:
1: High: Input is logic high
0: Low: Input is logic low

IDR10

Bit 10: Port input data.

Allowed values:
1: High: Input is logic high
0: Low: Input is logic low

IDR11

Bit 11: Port input data.

Allowed values:
1: High: Input is logic high
0: Low: Input is logic low

IDR12

Bit 12: Port input data.

Allowed values:
1: High: Input is logic high
0: Low: Input is logic low

IDR13

Bit 13: Port input data.

Allowed values:
1: High: Input is logic high
0: Low: Input is logic low

IDR14

Bit 14: Port input data.

Allowed values:
1: High: Input is logic high
0: Low: Input is logic low

IDR15

Bit 15: Port input data.

Allowed values:
1: High: Input is logic high
0: Low: Input is logic low

ODR

Port output data register (GPIOn_ODR)

Offset: 0xC, reset: 0x00000000, access: read-write

16/16 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ODR15
rw
ODR14
rw
ODR13
rw
ODR12
rw
ODR11
rw
ODR10
rw
ODR9
rw
ODR8
rw
ODR7
rw
ODR6
rw
ODR5
rw
ODR4
rw
ODR3
rw
ODR2
rw
ODR1
rw
ODR0
rw
Toggle Fields.

ODR0

Bit 0: Port output data.

Allowed values:
1: High: Set output to logic high
0: Low: Set output to logic low

ODR1

Bit 1: Port output data.

Allowed values:
1: High: Set output to logic high
0: Low: Set output to logic low

ODR2

Bit 2: Port output data.

Allowed values:
1: High: Set output to logic high
0: Low: Set output to logic low

ODR3

Bit 3: Port output data.

Allowed values:
1: High: Set output to logic high
0: Low: Set output to logic low

ODR4

Bit 4: Port output data.

Allowed values:
1: High: Set output to logic high
0: Low: Set output to logic low

ODR5

Bit 5: Port output data.

Allowed values:
1: High: Set output to logic high
0: Low: Set output to logic low

ODR6

Bit 6: Port output data.

Allowed values:
1: High: Set output to logic high
0: Low: Set output to logic low

ODR7

Bit 7: Port output data.

Allowed values:
1: High: Set output to logic high
0: Low: Set output to logic low

ODR8

Bit 8: Port output data.

Allowed values:
1: High: Set output to logic high
0: Low: Set output to logic low

ODR9

Bit 9: Port output data.

Allowed values:
1: High: Set output to logic high
0: Low: Set output to logic low

ODR10

Bit 10: Port output data.

Allowed values:
1: High: Set output to logic high
0: Low: Set output to logic low

ODR11

Bit 11: Port output data.

Allowed values:
1: High: Set output to logic high
0: Low: Set output to logic low

ODR12

Bit 12: Port output data.

Allowed values:
1: High: Set output to logic high
0: Low: Set output to logic low

ODR13

Bit 13: Port output data.

Allowed values:
1: High: Set output to logic high
0: Low: Set output to logic low

ODR14

Bit 14: Port output data.

Allowed values:
1: High: Set output to logic high
0: Low: Set output to logic low

ODR15

Bit 15: Port output data.

Allowed values:
1: High: Set output to logic high
0: Low: Set output to logic low

BSRR

Port bit set/reset register (GPIOn_BSRR)

Offset: 0x10, reset: 0x00000000, access: write-only

32/32 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
BR15
w
BR14
w
BR13
w
BR12
w
BR11
w
BR10
w
BR9
w
BR8
w
BR7
w
BR6
w
BR5
w
BR4
w
BR3
w
BR2
w
BR1
w
BR0
w
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
BS15
w
BS14
w
BS13
w
BS12
w
BS11
w
BS10
w
BS9
w
BS8
w
BS7
w
BS6
w
BS5
w
BS4
w
BS3
w
BS2
w
BS1
w
BS0
w
Toggle Fields.

BS0

Bit 0: Set bit 0.

Allowed values:
1: Set: Sets the corresponding ODRx bit

BS1

Bit 1: Set bit 1.

Allowed values:
1: Set: Sets the corresponding ODRx bit

BS2

Bit 2: Set bit 1.

Allowed values:
1: Set: Sets the corresponding ODRx bit

BS3

Bit 3: Set bit 3.

Allowed values:
1: Set: Sets the corresponding ODRx bit

BS4

Bit 4: Set bit 4.

Allowed values:
1: Set: Sets the corresponding ODRx bit

BS5

Bit 5: Set bit 5.

Allowed values:
1: Set: Sets the corresponding ODRx bit

BS6

Bit 6: Set bit 6.

Allowed values:
1: Set: Sets the corresponding ODRx bit

BS7

Bit 7: Set bit 7.

Allowed values:
1: Set: Sets the corresponding ODRx bit

BS8

Bit 8: Set bit 8.

Allowed values:
1: Set: Sets the corresponding ODRx bit

BS9

Bit 9: Set bit 9.

Allowed values:
1: Set: Sets the corresponding ODRx bit

BS10

Bit 10: Set bit 10.

Allowed values:
1: Set: Sets the corresponding ODRx bit

BS11

Bit 11: Set bit 11.

Allowed values:
1: Set: Sets the corresponding ODRx bit

BS12

Bit 12: Set bit 12.

Allowed values:
1: Set: Sets the corresponding ODRx bit

BS13

Bit 13: Set bit 13.

Allowed values:
1: Set: Sets the corresponding ODRx bit

BS14

Bit 14: Set bit 14.

Allowed values:
1: Set: Sets the corresponding ODRx bit

BS15

Bit 15: Set bit 15.

Allowed values:
1: Set: Sets the corresponding ODRx bit

BR0

Bit 16: Reset bit 0.

Allowed values:
1: Reset: Resets the corresponding ODRx bit

BR1

Bit 17: Reset bit 1.

Allowed values:
1: Reset: Resets the corresponding ODRx bit

BR2

Bit 18: Reset bit 2.

Allowed values:
1: Reset: Resets the corresponding ODRx bit

BR3

Bit 19: Reset bit 3.

Allowed values:
1: Reset: Resets the corresponding ODRx bit

BR4

Bit 20: Reset bit 4.

Allowed values:
1: Reset: Resets the corresponding ODRx bit

BR5

Bit 21: Reset bit 5.

Allowed values:
1: Reset: Resets the corresponding ODRx bit

BR6

Bit 22: Reset bit 6.

Allowed values:
1: Reset: Resets the corresponding ODRx bit

BR7

Bit 23: Reset bit 7.

Allowed values:
1: Reset: Resets the corresponding ODRx bit

BR8

Bit 24: Reset bit 8.

Allowed values:
1: Reset: Resets the corresponding ODRx bit

BR9

Bit 25: Reset bit 9.

Allowed values:
1: Reset: Resets the corresponding ODRx bit

BR10

Bit 26: Reset bit 10.

Allowed values:
1: Reset: Resets the corresponding ODRx bit

BR11

Bit 27: Reset bit 11.

Allowed values:
1: Reset: Resets the corresponding ODRx bit

BR12

Bit 28: Reset bit 12.

Allowed values:
1: Reset: Resets the corresponding ODRx bit

BR13

Bit 29: Reset bit 13.

Allowed values:
1: Reset: Resets the corresponding ODRx bit

BR14

Bit 30: Reset bit 14.

Allowed values:
1: Reset: Resets the corresponding ODRx bit

BR15

Bit 31: Reset bit 15.

Allowed values:
1: Reset: Resets the corresponding ODRx bit

BRR

Port bit reset register (GPIOn_BRR)

Offset: 0x14, reset: 0x00000000, access: write-only

16/16 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
BR15
w
BR14
w
BR13
w
BR12
w
BR11
w
BR10
w
BR9
w
BR8
w
BR7
w
BR6
w
BR5
w
BR4
w
BR3
w
BR2
w
BR1
w
BR0
w
Toggle Fields.

BR0

Bit 0: Reset bit 0.

Allowed values:
0: NoAction: No action on the corresponding ODx bit
1: Reset: Reset the ODx bit

BR1

Bit 1: Reset bit 1.

Allowed values:
0: NoAction: No action on the corresponding ODx bit
1: Reset: Reset the ODx bit

BR2

Bit 2: Reset bit 1.

Allowed values:
0: NoAction: No action on the corresponding ODx bit
1: Reset: Reset the ODx bit

BR3

Bit 3: Reset bit 3.

Allowed values:
0: NoAction: No action on the corresponding ODx bit
1: Reset: Reset the ODx bit

BR4

Bit 4: Reset bit 4.

Allowed values:
0: NoAction: No action on the corresponding ODx bit
1: Reset: Reset the ODx bit

BR5

Bit 5: Reset bit 5.

Allowed values:
0: NoAction: No action on the corresponding ODx bit
1: Reset: Reset the ODx bit

BR6

Bit 6: Reset bit 6.

Allowed values:
0: NoAction: No action on the corresponding ODx bit
1: Reset: Reset the ODx bit

BR7

Bit 7: Reset bit 7.

Allowed values:
0: NoAction: No action on the corresponding ODx bit
1: Reset: Reset the ODx bit

BR8

Bit 8: Reset bit 8.

Allowed values:
0: NoAction: No action on the corresponding ODx bit
1: Reset: Reset the ODx bit

BR9

Bit 9: Reset bit 9.

Allowed values:
0: NoAction: No action on the corresponding ODx bit
1: Reset: Reset the ODx bit

BR10

Bit 10: Reset bit 10.

Allowed values:
0: NoAction: No action on the corresponding ODx bit
1: Reset: Reset the ODx bit

BR11

Bit 11: Reset bit 11.

Allowed values:
0: NoAction: No action on the corresponding ODx bit
1: Reset: Reset the ODx bit

BR12

Bit 12: Reset bit 12.

Allowed values:
0: NoAction: No action on the corresponding ODx bit
1: Reset: Reset the ODx bit

BR13

Bit 13: Reset bit 13.

Allowed values:
0: NoAction: No action on the corresponding ODx bit
1: Reset: Reset the ODx bit

BR14

Bit 14: Reset bit 14.

Allowed values:
0: NoAction: No action on the corresponding ODx bit
1: Reset: Reset the ODx bit

BR15

Bit 15: Reset bit 15.

Allowed values:
0: NoAction: No action on the corresponding ODx bit
1: Reset: Reset the ODx bit

LCKR

Port configuration lock register

Offset: 0x18, reset: 0x00000000, access: read-write

17/17 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LCKK
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LCK15
rw
LCK14
rw
LCK13
rw
LCK12
rw
LCK11
rw
LCK10
rw
LCK9
rw
LCK8
rw
LCK7
rw
LCK6
rw
LCK5
rw
LCK4
rw
LCK3
rw
LCK2
rw
LCK1
rw
LCK0
rw
Toggle Fields.

LCK0

Bit 0: Port A Lock bit 0.

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCK1

Bit 1: Port A Lock bit 1.

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCK2

Bit 2: Port A Lock bit 2.

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCK3

Bit 3: Port A Lock bit 3.

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCK4

Bit 4: Port A Lock bit 4.

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCK5

Bit 5: Port A Lock bit 5.

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCK6

Bit 6: Port A Lock bit 6.

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCK7

Bit 7: Port A Lock bit 7.

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCK8

Bit 8: Port A Lock bit 8.

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCK9

Bit 9: Port A Lock bit 9.

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCK10

Bit 10: Port A Lock bit 10.

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCK11

Bit 11: Port A Lock bit 11.

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCK12

Bit 12: Port A Lock bit 12.

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCK13

Bit 13: Port A Lock bit 13.

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCK14

Bit 14: Port A Lock bit 14.

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCK15

Bit 15: Port A Lock bit 15.

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCKK

Bit 16: Lock key.

Allowed values:
0: NotActive: Port configuration lock key not active
1: Active: Port configuration lock key active

I2C1

0x40005400: Inter integrated circuit

51/51 fields covered. Toggle Registers.

CR1

Control register 1

Offset: 0x0, reset: 0x0000, access: read-write

14/14 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SWRST
rw
ALERT
rw
PEC
rw
POS
rw
ACK
rw
STOP
rw
START
rw
NOSTRETCH
rw
ENGC
rw
ENPEC
rw
ENARP
rw
SMBTYPE
rw
SMBUS
rw
PE
rw
Toggle Fields.

PE

Bit 0: Peripheral enable.

Allowed values:
0: Disabled: Peripheral disabled
1: Enabled: Peripheral enabled

SMBUS

Bit 1: SMBus mode.

Allowed values:
0: I2C: I2C Mode
1: SMBus: SMBus

SMBTYPE

Bit 3: SMBus type.

Allowed values:
0: Device: SMBus Device
1: Host: SMBus Host

ENARP

Bit 4: ARP enable.

Allowed values:
0: Disabled: ARP disabled
1: Enabled: ARP enabled

ENPEC

Bit 5: PEC enable.

Allowed values:
0: Disabled: PEC calculation disabled
1: Enabled: PEC calculation enabled

ENGC

Bit 6: General call enable.

Allowed values:
0: Disabled: General call disabled
1: Enabled: General call enabled

NOSTRETCH

Bit 7: Clock stretching disable (Slave mode).

Allowed values:
0: Enabled: Clock stretching enabled
1: Disabled: Clock stretching disabled

START

Bit 8: Start generation.

Allowed values:
0: NoStart: No Start generation
1: Start: In master mode: repeated start generation, in slave mode: start generation when bus is free

STOP

Bit 9: Stop generation.

Allowed values:
0: NoStop: No Stop generation
1: Stop: In master mode: stop generation after current byte/start, in slave mode: release SCL and SDA after current byte

ACK

Bit 10: Acknowledge enable.

Allowed values:
0: NAK: No acknowledge returned
1: ACK: Acknowledge returned after a byte is received

POS

Bit 11: Acknowledge/PEC Position (for data reception).

Allowed values:
0: Current: ACK bit controls the (N)ACK of the current byte being received
1: Next: ACK bit controls the (N)ACK of the next byte to be received

PEC

Bit 12: Packet error checking.

Allowed values:
0: Disabled: No PEC transfer
1: Enabled: PEC transfer

ALERT

Bit 13: SMBus alert.

Allowed values:
0: Release: SMBA pin released high
1: Drive: SMBA pin driven low

SWRST

Bit 15: Software reset.

Allowed values:
0: NotReset: I2C peripheral not under reset
1: Reset: I2C peripheral under reset

CR2

Control register 2

Offset: 0x4, reset: 0x0000, access: read-write

6/6 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LAST
rw
DMAEN
rw
ITBUFEN
rw
ITEVTEN
rw
ITERREN
rw
FREQ
rw
Toggle Fields.

FREQ

Bits 0-5: Peripheral clock frequency.

Allowed values: 2-50

ITERREN

Bit 8: Error interrupt enable.

Allowed values:
0: Disabled: Error interrupt disabled
1: Enabled: Error interrupt enabled

ITEVTEN

Bit 9: Event interrupt enable.

Allowed values:
0: Disabled: Event interrupt disabled
1: Enabled: Event interrupt enabled

ITBUFEN

Bit 10: Buffer interrupt enable.

Allowed values:
0: Disabled: TxE=1 or RxNE=1 does not generate any interrupt
1: Enabled: TxE=1 or RxNE=1 generates Event interrupt

DMAEN

Bit 11: DMA requests enable.

Allowed values:
0: Disabled: DMA requests disabled
1: Enabled: DMA request enabled when TxE=1 or RxNE=1

LAST

Bit 12: DMA last transfer.

Allowed values:
0: NotLast: Next DMA EOT is not the last transfer
1: Last: Next DMA EOT is the last transfer

OAR1

Own address register 1

Offset: 0x8, reset: 0x0000, access: read-write

2/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ADDMODE
rw
ADD
rw
Toggle Fields.

ADD

Bits 0-9: Interface address.

Allowed values: 0-1023

ADDMODE

Bit 15: Addressing mode (slave mode).

Allowed values:
0: ADD7: 7-bit slave address
1: ADD10: 10-bit slave address

OAR2

Own address register 2

Offset: 0xC, reset: 0x0000, access: read-write

2/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ADD2
rw
ENDUAL
rw
Toggle Fields.

ENDUAL

Bit 0: Dual addressing mode enable.

Allowed values:
0: Single: Single addressing mode
1: Dual: Dual addressing mode

ADD2

Bits 1-7: Interface address.

Allowed values: 0-127

DR

Data register

Offset: 0x10, reset: 0x0000, access: read-write

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DR
rw
Toggle Fields.

DR

Bits 0-7: 8-bit data register.

Allowed values: 0-255

SR1

Status register 1

Offset: 0x14, reset: 0x0000, access: Unspecified

14/14 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SMBALERT
rw
TIMEOUT
rw
PECERR
rw
OVR
rw
AF
rw
ARLO
rw
BERR
rw
TxE
r
RxNE
r
STOPF
r
ADD10
r
BTF
r
ADDR
r
SB
r
Toggle Fields.

SB

Bit 0: Start bit (Master mode).

Allowed values:
0: NoStart: No Start condition
1: Start: Start condition generated

ADDR

Bit 1: Address sent (master mode)/matched (slave mode).

Allowed values:
0: NotMatch: Adress mismatched or not received
1: Match: Received slave address matched with one of the enabled slave addresses

BTF

Bit 2: Byte transfer finished.

Allowed values:
0: NotFinished: Data byte transfer not done
1: Finished: Data byte transfer successful

ADD10

Bit 3: 10-bit header sent (Master mode).

STOPF

Bit 4: Stop detection (slave mode).

Allowed values:
0: NoStop: No Stop condition detected
1: Stop: Stop condition detected

RxNE

Bit 6: Data register not empty (receivers).

Allowed values:
0: Empty: Data register empty
1: NotEmpty: Data register not empty

TxE

Bit 7: Data register empty (transmitters).

Allowed values:
0: NotEmpty: Data register not empty
1: Empty: Data register empty

BERR

Bit 8: Bus error.

Allowed values:
0: NoError: No misplaced Start or Stop condition
1: Error: Misplaced Start or Stop condition

ARLO

Bit 9: Arbitration lost (master mode).

Allowed values:
0: NoLost: No Arbitration Lost detected
1: Lost: Arbitration Lost detected

AF

Bit 10: Acknowledge failure.

Allowed values:
0: NoFailure: No acknowledge failure
1: Failure: Acknowledge failure

OVR

Bit 11: Overrun/Underrun.

Allowed values:
0: NoOverrun: No overrun/underrun occured
1: Overrun: Overrun/underrun occured

PECERR

Bit 12: PEC Error in reception.

Allowed values:
0: NoError: no PEC error: receiver returns ACK after PEC reception (if ACK=1)
1: Error: PEC error: receiver returns NACK after PEC reception (whatever ACK)

TIMEOUT

Bit 14: Timeout or Tlow error.

Allowed values:
0: NoTimeout: No Timeout error
1: Timeout: SCL remained LOW for 25 ms

SMBALERT

Bit 15: SMBus alert.

Allowed values:
0: NoAlert: No SMBALERT occured
1: Alert: SMBALERT occurred

SR2

Status register 2

Offset: 0x18, reset: 0x0000, access: read-only

8/8 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PEC
r
DUALF
r
SMBHOST
r
SMBDEFAULT
r
GENCALL
r
TRA
r
BUSY
r
MSL
r
Toggle Fields.

MSL

Bit 0: Master/slave.

BUSY

Bit 1: Bus busy.

TRA

Bit 2: Transmitter/receiver.

GENCALL

Bit 4: General call address (Slave mode).

SMBDEFAULT

Bit 5: SMBus device default address (Slave mode).

SMBHOST

Bit 6: SMBus host header (Slave mode).

DUALF

Bit 7: Dual flag (Slave mode).

PEC

Bits 8-15: acket error checking register.

CCR

Clock control register

Offset: 0x1C, reset: 0x0000, access: read-write

3/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
F_S
rw
DUTY
rw
CCR
rw
Toggle Fields.

CCR

Bits 0-11: Clock control register in Fast/Standard mode (Master mode).

Allowed values: 1-4095

DUTY

Bit 14: Fast mode duty cycle.

Allowed values:
0: Duty2_1: Duty cycle t_low/t_high = 2/1
1: Duty16_9: Duty cycle t_low/t_high = 16/9

F_S

Bit 15: I2C master mode selection.

Allowed values:
0: Standard: Standard mode I2C
1: Fast: Fast mode I2C

TRISE

TRISE register

Offset: 0x20, reset: 0x0002, access: read-write

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TRISE
rw
Toggle Fields.

TRISE

Bits 0-5: Maximum rise time in Fast/Standard mode (Master mode).

Allowed values: 0-63

I2C2

0x40005800: Inter integrated circuit

51/51 fields covered. Toggle Registers.

CR1

Control register 1

Offset: 0x0, reset: 0x0000, access: read-write

14/14 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SWRST
rw
ALERT
rw
PEC
rw
POS
rw
ACK
rw
STOP
rw
START
rw
NOSTRETCH
rw
ENGC
rw
ENPEC
rw
ENARP
rw
SMBTYPE
rw
SMBUS
rw
PE
rw
Toggle Fields.

PE

Bit 0: Peripheral enable.

Allowed values:
0: Disabled: Peripheral disabled
1: Enabled: Peripheral enabled

SMBUS

Bit 1: SMBus mode.

Allowed values:
0: I2C: I2C Mode
1: SMBus: SMBus

SMBTYPE

Bit 3: SMBus type.

Allowed values:
0: Device: SMBus Device
1: Host: SMBus Host

ENARP

Bit 4: ARP enable.

Allowed values:
0: Disabled: ARP disabled
1: Enabled: ARP enabled

ENPEC

Bit 5: PEC enable.

Allowed values:
0: Disabled: PEC calculation disabled
1: Enabled: PEC calculation enabled

ENGC

Bit 6: General call enable.

Allowed values:
0: Disabled: General call disabled
1: Enabled: General call enabled

NOSTRETCH

Bit 7: Clock stretching disable (Slave mode).

Allowed values:
0: Enabled: Clock stretching enabled
1: Disabled: Clock stretching disabled

START

Bit 8: Start generation.

Allowed values:
0: NoStart: No Start generation
1: Start: In master mode: repeated start generation, in slave mode: start generation when bus is free

STOP

Bit 9: Stop generation.

Allowed values:
0: NoStop: No Stop generation
1: Stop: In master mode: stop generation after current byte/start, in slave mode: release SCL and SDA after current byte

ACK

Bit 10: Acknowledge enable.

Allowed values:
0: NAK: No acknowledge returned
1: ACK: Acknowledge returned after a byte is received

POS

Bit 11: Acknowledge/PEC Position (for data reception).

Allowed values:
0: Current: ACK bit controls the (N)ACK of the current byte being received
1: Next: ACK bit controls the (N)ACK of the next byte to be received

PEC

Bit 12: Packet error checking.

Allowed values:
0: Disabled: No PEC transfer
1: Enabled: PEC transfer

ALERT

Bit 13: SMBus alert.

Allowed values:
0: Release: SMBA pin released high
1: Drive: SMBA pin driven low

SWRST

Bit 15: Software reset.

Allowed values:
0: NotReset: I2C peripheral not under reset
1: Reset: I2C peripheral under reset

CR2

Control register 2

Offset: 0x4, reset: 0x0000, access: read-write

6/6 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LAST
rw
DMAEN
rw
ITBUFEN
rw
ITEVTEN
rw
ITERREN
rw
FREQ
rw
Toggle Fields.

FREQ

Bits 0-5: Peripheral clock frequency.

Allowed values: 2-50

ITERREN

Bit 8: Error interrupt enable.

Allowed values:
0: Disabled: Error interrupt disabled
1: Enabled: Error interrupt enabled

ITEVTEN

Bit 9: Event interrupt enable.

Allowed values:
0: Disabled: Event interrupt disabled
1: Enabled: Event interrupt enabled

ITBUFEN

Bit 10: Buffer interrupt enable.

Allowed values:
0: Disabled: TxE=1 or RxNE=1 does not generate any interrupt
1: Enabled: TxE=1 or RxNE=1 generates Event interrupt

DMAEN

Bit 11: DMA requests enable.

Allowed values:
0: Disabled: DMA requests disabled
1: Enabled: DMA request enabled when TxE=1 or RxNE=1

LAST

Bit 12: DMA last transfer.

Allowed values:
0: NotLast: Next DMA EOT is not the last transfer
1: Last: Next DMA EOT is the last transfer

OAR1

Own address register 1

Offset: 0x8, reset: 0x0000, access: read-write

2/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ADDMODE
rw
ADD
rw
Toggle Fields.

ADD

Bits 0-9: Interface address.

Allowed values: 0-1023

ADDMODE

Bit 15: Addressing mode (slave mode).

Allowed values:
0: ADD7: 7-bit slave address
1: ADD10: 10-bit slave address

OAR2

Own address register 2

Offset: 0xC, reset: 0x0000, access: read-write

2/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ADD2
rw
ENDUAL
rw
Toggle Fields.

ENDUAL

Bit 0: Dual addressing mode enable.

Allowed values:
0: Single: Single addressing mode
1: Dual: Dual addressing mode

ADD2

Bits 1-7: Interface address.

Allowed values: 0-127

DR

Data register

Offset: 0x10, reset: 0x0000, access: read-write

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DR
rw
Toggle Fields.

DR

Bits 0-7: 8-bit data register.

Allowed values: 0-255

SR1

Status register 1

Offset: 0x14, reset: 0x0000, access: Unspecified

14/14 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SMBALERT
rw
TIMEOUT
rw
PECERR
rw
OVR
rw
AF
rw
ARLO
rw
BERR
rw
TxE
r
RxNE
r
STOPF
r
ADD10
r
BTF
r
ADDR
r
SB
r
Toggle Fields.

SB

Bit 0: Start bit (Master mode).

Allowed values:
0: NoStart: No Start condition
1: Start: Start condition generated

ADDR

Bit 1: Address sent (master mode)/matched (slave mode).

Allowed values:
0: NotMatch: Adress mismatched or not received
1: Match: Received slave address matched with one of the enabled slave addresses

BTF

Bit 2: Byte transfer finished.

Allowed values:
0: NotFinished: Data byte transfer not done
1: Finished: Data byte transfer successful

ADD10

Bit 3: 10-bit header sent (Master mode).

STOPF

Bit 4: Stop detection (slave mode).

Allowed values:
0: NoStop: No Stop condition detected
1: Stop: Stop condition detected

RxNE

Bit 6: Data register not empty (receivers).

Allowed values:
0: Empty: Data register empty
1: NotEmpty: Data register not empty

TxE

Bit 7: Data register empty (transmitters).

Allowed values:
0: NotEmpty: Data register not empty
1: Empty: Data register empty

BERR

Bit 8: Bus error.

Allowed values:
0: NoError: No misplaced Start or Stop condition
1: Error: Misplaced Start or Stop condition

ARLO

Bit 9: Arbitration lost (master mode).

Allowed values:
0: NoLost: No Arbitration Lost detected
1: Lost: Arbitration Lost detected

AF

Bit 10: Acknowledge failure.

Allowed values:
0: NoFailure: No acknowledge failure
1: Failure: Acknowledge failure

OVR

Bit 11: Overrun/Underrun.

Allowed values:
0: NoOverrun: No overrun/underrun occured
1: Overrun: Overrun/underrun occured

PECERR

Bit 12: PEC Error in reception.

Allowed values:
0: NoError: no PEC error: receiver returns ACK after PEC reception (if ACK=1)
1: Error: PEC error: receiver returns NACK after PEC reception (whatever ACK)

TIMEOUT

Bit 14: Timeout or Tlow error.

Allowed values:
0: NoTimeout: No Timeout error
1: Timeout: SCL remained LOW for 25 ms

SMBALERT

Bit 15: SMBus alert.

Allowed values:
0: NoAlert: No SMBALERT occured
1: Alert: SMBALERT occurred

SR2

Status register 2

Offset: 0x18, reset: 0x0000, access: read-only

8/8 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PEC
r
DUALF
r
SMBHOST
r
SMBDEFAULT
r
GENCALL
r
TRA
r
BUSY
r
MSL
r
Toggle Fields.

MSL

Bit 0: Master/slave.

BUSY

Bit 1: Bus busy.

TRA

Bit 2: Transmitter/receiver.

GENCALL

Bit 4: General call address (Slave mode).

SMBDEFAULT

Bit 5: SMBus device default address (Slave mode).

SMBHOST

Bit 6: SMBus host header (Slave mode).

DUALF

Bit 7: Dual flag (Slave mode).

PEC

Bits 8-15: acket error checking register.

CCR

Clock control register

Offset: 0x1C, reset: 0x0000, access: read-write

3/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
F_S
rw
DUTY
rw
CCR
rw
Toggle Fields.

CCR

Bits 0-11: Clock control register in Fast/Standard mode (Master mode).

Allowed values: 1-4095

DUTY

Bit 14: Fast mode duty cycle.

Allowed values:
0: Duty2_1: Duty cycle t_low/t_high = 2/1
1: Duty16_9: Duty cycle t_low/t_high = 16/9

F_S

Bit 15: I2C master mode selection.

Allowed values:
0: Standard: Standard mode I2C
1: Fast: Fast mode I2C

TRISE

TRISE register

Offset: 0x20, reset: 0x0002, access: read-write

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TRISE
rw
Toggle Fields.

TRISE

Bits 0-5: Maximum rise time in Fast/Standard mode (Master mode).

Allowed values: 0-63

IWDG

0x40003000: Independent watchdog

5/5 fields covered. Toggle Registers.

KR

Key register (IWDG_KR)

Offset: 0x0, reset: 0x00000000, access: write-only

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
KEY
w
Toggle Fields.

KEY

Bits 0-15: Key value.

Allowed values:
21845: Enable: Enable access to PR, RLR and WINR registers (0x5555)
43690: Reset: Reset the watchdog value (0xAAAA)
52428: Start: Start the watchdog (0xCCCC)

PR

Prescaler register (IWDG_PR)

Offset: 0x4, reset: 0x00000000, access: read-write

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PR
rw
Toggle Fields.

PR

Bits 0-2: Prescaler divider.

Allowed values:
0: DivideBy4: Divider /4
1: DivideBy8: Divider /8
2: DivideBy16: Divider /16
3: DivideBy32: Divider /32
4: DivideBy64: Divider /64
5: DivideBy128: Divider /128
6: DivideBy256: Divider /256
7: DivideBy256bis: Divider /256

RLR

Reload register (IWDG_RLR)

Offset: 0x8, reset: 0x00000FFF, access: read-write

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RL
rw
Toggle Fields.

RL

Bits 0-11: Watchdog counter reload value.

Allowed values: 0-4095

SR

Status register (IWDG_SR)

Offset: 0xC, reset: 0x00000000, access: read-only

2/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RVU
r
PVU
r
Toggle Fields.

PVU

Bit 0: Watchdog prescaler value update.

RVU

Bit 1: Watchdog counter reload value update.

MPU

0xE000ED90: Memory protection unit

6/19 fields covered. Toggle Registers.

MPU_TYPER

MPU type register

Offset: 0x0, reset: 0X00000800, access: read-only

3/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
IREGION
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DREGION
r
SEPARATE
r
Toggle Fields.

SEPARATE

Bit 0: Separate flag.

DREGION

Bits 8-15: Number of MPU data regions.

IREGION

Bits 16-23: Number of MPU instruction regions.

MPU_CTRL

MPU control register

Offset: 0x4, reset: 0X00000000, access: read-only

3/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PRIVDEFENA
r
HFNMIENA
r
ENABLE
r
Toggle Fields.

ENABLE

Bit 0: Enables the MPU.

HFNMIENA

Bit 1: Enables the operation of MPU during hard fault.

PRIVDEFENA

Bit 2: Enable priviliged software access to default memory map.

MPU_RNR

MPU region number register

Offset: 0x8, reset: 0X00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
REGION
rw
Toggle Fields.

REGION

Bits 0-7: MPU region.

MPU_RBAR

MPU region base address register

Offset: 0xC, reset: 0X00000000, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
ADDR
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ADDR
rw
VALID
rw
REGION
rw
Toggle Fields.

REGION

Bits 0-3: MPU region field.

VALID

Bit 4: MPU region number valid.

ADDR

Bits 5-31: Region base address field.

MPU_RASR

MPU region attribute and size register

Offset: 0x10, reset: 0X00000000, access: read-write

0/9 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
XN
rw
AP
rw
TEX
rw
S
rw
C
rw
B
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SRD
rw
SIZE
rw
ENABLE
rw
Toggle Fields.

ENABLE

Bit 0: Region enable bit..

SIZE

Bits 1-5: Size of the MPU protection region.

SRD

Bits 8-15: Subregion disable bits.

B

Bit 16: memory attribute.

C

Bit 17: memory attribute.

S

Bit 18: Shareable memory attribute.

TEX

Bits 19-21: memory attribute.

AP

Bits 24-26: Access permission.

XN

Bit 28: Instruction access disable bit.

NVIC

0xE000E100: Nested Vectored Interrupt Controller

2/70 fields covered. Toggle Registers.

ISER0

Interrupt Set-Enable Register

Offset: 0x0, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
SETENA
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SETENA
rw
Toggle Fields.

SETENA

Bits 0-31: SETENA.

ISER1

Interrupt Set-Enable Register

Offset: 0x4, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
SETENA
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SETENA
rw
Toggle Fields.

SETENA

Bits 0-31: SETENA.

ICER0

Interrupt Clear-Enable Register

Offset: 0x80, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CLRENA
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CLRENA
rw
Toggle Fields.

CLRENA

Bits 0-31: CLRENA.

ICER1

Interrupt Clear-Enable Register

Offset: 0x84, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CLRENA
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CLRENA
rw
Toggle Fields.

CLRENA

Bits 0-31: CLRENA.

ISPR0

Interrupt Set-Pending Register

Offset: 0x100, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
SETPEND
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SETPEND
rw
Toggle Fields.

SETPEND

Bits 0-31: SETPEND.

ISPR1

Interrupt Set-Pending Register

Offset: 0x104, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
SETPEND
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SETPEND
rw
Toggle Fields.

SETPEND

Bits 0-31: SETPEND.

ICPR0

Interrupt Clear-Pending Register

Offset: 0x180, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CLRPEND
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CLRPEND
rw
Toggle Fields.

CLRPEND

Bits 0-31: CLRPEND.

ICPR1

Interrupt Clear-Pending Register

Offset: 0x184, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CLRPEND
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CLRPEND
rw
Toggle Fields.

CLRPEND

Bits 0-31: CLRPEND.

IABR0

Interrupt Active Bit Register

Offset: 0x200, reset: 0x00000000, access: read-only

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
ACTIVE
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ACTIVE
r
Toggle Fields.

ACTIVE

Bits 0-31: ACTIVE.

IABR1

Interrupt Active Bit Register

Offset: 0x204, reset: 0x00000000, access: read-only

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
ACTIVE
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ACTIVE
r
Toggle Fields.

ACTIVE

Bits 0-31: ACTIVE.

IPR0

Interrupt Priority Register

Offset: 0x300, reset: 0x00000000, access: read-write

0/4 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
IPR_N3
rw
IPR_N2
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
IPR_N1
rw
IPR_N0
rw
Toggle Fields.

IPR_N0

Bits 0-7: IPR_N0.

IPR_N1

Bits 8-15: IPR_N1.

IPR_N2

Bits 16-23: IPR_N2.

IPR_N3

Bits 24-31: IPR_N3.

IPR1

Interrupt Priority Register

Offset: 0x304, reset: 0x00000000, access: read-write

0/4 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
IPR_N3
rw
IPR_N2
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
IPR_N1
rw
IPR_N0
rw
Toggle Fields.

IPR_N0

Bits 0-7: IPR_N0.

IPR_N1

Bits 8-15: IPR_N1.

IPR_N2

Bits 16-23: IPR_N2.

IPR_N3

Bits 24-31: IPR_N3.

IPR2

Interrupt Priority Register

Offset: 0x308, reset: 0x00000000, access: read-write

0/4 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
IPR_N3
rw
IPR_N2
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
IPR_N1
rw
IPR_N0
rw
Toggle Fields.

IPR_N0

Bits 0-7: IPR_N0.

IPR_N1

Bits 8-15: IPR_N1.

IPR_N2

Bits 16-23: IPR_N2.

IPR_N3

Bits 24-31: IPR_N3.

IPR3

Interrupt Priority Register

Offset: 0x30C, reset: 0x00000000, access: read-write

0/4 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
IPR_N3
rw
IPR_N2
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
IPR_N1
rw
IPR_N0
rw
Toggle Fields.

IPR_N0

Bits 0-7: IPR_N0.

IPR_N1

Bits 8-15: IPR_N1.

IPR_N2

Bits 16-23: IPR_N2.

IPR_N3

Bits 24-31: IPR_N3.

IPR4

Interrupt Priority Register

Offset: 0x310, reset: 0x00000000, access: read-write

0/4 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
IPR_N3
rw
IPR_N2
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
IPR_N1
rw
IPR_N0
rw
Toggle Fields.

IPR_N0

Bits 0-7: IPR_N0.

IPR_N1

Bits 8-15: IPR_N1.

IPR_N2

Bits 16-23: IPR_N2.

IPR_N3

Bits 24-31: IPR_N3.

IPR5

Interrupt Priority Register

Offset: 0x314, reset: 0x00000000, access: read-write

0/4 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
IPR_N3
rw
IPR_N2
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
IPR_N1
rw
IPR_N0
rw
Toggle Fields.

IPR_N0

Bits 0-7: IPR_N0.

IPR_N1

Bits 8-15: IPR_N1.

IPR_N2

Bits 16-23: IPR_N2.

IPR_N3

Bits 24-31: IPR_N3.

IPR6

Interrupt Priority Register

Offset: 0x318, reset: 0x00000000, access: read-write

0/4 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
IPR_N3
rw
IPR_N2
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
IPR_N1
rw
IPR_N0
rw
Toggle Fields.

IPR_N0

Bits 0-7: IPR_N0.

IPR_N1

Bits 8-15: IPR_N1.

IPR_N2

Bits 16-23: IPR_N2.

IPR_N3

Bits 24-31: IPR_N3.

IPR7

Interrupt Priority Register

Offset: 0x31C, reset: 0x00000000, access: read-write

0/4 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
IPR_N3
rw
IPR_N2
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
IPR_N1
rw
IPR_N0
rw
Toggle Fields.

IPR_N0

Bits 0-7: IPR_N0.

IPR_N1

Bits 8-15: IPR_N1.

IPR_N2

Bits 16-23: IPR_N2.

IPR_N3

Bits 24-31: IPR_N3.

IPR8

Interrupt Priority Register

Offset: 0x320, reset: 0x00000000, access: read-write

0/4 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
IPR_N3
rw
IPR_N2
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
IPR_N1
rw
IPR_N0
rw
Toggle Fields.

IPR_N0

Bits 0-7: IPR_N0.

IPR_N1

Bits 8-15: IPR_N1.

IPR_N2

Bits 16-23: IPR_N2.

IPR_N3

Bits 24-31: IPR_N3.

IPR9

Interrupt Priority Register

Offset: 0x324, reset: 0x00000000, access: read-write

0/4 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
IPR_N3
rw
IPR_N2
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
IPR_N1
rw
IPR_N0
rw
Toggle Fields.

IPR_N0

Bits 0-7: IPR_N0.

IPR_N1

Bits 8-15: IPR_N1.

IPR_N2

Bits 16-23: IPR_N2.

IPR_N3

Bits 24-31: IPR_N3.

IPR10

Interrupt Priority Register

Offset: 0x328, reset: 0x00000000, access: read-write

0/4 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
IPR_N3
rw
IPR_N2
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
IPR_N1
rw
IPR_N0
rw
Toggle Fields.

IPR_N0

Bits 0-7: IPR_N0.

IPR_N1

Bits 8-15: IPR_N1.

IPR_N2

Bits 16-23: IPR_N2.

IPR_N3

Bits 24-31: IPR_N3.

IPR11

Interrupt Priority Register

Offset: 0x32C, reset: 0x00000000, access: read-write

0/4 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
IPR_N3
rw
IPR_N2
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
IPR_N1
rw
IPR_N0
rw
Toggle Fields.

IPR_N0

Bits 0-7: IPR_N0.

IPR_N1

Bits 8-15: IPR_N1.

IPR_N2

Bits 16-23: IPR_N2.

IPR_N3

Bits 24-31: IPR_N3.

IPR12

Interrupt Priority Register

Offset: 0x330, reset: 0x00000000, access: read-write

0/4 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
IPR_N3
rw
IPR_N2
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
IPR_N1
rw
IPR_N0
rw
Toggle Fields.

IPR_N0

Bits 0-7: IPR_N0.

IPR_N1

Bits 8-15: IPR_N1.

IPR_N2

Bits 16-23: IPR_N2.

IPR_N3

Bits 24-31: IPR_N3.

IPR13

Interrupt Priority Register

Offset: 0x334, reset: 0x00000000, access: read-write

0/4 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
IPR_N3
rw
IPR_N2
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
IPR_N1
rw
IPR_N0
rw
Toggle Fields.

IPR_N0

Bits 0-7: IPR_N0.

IPR_N1

Bits 8-15: IPR_N1.

IPR_N2

Bits 16-23: IPR_N2.

IPR_N3

Bits 24-31: IPR_N3.

IPR14

Interrupt Priority Register

Offset: 0x338, reset: 0x00000000, access: read-write

0/4 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
IPR_N3
rw
IPR_N2
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
IPR_N1
rw
IPR_N0
rw
Toggle Fields.

IPR_N0

Bits 0-7: IPR_N0.

IPR_N1

Bits 8-15: IPR_N1.

IPR_N2

Bits 16-23: IPR_N2.

IPR_N3

Bits 24-31: IPR_N3.

NVIC_STIR

0xE000EF00: Nested vectored interrupt controller

0/1 fields covered. Toggle Registers.

STIR

Software trigger interrupt register

Offset: 0x0, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
INTID
rw
Toggle Fields.

INTID

Bits 0-8: Software generated interrupt ID.

OTG_FS_DEVICE

0x50000800: USB on the go full speed

38/204 fields covered. Toggle Registers.

FS_DCFG

OTG_FS device configuration register (OTG_FS_DCFG)

Offset: 0x0, reset: 0x02200000, access: read-write

0/4 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PFIVL
rw
DAD
rw
NZLSOHSK
rw
DSPD
rw
Toggle Fields.

DSPD

Bits 0-1: Device speed.

NZLSOHSK

Bit 2: Non-zero-length status OUT handshake.

DAD

Bits 4-10: Device address.

PFIVL

Bits 11-12: Periodic frame interval.

FS_DCTL

OTG_FS device control register (OTG_FS_DCTL)

Offset: 0x4, reset: 0x00000000, access: Unspecified

2/10 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
POPRGDNE
rw
CGONAK
rw
SGONAK
rw
CGINAK
rw
SGINAK
rw
TCTL
rw
GONSTS
r
GINSTS
r
SDIS
rw
RWUSIG
rw
Toggle Fields.

RWUSIG

Bit 0: Remote wakeup signaling.

SDIS

Bit 1: Soft disconnect.

GINSTS

Bit 2: Global IN NAK status.

GONSTS

Bit 3: Global OUT NAK status.

TCTL

Bits 4-6: Test control.

SGINAK

Bit 7: Set global IN NAK.

CGINAK

Bit 8: Clear global IN NAK.

SGONAK

Bit 9: Set global OUT NAK.

CGONAK

Bit 10: Clear global OUT NAK.

POPRGDNE

Bit 11: Power-on programming done.

FS_DSTS

OTG_FS device status register (OTG_FS_DSTS)

Offset: 0x8, reset: 0x00000010, access: read-only

4/4 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
FNSOF
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FNSOF
r
EERR
r
ENUMSPD
r
SUSPSTS
r
Toggle Fields.

SUSPSTS

Bit 0: Suspend status.

ENUMSPD

Bits 1-2: Enumerated speed.

EERR

Bit 3: Erratic error.

FNSOF

Bits 8-21: Frame number of the received SOF.

FS_DIEPMSK

OTG_FS device IN endpoint common interrupt mask register (OTG_FS_DIEPMSK)

Offset: 0x10, reset: 0x00000000, access: read-write

0/6 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
INEPNEM
rw
INEPNMM
rw
ITTXFEMSK
rw
TOM
rw
EPDM
rw
XFRCM
rw
Toggle Fields.

XFRCM

Bit 0: Transfer completed interrupt mask.

EPDM

Bit 1: Endpoint disabled interrupt mask.

TOM

Bit 3: Timeout condition mask (Non-isochronous endpoints).

ITTXFEMSK

Bit 4: IN token received when TxFIFO empty mask.

INEPNMM

Bit 5: IN token received with EP mismatch mask.

INEPNEM

Bit 6: IN endpoint NAK effective mask.

FS_DOEPMSK

OTG_FS device OUT endpoint common interrupt mask register (OTG_FS_DOEPMSK)

Offset: 0x14, reset: 0x00000000, access: read-write

0/4 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
OTEPDM
rw
STUPM
rw
EPDM
rw
XFRCM
rw
Toggle Fields.

XFRCM

Bit 0: Transfer completed interrupt mask.

EPDM

Bit 1: Endpoint disabled interrupt mask.

STUPM

Bit 3: SETUP phase done mask.

OTEPDM

Bit 4: OUT token received when endpoint disabled mask.

FS_DAINT

OTG_FS device all endpoints interrupt register (OTG_FS_DAINT)

Offset: 0x18, reset: 0x00000000, access: read-only

2/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
OEPINT
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
IEPINT
r
Toggle Fields.

IEPINT

Bits 0-15: IN endpoint interrupt bits.

OEPINT

Bits 16-31: OUT endpoint interrupt bits.

FS_DAINTMSK

OTG_FS all endpoints interrupt mask register (OTG_FS_DAINTMSK)

Offset: 0x1C, reset: 0x00000000, access: read-write

0/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
OEPINT
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
IEPM
rw
Toggle Fields.

IEPM

Bits 0-15: IN EP interrupt mask bits.

OEPINT

Bits 16-31: OUT endpoint interrupt bits.

DVBUSDIS

OTG_FS device VBUS discharge time register

Offset: 0x28, reset: 0x000017D7, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
VBUSDT
rw
Toggle Fields.

VBUSDT

Bits 0-15: Device VBUS discharge time.

DVBUSPULSE

OTG_FS device VBUS pulsing time register

Offset: 0x2C, reset: 0x000005B8, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DVBUSP
rw
Toggle Fields.

DVBUSP

Bits 0-11: Device VBUS pulsing time.

DIEPEMPMSK

OTG_FS device IN endpoint FIFO empty interrupt mask register

Offset: 0x34, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
INEPTXFEM
rw
Toggle Fields.

INEPTXFEM

Bits 0-15: IN EP Tx FIFO empty interrupt mask bits.

FS_DIEPCTL0

OTG_FS device control IN endpoint 0 control register (OTG_FS_DIEPCTL0)

Offset: 0x100, reset: 0x00000000, access: Unspecified

5/10 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
EPENA
r
EPDIS
r
SNAK
w
CNAK
w
TXFNUM
rw
STALL
rw
EPTYP
r
NAKSTS
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
USBAEP
r
MPSIZ
rw
Toggle Fields.

MPSIZ

Bits 0-1: Maximum packet size.

USBAEP

Bit 15: USB active endpoint.

NAKSTS

Bit 17: NAK status.

EPTYP

Bits 18-19: Endpoint type.

STALL

Bit 21: STALL handshake.

TXFNUM

Bits 22-25: TxFIFO number.

CNAK

Bit 26: Clear NAK.

SNAK

Bit 27: Set NAK.

EPDIS

Bit 30: Endpoint disable.

EPENA

Bit 31: Endpoint enable.

DIEPINT0

device endpoint-x interrupt register

Offset: 0x108, reset: 0x00000080, access: Unspecified

1/6 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TXFE
r
INEPNE
rw
ITTXFE
rw
TOC
rw
EPDISD
rw
XFRC
rw
Toggle Fields.

XFRC

Bit 0: XFRC.

EPDISD

Bit 1: EPDISD.

TOC

Bit 3: TOC.

ITTXFE

Bit 4: ITTXFE.

INEPNE

Bit 6: INEPNE.

TXFE

Bit 7: TXFE.

DIEPTSIZ0

device endpoint-0 transfer size register

Offset: 0x110, reset: 0x00000000, access: read-write

0/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
PKTCNT
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
XFRSIZ
rw
Toggle Fields.

XFRSIZ

Bits 0-6: Transfer size.

PKTCNT

Bits 19-20: Packet count.

DTXFSTS0

OTG_FS device IN endpoint transmit FIFO status register

Offset: 0x118, reset: 0x00000000, access: read-only

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
INEPTFSAV
r
Toggle Fields.

INEPTFSAV

Bits 0-15: IN endpoint TxFIFO space available.

DIEPCTL1

OTG device endpoint-1 control register

Offset: 0x120, reset: 0x00000000, access: Unspecified

2/13 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
EPENA
rw
EPDIS
rw
SODDFRM_SD1PID
w
SD0PID_SEVNFRM
w
SNAK
w
CNAK
w
TXFNUM
rw
Stall
rw
EPTYP
rw
NAKSTS
r
EONUM_DPID
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
USBAEP
rw
MPSIZ
rw
Toggle Fields.

MPSIZ

Bits 0-10: MPSIZ.

USBAEP

Bit 15: USBAEP.

EONUM_DPID

Bit 16: EONUM/DPID.

NAKSTS

Bit 17: NAKSTS.

EPTYP

Bits 18-19: EPTYP.

Stall

Bit 21: Stall.

TXFNUM

Bits 22-25: TXFNUM.

CNAK

Bit 26: CNAK.

SNAK

Bit 27: SNAK.

SD0PID_SEVNFRM

Bit 28: SD0PID/SEVNFRM.

SODDFRM_SD1PID

Bit 29: SODDFRM/SD1PID.

EPDIS

Bit 30: EPDIS.

EPENA

Bit 31: EPENA.

DIEPINT1

device endpoint-1 interrupt register

Offset: 0x128, reset: 0x00000080, access: Unspecified

1/6 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TXFE
r
INEPNE
rw
ITTXFE
rw
TOC
rw
EPDISD
rw
XFRC
rw
Toggle Fields.

XFRC

Bit 0: XFRC.

EPDISD

Bit 1: EPDISD.

TOC

Bit 3: TOC.

ITTXFE

Bit 4: ITTXFE.

INEPNE

Bit 6: INEPNE.

TXFE

Bit 7: TXFE.

DIEPTSIZ1

device endpoint-1 transfer size register

Offset: 0x130, reset: 0x00000000, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
MCNT
rw
PKTCNT
rw
XFRSIZ
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
XFRSIZ
rw
Toggle Fields.

XFRSIZ

Bits 0-18: Transfer size.

PKTCNT

Bits 19-28: Packet count.

MCNT

Bits 29-30: Multi count.

DTXFSTS1

OTG_FS device IN endpoint transmit FIFO status register

Offset: 0x138, reset: 0x00000000, access: read-only

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
INEPTFSAV
r
Toggle Fields.

INEPTFSAV

Bits 0-15: IN endpoint TxFIFO space available.

DIEPCTL2

OTG device endpoint-2 control register

Offset: 0x140, reset: 0x00000000, access: Unspecified

2/13 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
EPENA
rw
EPDIS
rw
SODDFRM
w
SD0PID_SEVNFRM
w
SNAK
w
CNAK
w
TXFNUM
rw
Stall
rw
EPTYP
rw
NAKSTS
r
EONUM_DPID
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
USBAEP
rw
MPSIZ
rw
Toggle Fields.

MPSIZ

Bits 0-10: MPSIZ.

USBAEP

Bit 15: USBAEP.

EONUM_DPID

Bit 16: EONUM/DPID.

NAKSTS

Bit 17: NAKSTS.

EPTYP

Bits 18-19: EPTYP.

Stall

Bit 21: Stall.

TXFNUM

Bits 22-25: TXFNUM.

CNAK

Bit 26: CNAK.

SNAK

Bit 27: SNAK.

SD0PID_SEVNFRM

Bit 28: SD0PID/SEVNFRM.

SODDFRM

Bit 29: SODDFRM.

EPDIS

Bit 30: EPDIS.

EPENA

Bit 31: EPENA.

DIEPINT2

device endpoint-2 interrupt register

Offset: 0x148, reset: 0x00000080, access: Unspecified

1/6 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TXFE
r
INEPNE
rw
ITTXFE
rw
TOC
rw
EPDISD
rw
XFRC
rw
Toggle Fields.

XFRC

Bit 0: XFRC.

EPDISD

Bit 1: EPDISD.

TOC

Bit 3: TOC.

ITTXFE

Bit 4: ITTXFE.

INEPNE

Bit 6: INEPNE.

TXFE

Bit 7: TXFE.

DIEPTSIZ2

device endpoint-2 transfer size register

Offset: 0x150, reset: 0x00000000, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
MCNT
rw
PKTCNT
rw
XFRSIZ
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
XFRSIZ
rw
Toggle Fields.

XFRSIZ

Bits 0-18: Transfer size.

PKTCNT

Bits 19-28: Packet count.

MCNT

Bits 29-30: Multi count.

DTXFSTS2

OTG_FS device IN endpoint transmit FIFO status register

Offset: 0x158, reset: 0x00000000, access: read-only

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
INEPTFSAV
r
Toggle Fields.

INEPTFSAV

Bits 0-15: IN endpoint TxFIFO space available.

DIEPCTL3

OTG device endpoint-3 control register

Offset: 0x160, reset: 0x00000000, access: Unspecified

2/13 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
EPENA
rw
EPDIS
rw
SODDFRM
w
SD0PID_SEVNFRM
w
SNAK
w
CNAK
w
TXFNUM
rw
Stall
rw
EPTYP
rw
NAKSTS
r
EONUM_DPID
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
USBAEP
rw
MPSIZ
rw
Toggle Fields.

MPSIZ

Bits 0-10: MPSIZ.

USBAEP

Bit 15: USBAEP.

EONUM_DPID

Bit 16: EONUM/DPID.

NAKSTS

Bit 17: NAKSTS.

EPTYP

Bits 18-19: EPTYP.

Stall

Bit 21: Stall.

TXFNUM

Bits 22-25: TXFNUM.

CNAK

Bit 26: CNAK.

SNAK

Bit 27: SNAK.

SD0PID_SEVNFRM

Bit 28: SD0PID/SEVNFRM.

SODDFRM

Bit 29: SODDFRM.

EPDIS

Bit 30: EPDIS.

EPENA

Bit 31: EPENA.

DIEPINT3

device endpoint-3 interrupt register

Offset: 0x168, reset: 0x00000080, access: Unspecified

1/6 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TXFE
r
INEPNE
rw
ITTXFE
rw
TOC
rw
EPDISD
rw
XFRC
rw
Toggle Fields.

XFRC

Bit 0: XFRC.

EPDISD

Bit 1: EPDISD.

TOC

Bit 3: TOC.

ITTXFE

Bit 4: ITTXFE.

INEPNE

Bit 6: INEPNE.

TXFE

Bit 7: TXFE.

DIEPTSIZ3

device endpoint-3 transfer size register

Offset: 0x170, reset: 0x00000000, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
MCNT
rw
PKTCNT
rw
XFRSIZ
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
XFRSIZ
rw
Toggle Fields.

XFRSIZ

Bits 0-18: Transfer size.

PKTCNT

Bits 19-28: Packet count.

MCNT

Bits 29-30: Multi count.

DTXFSTS3

OTG_FS device IN endpoint transmit FIFO status register

Offset: 0x178, reset: 0x00000000, access: read-only

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
INEPTFSAV
r
Toggle Fields.

INEPTFSAV

Bits 0-15: IN endpoint TxFIFO space available.

DOEPCTL0

device endpoint-0 control register

Offset: 0x300, reset: 0x00008000, access: Unspecified

5/10 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
EPENA
w
EPDIS
r
SNAK
w
CNAK
w
Stall
rw
SNPM
rw
EPTYP
r
NAKSTS
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
USBAEP
r
MPSIZ
r
Toggle Fields.

MPSIZ

Bits 0-1: MPSIZ.

USBAEP

Bit 15: USBAEP.

NAKSTS

Bit 17: NAKSTS.

EPTYP

Bits 18-19: EPTYP.

SNPM

Bit 20: SNPM.

Stall

Bit 21: Stall.

CNAK

Bit 26: CNAK.

SNAK

Bit 27: SNAK.

EPDIS

Bit 30: EPDIS.

EPENA

Bit 31: EPENA.

DOEPINT0

device endpoint-0 interrupt register

Offset: 0x308, reset: 0x00000080, access: read-write

0/5 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
B2BSTUP
rw
OTEPDIS
rw
STUP
rw
EPDISD
rw
XFRC
rw
Toggle Fields.

XFRC

Bit 0: XFRC.

EPDISD

Bit 1: EPDISD.

STUP

Bit 3: STUP.

OTEPDIS

Bit 4: OTEPDIS.

B2BSTUP

Bit 6: B2BSTUP.

DOEPTSIZ0

device OUT endpoint-0 transfer size register

Offset: 0x310, reset: 0x00000000, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
STUPCNT
rw
PKTCNT
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
XFRSIZ
rw
Toggle Fields.

XFRSIZ

Bits 0-6: Transfer size.

PKTCNT

Bit 19: Packet count.

STUPCNT

Bits 29-30: SETUP packet count.

DOEPCTL1

device endpoint-1 control register

Offset: 0x320, reset: 0x00000000, access: Unspecified

2/13 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
EPENA
rw
EPDIS
rw
SODDFRM
w
SD0PID_SEVNFRM
w
SNAK
w
CNAK
w
Stall
rw
SNPM
rw
EPTYP
rw
NAKSTS
r
EONUM_DPID
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
USBAEP
rw
MPSIZ
rw
Toggle Fields.

MPSIZ

Bits 0-10: MPSIZ.

USBAEP

Bit 15: USBAEP.

EONUM_DPID

Bit 16: EONUM/DPID.

NAKSTS

Bit 17: NAKSTS.

EPTYP

Bits 18-19: EPTYP.

SNPM

Bit 20: SNPM.

Stall

Bit 21: Stall.

CNAK

Bit 26: CNAK.

SNAK

Bit 27: SNAK.

SD0PID_SEVNFRM

Bit 28: SD0PID/SEVNFRM.

SODDFRM

Bit 29: SODDFRM.

EPDIS

Bit 30: EPDIS.

EPENA

Bit 31: EPENA.

DOEPINT1

device endpoint-1 interrupt register

Offset: 0x328, reset: 0x00000080, access: read-write

0/5 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
B2BSTUP
rw
OTEPDIS
rw
STUP
rw
EPDISD
rw
XFRC
rw
Toggle Fields.

XFRC

Bit 0: XFRC.

EPDISD

Bit 1: EPDISD.

STUP

Bit 3: STUP.

OTEPDIS

Bit 4: OTEPDIS.

B2BSTUP

Bit 6: B2BSTUP.

DOEPTSIZ1

device OUT endpoint-1 transfer size register

Offset: 0x330, reset: 0x00000000, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
RXDPID_STUPCNT
rw
PKTCNT
rw
XFRSIZ
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
XFRSIZ
rw
Toggle Fields.

XFRSIZ

Bits 0-18: Transfer size.

PKTCNT

Bits 19-28: Packet count.

RXDPID_STUPCNT

Bits 29-30: Received data PID/SETUP packet count.

DOEPCTL2

device endpoint-2 control register

Offset: 0x340, reset: 0x00000000, access: Unspecified

2/13 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
EPENA
rw
EPDIS
rw
SODDFRM
w
SD0PID_SEVNFRM
w
SNAK
w
CNAK
w
Stall
rw
SNPM
rw
EPTYP
rw
NAKSTS
r
EONUM_DPID
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
USBAEP
rw
MPSIZ
rw
Toggle Fields.

MPSIZ

Bits 0-10: MPSIZ.

USBAEP

Bit 15: USBAEP.

EONUM_DPID

Bit 16: EONUM/DPID.

NAKSTS

Bit 17: NAKSTS.

EPTYP

Bits 18-19: EPTYP.

SNPM

Bit 20: SNPM.

Stall

Bit 21: Stall.

CNAK

Bit 26: CNAK.

SNAK

Bit 27: SNAK.

SD0PID_SEVNFRM

Bit 28: SD0PID/SEVNFRM.

SODDFRM

Bit 29: SODDFRM.

EPDIS

Bit 30: EPDIS.

EPENA

Bit 31: EPENA.

DOEPINT2

device endpoint-2 interrupt register

Offset: 0x348, reset: 0x00000080, access: read-write

0/5 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
B2BSTUP
rw
OTEPDIS
rw
STUP
rw
EPDISD
rw
XFRC
rw
Toggle Fields.

XFRC

Bit 0: XFRC.

EPDISD

Bit 1: EPDISD.

STUP

Bit 3: STUP.

OTEPDIS

Bit 4: OTEPDIS.

B2BSTUP

Bit 6: B2BSTUP.

DOEPTSIZ2

device OUT endpoint-2 transfer size register

Offset: 0x350, reset: 0x00000000, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
RXDPID_STUPCNT
rw
PKTCNT
rw
XFRSIZ
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
XFRSIZ
rw
Toggle Fields.

XFRSIZ

Bits 0-18: Transfer size.

PKTCNT

Bits 19-28: Packet count.

RXDPID_STUPCNT

Bits 29-30: Received data PID/SETUP packet count.

DOEPCTL3

device endpoint-3 control register

Offset: 0x360, reset: 0x00000000, access: Unspecified

2/13 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
EPENA
rw
EPDIS
rw
SODDFRM
w
SD0PID_SEVNFRM
w
SNAK
w
CNAK
w
Stall
rw
SNPM
rw
EPTYP
rw
NAKSTS
r
EONUM_DPID
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
USBAEP
rw
MPSIZ
rw
Toggle Fields.

MPSIZ

Bits 0-10: MPSIZ.

USBAEP

Bit 15: USBAEP.

EONUM_DPID

Bit 16: EONUM/DPID.

NAKSTS

Bit 17: NAKSTS.

EPTYP

Bits 18-19: EPTYP.

SNPM

Bit 20: SNPM.

Stall

Bit 21: Stall.

CNAK

Bit 26: CNAK.

SNAK

Bit 27: SNAK.

SD0PID_SEVNFRM

Bit 28: SD0PID/SEVNFRM.

SODDFRM

Bit 29: SODDFRM.

EPDIS

Bit 30: EPDIS.

EPENA

Bit 31: EPENA.

DOEPINT3

device endpoint-3 interrupt register

Offset: 0x368, reset: 0x00000080, access: read-write

0/5 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
B2BSTUP
rw
OTEPDIS
rw
STUP
rw
EPDISD
rw
XFRC
rw
Toggle Fields.

XFRC

Bit 0: XFRC.

EPDISD

Bit 1: EPDISD.

STUP

Bit 3: STUP.

OTEPDIS

Bit 4: OTEPDIS.

B2BSTUP

Bit 6: B2BSTUP.

DOEPTSIZ3

device OUT endpoint-3 transfer size register

Offset: 0x370, reset: 0x00000000, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
RXDPID_STUPCNT
rw
PKTCNT
rw
XFRSIZ
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
XFRSIZ
rw
Toggle Fields.

XFRSIZ

Bits 0-18: Transfer size.

PKTCNT

Bits 19-28: Packet count.

RXDPID_STUPCNT

Bits 29-30: Received data PID/SETUP packet count.

OTG_FS_GLOBAL

0x50000000: USB on the go full speed

32/115 fields covered. Toggle Registers.

FS_GOTGCTL

OTG_FS control and status register (OTG_FS_GOTGCTL)

Offset: 0x0, reset: 0x00000800, access: Unspecified

6/10 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
BSVLD
r
ASVLD
r
DBCT
r
CIDSTS
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DHNPEN
rw
HSHNPEN
rw
HNPRQ
rw
HNGSCS
r
SRQ
rw
SRQSCS
r
Toggle Fields.

SRQSCS

Bit 0: Session request success.

SRQ

Bit 1: Session request.

HNGSCS

Bit 8: Host negotiation success.

HNPRQ

Bit 9: HNP request.

HSHNPEN

Bit 10: Host set HNP enable.

DHNPEN

Bit 11: Device HNP enabled.

CIDSTS

Bit 16: Connector ID status.

DBCT

Bit 17: Long/short debounce time.

ASVLD

Bit 18: A-session valid.

BSVLD

Bit 19: B-session valid.

FS_GOTGINT

OTG_FS interrupt register (OTG_FS_GOTGINT)

Offset: 0x4, reset: 0x00000000, access: read-write

0/6 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DBCDNE
rw
ADTOCHG
rw
HNGDET
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
HNSSCHG
rw
SRSSCHG
rw
SEDET
rw
Toggle Fields.

SEDET

Bit 2: Session end detected.

SRSSCHG

Bit 8: Session request success status change.

HNSSCHG

Bit 9: Host negotiation success status change.

HNGDET

Bit 17: Host negotiation detected.

ADTOCHG

Bit 18: A-device timeout change.

DBCDNE

Bit 19: Debounce done.

FS_GAHBCFG

OTG_FS AHB configuration register (OTG_FS_GAHBCFG)

Offset: 0x8, reset: 0x00000000, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PTXFELVL
rw
TXFELVL
rw
GINT
rw
Toggle Fields.

GINT

Bit 0: Global interrupt mask.

TXFELVL

Bit 7: TxFIFO empty level.

PTXFELVL

Bit 8: Periodic TxFIFO empty level.

FS_GUSBCFG

OTG_FS USB configuration register (OTG_FS_GUSBCFG)

Offset: 0xC, reset: 0x00000A00, access: Unspecified

0/8 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CTXPKT
rw
FDMOD
rw
FHMOD
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TRDT
rw
HNPCAP
rw
SRPCAP
rw
PHYSEL
w
TOCAL
rw
Toggle Fields.

TOCAL

Bits 0-2: FS timeout calibration.

PHYSEL

Bit 6: Full Speed serial transceiver select.

SRPCAP

Bit 8: SRP-capable.

HNPCAP

Bit 9: HNP-capable.

TRDT

Bits 10-13: USB turnaround time.

FHMOD

Bit 29: Force host mode.

FDMOD

Bit 30: Force device mode.

CTXPKT

Bit 31: Corrupt Tx packet.

FS_GRSTCTL

OTG_FS reset register (OTG_FS_GRSTCTL)

Offset: 0x10, reset: 0x20000000, access: Unspecified

1/7 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
AHBIDL
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TXFNUM
rw
TXFFLSH
rw
RXFFLSH
rw
FCRST
rw
HSRST
rw
CSRST
rw
Toggle Fields.

CSRST

Bit 0: Core soft reset.

HSRST

Bit 1: HCLK soft reset.

FCRST

Bit 2: Host frame counter reset.

RXFFLSH

Bit 4: RxFIFO flush.

TXFFLSH

Bit 5: TxFIFO flush.

TXFNUM

Bits 6-10: TxFIFO number.

AHBIDL

Bit 31: AHB master idle.

FS_GINTSTS

OTG_FS core interrupt register (OTG_FS_GINTSTS)

Offset: 0x14, reset: 0x04000020, access: Unspecified

11/25 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
WKUPINT
rw
SRQINT
rw
DISCINT
rw
CIDSCHG
rw
PTXFE
r
HCINT
r
HPRTINT
r
IPXFR_INCOMPISOOUT
rw
IISOIXFR
rw
OEPINT
r
IEPINT
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
EOPF
rw
ISOODRP
rw
ENUMDNE
rw
USBRST
rw
USBSUSP
rw
ESUSP
rw
GOUTNAKEFF
r
GINAKEFF
r
NPTXFE
r
RXFLVL
r
SOF
rw
OTGINT
r
MMIS
rw
CMOD
r
Toggle Fields.

CMOD

Bit 0: Current mode of operation.

MMIS

Bit 1: Mode mismatch interrupt.

OTGINT

Bit 2: OTG interrupt.

SOF

Bit 3: Start of frame.

RXFLVL

Bit 4: RxFIFO non-empty.

NPTXFE

Bit 5: Non-periodic TxFIFO empty.

GINAKEFF

Bit 6: Global IN non-periodic NAK effective.

GOUTNAKEFF

Bit 7: Global OUT NAK effective.

ESUSP

Bit 10: Early suspend.

USBSUSP

Bit 11: USB suspend.

USBRST

Bit 12: USB reset.

ENUMDNE

Bit 13: Enumeration done.

ISOODRP

Bit 14: Isochronous OUT packet dropped interrupt.

EOPF

Bit 15: End of periodic frame interrupt.

IEPINT

Bit 18: IN endpoint interrupt.

OEPINT

Bit 19: OUT endpoint interrupt.

IISOIXFR

Bit 20: Incomplete isochronous IN transfer.

IPXFR_INCOMPISOOUT

Bit 21: Incomplete periodic transfer(Host mode)/Incomplete isochronous OUT transfer(Device mode).

HPRTINT

Bit 24: Host port interrupt.

HCINT

Bit 25: Host channels interrupt.

PTXFE

Bit 26: Periodic TxFIFO empty.

CIDSCHG

Bit 28: Connector ID status change.

DISCINT

Bit 29: Disconnect detected interrupt.

SRQINT

Bit 30: Session request/new session detected interrupt.

WKUPINT

Bit 31: Resume/remote wakeup detected interrupt.

FS_GINTMSK

OTG_FS interrupt mask register (OTG_FS_GINTMSK)

Offset: 0x18, reset: 0x00000000, access: Unspecified

1/25 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
WUIM
rw
SRQIM
rw
DISCINT
rw
CIDSCHGM
rw
PTXFEM
rw
HCIM
rw
PRTIM
r
IPXFRM_IISOOXFRM
rw
IISOIXFRM
rw
OEPINT
rw
IEPINT
rw
EPMISM
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
EOPFM
rw
ISOODRPM
rw
ENUMDNEM
rw
USBRST
rw
USBSUSPM
rw
ESUSPM
rw
GONAKEFFM
rw
GINAKEFFM
rw
NPTXFEM
rw
RXFLVLM
rw
SOFM
rw
OTGINT
rw
MMISM
rw
Toggle Fields.

MMISM

Bit 1: Mode mismatch interrupt mask.

OTGINT

Bit 2: OTG interrupt mask.

SOFM

Bit 3: Start of frame mask.

RXFLVLM

Bit 4: Receive FIFO non-empty mask.

NPTXFEM

Bit 5: Non-periodic TxFIFO empty mask.

GINAKEFFM

Bit 6: Global non-periodic IN NAK effective mask.

GONAKEFFM

Bit 7: Global OUT NAK effective mask.

ESUSPM

Bit 10: Early suspend mask.

USBSUSPM

Bit 11: USB suspend mask.

USBRST

Bit 12: USB reset mask.

ENUMDNEM

Bit 13: Enumeration done mask.

ISOODRPM

Bit 14: Isochronous OUT packet dropped interrupt mask.

EOPFM

Bit 15: End of periodic frame interrupt mask.

EPMISM

Bit 17: Endpoint mismatch interrupt mask.

IEPINT

Bit 18: IN endpoints interrupt mask.

OEPINT

Bit 19: OUT endpoints interrupt mask.

IISOIXFRM

Bit 20: Incomplete isochronous IN transfer mask.

IPXFRM_IISOOXFRM

Bit 21: Incomplete periodic transfer mask(Host mode)/Incomplete isochronous OUT transfer mask(Device mode).

PRTIM

Bit 24: Host port interrupt mask.

HCIM

Bit 25: Host channels interrupt mask.

PTXFEM

Bit 26: Periodic TxFIFO empty mask.

CIDSCHGM

Bit 28: Connector ID status change mask.

DISCINT

Bit 29: Disconnect detected interrupt mask.

SRQIM

Bit 30: Session request/new session detected interrupt mask.

WUIM

Bit 31: Resume/remote wakeup detected interrupt mask.

FS_GRXSTSR_Host

OTG_FS Receive status debug read(Host mode)

Offset: 0x1C, reset: 0x00000000, access: read-only

5/5 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
FRMNUM
r
PKTSTS
r
DPID
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DPID
r
BCNT
r
EPNUM
r
Toggle Fields.

EPNUM

Bits 0-3: Endpoint number.

BCNT

Bits 4-14: Byte count.

DPID

Bits 15-16: Data PID.

PKTSTS

Bits 17-20: Packet status.

FRMNUM

Bits 21-24: Frame number.

FS_GRXFSIZ

OTG_FS Receive FIFO size register (OTG_FS_GRXFSIZ)

Offset: 0x24, reset: 0x00000200, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RXFD
rw
Toggle Fields.

RXFD

Bits 0-15: RxFIFO depth.

FS_GNPTXFSIZ_Host

OTG_FS non-periodic transmit FIFO size register (Host mode)

Offset: 0x28, reset: 0x00000200, access: read-write

0/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
NPTXFD
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
NPTXFSA
rw
Toggle Fields.

NPTXFSA

Bits 0-15: Non-periodic transmit RAM start address.

NPTXFD

Bits 16-31: Non-periodic TxFIFO depth.

FS_GNPTXSTS

OTG_FS non-periodic transmit FIFO/queue status register (OTG_FS_GNPTXSTS)

Offset: 0x2C, reset: 0x00080200, access: read-only

3/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
NPTXQTOP
r
NPTQXSAV
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
NPTXFSAV
r
Toggle Fields.

NPTXFSAV

Bits 0-15: Non-periodic TxFIFO space available.

NPTQXSAV

Bits 16-23: Non-periodic transmit request queue space available.

NPTXQTOP

Bits 24-30: Top of the non-periodic transmit request queue.

FS_GCCFG

OTG_FS general core configuration register (OTG_FS_GCCFG)

Offset: 0x38, reset: 0x00000000, access: read-write

0/4 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
SOFOUTEN
rw
VBUSBSEN
rw
VBUSASEN
rw
PWRDWN
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Toggle Fields.

PWRDWN

Bit 16: Power down.

VBUSASEN

Bit 18: Enable the VBUS sensing device.

VBUSBSEN

Bit 19: Enable the VBUS sensing device.

SOFOUTEN

Bit 20: SOF output enable.

FS_CID

core ID register

Offset: 0x3C, reset: 0x00001000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
PRODUCT_ID
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PRODUCT_ID
rw
Toggle Fields.

PRODUCT_ID

Bits 0-31: Product ID field.

FS_HPTXFSIZ

OTG_FS Host periodic transmit FIFO size register (OTG_FS_HPTXFSIZ)

Offset: 0x100, reset: 0x02000600, access: read-write

0/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
PTXFSIZ
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PTXSA
rw
Toggle Fields.

PTXSA

Bits 0-15: Host periodic TxFIFO start address.

PTXFSIZ

Bits 16-31: Host periodic TxFIFO depth.

FS_DIEPTXF1

OTG_FS device IN endpoint transmit FIFO size register (OTG_FS_DIEPTXF2)

Offset: 0x104, reset: 0x02000400, access: read-write

0/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
INEPTXFD
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
INEPTXSA
rw
Toggle Fields.

INEPTXSA

Bits 0-15: IN endpoint FIFO2 transmit RAM start address.

INEPTXFD

Bits 16-31: IN endpoint TxFIFO depth.

FS_DIEPTXF2

OTG_FS device IN endpoint transmit FIFO size register (OTG_FS_DIEPTXF3)

Offset: 0x108, reset: 0x02000400, access: read-write

0/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
INEPTXFD
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
INEPTXSA
rw
Toggle Fields.

INEPTXSA

Bits 0-15: IN endpoint FIFO3 transmit RAM start address.

INEPTXFD

Bits 16-31: IN endpoint TxFIFO depth.

FS_DIEPTXF3

OTG_FS device IN endpoint transmit FIFO size register (OTG_FS_DIEPTXF4)

Offset: 0x10C, reset: 0x02000400, access: read-write

0/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
INEPTXFD
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
INEPTXSA
rw
Toggle Fields.

INEPTXSA

Bits 0-15: IN endpoint FIFO4 transmit RAM start address.

INEPTXFD

Bits 16-31: IN endpoint TxFIFO depth.

OTG_FS_HOST

0x50000400: USB on the go full speed

10/279 fields covered. Toggle Registers.

FS_HCFG

OTG_FS host configuration register (OTG_FS_HCFG)

Offset: 0x0, reset: 0x00000000, access: Unspecified

1/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FSLSS
r
FSLSPCS
rw
Toggle Fields.

FSLSPCS

Bits 0-1: FS/LS PHY clock select.

FSLSS

Bit 2: FS- and LS-only support.

HFIR

OTG_FS Host frame interval register

Offset: 0x4, reset: 0x0000EA60, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FRIVL
rw
Toggle Fields.

FRIVL

Bits 0-15: Frame interval.

FS_HFNUM

OTG_FS host frame number/frame time remaining register (OTG_FS_HFNUM)

Offset: 0x8, reset: 0x00003FFF, access: read-only

2/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
FTREM
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FRNUM
r
Toggle Fields.

FRNUM

Bits 0-15: Frame number.

FTREM

Bits 16-31: Frame time remaining.

FS_HPTXSTS

OTG_FS_Host periodic transmit FIFO/queue status register (OTG_FS_HPTXSTS)

Offset: 0x10, reset: 0x00080100, access: Unspecified

2/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
PTXQTOP
r
PTXQSAV
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PTXFSAVL
rw
Toggle Fields.

PTXFSAVL

Bits 0-15: Periodic transmit data FIFO space available.

PTXQSAV

Bits 16-23: Periodic transmit request queue space available.

PTXQTOP

Bits 24-31: Top of the periodic transmit request queue.

HAINT

OTG_FS Host all channels interrupt register

Offset: 0x14, reset: 0x00000000, access: read-only

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
HAINT
r
Toggle Fields.

HAINT

Bits 0-15: Channel interrupts.

HAINTMSK

OTG_FS host all channels interrupt mask register

Offset: 0x18, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
HAINTM
rw
Toggle Fields.

HAINTM

Bits 0-15: Channel interrupt mask.

FS_HPRT

OTG_FS host port control and status register (OTG_FS_HPRT)

Offset: 0x40, reset: 0x00000000, access: Unspecified

4/13 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
PSPD
r
PTCTL
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PTCTL
rw
PPWR
rw
PLSTS
r
PRST
rw
PSUSP
rw
PRES
rw
POCCHNG
rw
POCA
r
PENCHNG
rw
PENA
rw
PCDET
rw
PCSTS
r
Toggle Fields.

PCSTS

Bit 0: Port connect status.

PCDET

Bit 1: Port connect detected.

PENA

Bit 2: Port enable.

PENCHNG

Bit 3: Port enable/disable change.

POCA

Bit 4: Port overcurrent active.

POCCHNG

Bit 5: Port overcurrent change.

PRES

Bit 6: Port resume.

PSUSP

Bit 7: Port suspend.

PRST

Bit 8: Port reset.

PLSTS

Bits 10-11: Port line status.

PPWR

Bit 12: Port power.

PTCTL

Bits 13-16: Port test control.

PSPD

Bits 17-18: Port speed.

FS_HCCHAR0

OTG_FS host channel-0 characteristics register (OTG_FS_HCCHAR0)

Offset: 0x100, reset: 0x00000000, access: read-write

0/10 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CHENA
rw
CHDIS
rw
ODDFRM
rw
DAD
rw
MCNT
rw
EPTYP
rw
LSDEV
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
EPDIR
rw
EPNUM
rw
MPSIZ
rw
Toggle Fields.

MPSIZ

Bits 0-10: Maximum packet size.

EPNUM

Bits 11-14: Endpoint number.

EPDIR

Bit 15: Endpoint direction.

LSDEV

Bit 17: Low-speed device.

EPTYP

Bits 18-19: Endpoint type.

MCNT

Bits 20-21: Multicount.

DAD

Bits 22-28: Device address.

ODDFRM

Bit 29: Odd frame.

CHDIS

Bit 30: Channel disable.

CHENA

Bit 31: Channel enable.

FS_HCINT0

OTG_FS host channel-0 interrupt register (OTG_FS_HCINT0)

Offset: 0x108, reset: 0x00000000, access: read-write

0/9 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DTERR
rw
FRMOR
rw
BBERR
rw
TXERR
rw
ACK
rw
NAK
rw
STALL
rw
CHH
rw
XFRC
rw
Toggle Fields.

XFRC

Bit 0: Transfer completed.

CHH

Bit 1: Channel halted.

STALL

Bit 3: STALL response received interrupt.

NAK

Bit 4: NAK response received interrupt.

ACK

Bit 5: ACK response received/transmitted interrupt.

TXERR

Bit 7: Transaction error.

BBERR

Bit 8: Babble error.

FRMOR

Bit 9: Frame overrun.

DTERR

Bit 10: Data toggle error.

FS_HCINTMSK0

OTG_FS host channel-0 mask register (OTG_FS_HCINTMSK0)

Offset: 0x10C, reset: 0x00000000, access: read-write

0/10 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DTERRM
rw
FRMORM
rw
BBERRM
rw
TXERRM
rw
NYET
rw
ACKM
rw
NAKM
rw
STALLM
rw
CHHM
rw
XFRCM
rw
Toggle Fields.

XFRCM

Bit 0: Transfer completed mask.

CHHM

Bit 1: Channel halted mask.

STALLM

Bit 3: STALL response received interrupt mask.

NAKM

Bit 4: NAK response received interrupt mask.

ACKM

Bit 5: ACK response received/transmitted interrupt mask.

NYET

Bit 6: response received interrupt mask.

TXERRM

Bit 7: Transaction error mask.

BBERRM

Bit 8: Babble error mask.

FRMORM

Bit 9: Frame overrun mask.

DTERRM

Bit 10: Data toggle error mask.

FS_HCTSIZ0

OTG_FS host channel-0 transfer size register

Offset: 0x110, reset: 0x00000000, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DPID
rw
PKTCNT
rw
XFRSIZ
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
XFRSIZ
rw
Toggle Fields.

XFRSIZ

Bits 0-18: Transfer size.

PKTCNT

Bits 19-28: Packet count.

DPID

Bits 29-30: Data PID.

FS_HCCHAR1

OTG_FS host channel-1 characteristics register (OTG_FS_HCCHAR1)

Offset: 0x120, reset: 0x00000000, access: read-write

0/10 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CHENA
rw
CHDIS
rw
ODDFRM
rw
DAD
rw
MCNT
rw
EPTYP
rw
LSDEV
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
EPDIR
rw
EPNUM
rw
MPSIZ
rw
Toggle Fields.

MPSIZ

Bits 0-10: Maximum packet size.

EPNUM

Bits 11-14: Endpoint number.

EPDIR

Bit 15: Endpoint direction.

LSDEV

Bit 17: Low-speed device.

EPTYP

Bits 18-19: Endpoint type.

MCNT

Bits 20-21: Multicount.

DAD

Bits 22-28: Device address.

ODDFRM

Bit 29: Odd frame.

CHDIS

Bit 30: Channel disable.

CHENA

Bit 31: Channel enable.

FS_HCINT1

OTG_FS host channel-1 interrupt register (OTG_FS_HCINT1)

Offset: 0x128, reset: 0x00000000, access: read-write

0/9 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DTERR
rw
FRMOR
rw
BBERR
rw
TXERR
rw
ACK
rw
NAK
rw
STALL
rw
CHH
rw
XFRC
rw
Toggle Fields.

XFRC

Bit 0: Transfer completed.

CHH

Bit 1: Channel halted.

STALL

Bit 3: STALL response received interrupt.

NAK

Bit 4: NAK response received interrupt.

ACK

Bit 5: ACK response received/transmitted interrupt.

TXERR

Bit 7: Transaction error.

BBERR

Bit 8: Babble error.

FRMOR

Bit 9: Frame overrun.

DTERR

Bit 10: Data toggle error.

FS_HCINTMSK1

OTG_FS host channel-1 mask register (OTG_FS_HCINTMSK1)

Offset: 0x12C, reset: 0x00000000, access: read-write

0/10 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DTERRM
rw
FRMORM
rw
BBERRM
rw
TXERRM
rw
NYET
rw
ACKM
rw
NAKM
rw
STALLM
rw
CHHM
rw
XFRCM
rw
Toggle Fields.

XFRCM

Bit 0: Transfer completed mask.

CHHM

Bit 1: Channel halted mask.

STALLM

Bit 3: STALL response received interrupt mask.

NAKM

Bit 4: NAK response received interrupt mask.

ACKM

Bit 5: ACK response received/transmitted interrupt mask.

NYET

Bit 6: response received interrupt mask.

TXERRM

Bit 7: Transaction error mask.

BBERRM

Bit 8: Babble error mask.

FRMORM

Bit 9: Frame overrun mask.

DTERRM

Bit 10: Data toggle error mask.

FS_HCTSIZ1

OTG_FS host channel-1 transfer size register

Offset: 0x130, reset: 0x00000000, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DPID
rw
PKTCNT
rw
XFRSIZ
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
XFRSIZ
rw
Toggle Fields.

XFRSIZ

Bits 0-18: Transfer size.

PKTCNT

Bits 19-28: Packet count.

DPID

Bits 29-30: Data PID.

FS_HCCHAR2

OTG_FS host channel-2 characteristics register (OTG_FS_HCCHAR2)

Offset: 0x140, reset: 0x00000000, access: read-write

0/10 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CHENA
rw
CHDIS
rw
ODDFRM
rw
DAD
rw
MCNT
rw
EPTYP
rw
LSDEV
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
EPDIR
rw
EPNUM
rw
MPSIZ
rw
Toggle Fields.

MPSIZ

Bits 0-10: Maximum packet size.

EPNUM

Bits 11-14: Endpoint number.

EPDIR

Bit 15: Endpoint direction.

LSDEV

Bit 17: Low-speed device.

EPTYP

Bits 18-19: Endpoint type.

MCNT

Bits 20-21: Multicount.

DAD

Bits 22-28: Device address.

ODDFRM

Bit 29: Odd frame.

CHDIS

Bit 30: Channel disable.

CHENA

Bit 31: Channel enable.

FS_HCINT2

OTG_FS host channel-2 interrupt register (OTG_FS_HCINT2)

Offset: 0x148, reset: 0x00000000, access: read-write

0/9 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DTERR
rw
FRMOR
rw
BBERR
rw
TXERR
rw
ACK
rw
NAK
rw
STALL
rw
CHH
rw
XFRC
rw
Toggle Fields.

XFRC

Bit 0: Transfer completed.

CHH

Bit 1: Channel halted.

STALL

Bit 3: STALL response received interrupt.

NAK

Bit 4: NAK response received interrupt.

ACK

Bit 5: ACK response received/transmitted interrupt.

TXERR

Bit 7: Transaction error.

BBERR

Bit 8: Babble error.

FRMOR

Bit 9: Frame overrun.

DTERR

Bit 10: Data toggle error.

FS_HCINTMSK2

OTG_FS host channel-2 mask register (OTG_FS_HCINTMSK2)

Offset: 0x14C, reset: 0x00000000, access: read-write

0/10 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DTERRM
rw
FRMORM
rw
BBERRM
rw
TXERRM
rw
NYET
rw
ACKM
rw
NAKM
rw
STALLM
rw
CHHM
rw
XFRCM
rw
Toggle Fields.

XFRCM

Bit 0: Transfer completed mask.

CHHM

Bit 1: Channel halted mask.

STALLM

Bit 3: STALL response received interrupt mask.

NAKM

Bit 4: NAK response received interrupt mask.

ACKM

Bit 5: ACK response received/transmitted interrupt mask.

NYET

Bit 6: response received interrupt mask.

TXERRM

Bit 7: Transaction error mask.

BBERRM

Bit 8: Babble error mask.

FRMORM

Bit 9: Frame overrun mask.

DTERRM

Bit 10: Data toggle error mask.

FS_HCTSIZ2

OTG_FS host channel-2 transfer size register

Offset: 0x150, reset: 0x00000000, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DPID
rw
PKTCNT
rw
XFRSIZ
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
XFRSIZ
rw
Toggle Fields.

XFRSIZ

Bits 0-18: Transfer size.

PKTCNT

Bits 19-28: Packet count.

DPID

Bits 29-30: Data PID.

FS_HCCHAR3

OTG_FS host channel-3 characteristics register (OTG_FS_HCCHAR3)

Offset: 0x160, reset: 0x00000000, access: read-write

0/10 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CHENA
rw
CHDIS
rw
ODDFRM
rw
DAD
rw
MCNT
rw
EPTYP
rw
LSDEV
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
EPDIR
rw
EPNUM
rw
MPSIZ
rw
Toggle Fields.

MPSIZ

Bits 0-10: Maximum packet size.

EPNUM

Bits 11-14: Endpoint number.

EPDIR

Bit 15: Endpoint direction.

LSDEV

Bit 17: Low-speed device.

EPTYP

Bits 18-19: Endpoint type.

MCNT

Bits 20-21: Multicount.

DAD

Bits 22-28: Device address.

ODDFRM

Bit 29: Odd frame.

CHDIS

Bit 30: Channel disable.

CHENA

Bit 31: Channel enable.

FS_HCINT3

OTG_FS host channel-3 interrupt register (OTG_FS_HCINT3)

Offset: 0x168, reset: 0x00000000, access: read-write

0/9 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DTERR
rw
FRMOR
rw
BBERR
rw
TXERR
rw
ACK
rw
NAK
rw
STALL
rw
CHH
rw
XFRC
rw
Toggle Fields.

XFRC

Bit 0: Transfer completed.

CHH

Bit 1: Channel halted.

STALL

Bit 3: STALL response received interrupt.

NAK

Bit 4: NAK response received interrupt.

ACK

Bit 5: ACK response received/transmitted interrupt.

TXERR

Bit 7: Transaction error.

BBERR

Bit 8: Babble error.

FRMOR

Bit 9: Frame overrun.

DTERR

Bit 10: Data toggle error.

FS_HCINTMSK3

OTG_FS host channel-3 mask register (OTG_FS_HCINTMSK3)

Offset: 0x16C, reset: 0x00000000, access: read-write

0/10 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DTERRM
rw
FRMORM
rw
BBERRM
rw
TXERRM
rw
NYET
rw
ACKM
rw
NAKM
rw
STALLM
rw
CHHM
rw
XFRCM
rw
Toggle Fields.

XFRCM

Bit 0: Transfer completed mask.

CHHM

Bit 1: Channel halted mask.

STALLM

Bit 3: STALL response received interrupt mask.

NAKM

Bit 4: NAK response received interrupt mask.

ACKM

Bit 5: ACK response received/transmitted interrupt mask.

NYET

Bit 6: response received interrupt mask.

TXERRM

Bit 7: Transaction error mask.

BBERRM

Bit 8: Babble error mask.

FRMORM

Bit 9: Frame overrun mask.

DTERRM

Bit 10: Data toggle error mask.

FS_HCTSIZ3

OTG_FS host channel-3 transfer size register

Offset: 0x170, reset: 0x00000000, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DPID
rw
PKTCNT
rw
XFRSIZ
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
XFRSIZ
rw
Toggle Fields.

XFRSIZ

Bits 0-18: Transfer size.

PKTCNT

Bits 19-28: Packet count.

DPID

Bits 29-30: Data PID.

FS_HCCHAR4

OTG_FS host channel-4 characteristics register (OTG_FS_HCCHAR4)

Offset: 0x180, reset: 0x00000000, access: read-write

0/10 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CHENA
rw
CHDIS
rw
ODDFRM
rw
DAD
rw
MCNT
rw
EPTYP
rw
LSDEV
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
EPDIR
rw
EPNUM
rw
MPSIZ
rw
Toggle Fields.

MPSIZ

Bits 0-10: Maximum packet size.

EPNUM

Bits 11-14: Endpoint number.

EPDIR

Bit 15: Endpoint direction.

LSDEV

Bit 17: Low-speed device.

EPTYP

Bits 18-19: Endpoint type.

MCNT

Bits 20-21: Multicount.

DAD

Bits 22-28: Device address.

ODDFRM

Bit 29: Odd frame.

CHDIS

Bit 30: Channel disable.

CHENA

Bit 31: Channel enable.

FS_HCINT4

OTG_FS host channel-4 interrupt register (OTG_FS_HCINT4)

Offset: 0x188, reset: 0x00000000, access: read-write

0/9 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DTERR
rw
FRMOR
rw
BBERR
rw
TXERR
rw
ACK
rw
NAK
rw
STALL
rw
CHH
rw
XFRC
rw
Toggle Fields.

XFRC

Bit 0: Transfer completed.

CHH

Bit 1: Channel halted.

STALL

Bit 3: STALL response received interrupt.

NAK

Bit 4: NAK response received interrupt.

ACK

Bit 5: ACK response received/transmitted interrupt.

TXERR

Bit 7: Transaction error.

BBERR

Bit 8: Babble error.

FRMOR

Bit 9: Frame overrun.

DTERR

Bit 10: Data toggle error.

FS_HCINTMSK4

OTG_FS host channel-4 mask register (OTG_FS_HCINTMSK4)

Offset: 0x18C, reset: 0x00000000, access: read-write

0/10 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DTERRM
rw
FRMORM
rw
BBERRM
rw
TXERRM
rw
NYET
rw
ACKM
rw
NAKM
rw
STALLM
rw
CHHM
rw
XFRCM
rw
Toggle Fields.

XFRCM

Bit 0: Transfer completed mask.

CHHM

Bit 1: Channel halted mask.

STALLM

Bit 3: STALL response received interrupt mask.

NAKM

Bit 4: NAK response received interrupt mask.

ACKM

Bit 5: ACK response received/transmitted interrupt mask.

NYET

Bit 6: response received interrupt mask.

TXERRM

Bit 7: Transaction error mask.

BBERRM

Bit 8: Babble error mask.

FRMORM

Bit 9: Frame overrun mask.

DTERRM

Bit 10: Data toggle error mask.

FS_HCTSIZ4

OTG_FS host channel-x transfer size register

Offset: 0x190, reset: 0x00000000, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DPID
rw
PKTCNT
rw
XFRSIZ
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
XFRSIZ
rw
Toggle Fields.

XFRSIZ

Bits 0-18: Transfer size.

PKTCNT

Bits 19-28: Packet count.

DPID

Bits 29-30: Data PID.

FS_HCCHAR5

OTG_FS host channel-5 characteristics register (OTG_FS_HCCHAR5)

Offset: 0x1A0, reset: 0x00000000, access: read-write

0/10 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CHENA
rw
CHDIS
rw
ODDFRM
rw
DAD
rw
MCNT
rw
EPTYP
rw
LSDEV
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
EPDIR
rw
EPNUM
rw
MPSIZ
rw
Toggle Fields.

MPSIZ

Bits 0-10: Maximum packet size.

EPNUM

Bits 11-14: Endpoint number.

EPDIR

Bit 15: Endpoint direction.

LSDEV

Bit 17: Low-speed device.

EPTYP

Bits 18-19: Endpoint type.

MCNT

Bits 20-21: Multicount.

DAD

Bits 22-28: Device address.

ODDFRM

Bit 29: Odd frame.

CHDIS

Bit 30: Channel disable.

CHENA

Bit 31: Channel enable.

FS_HCINT5

OTG_FS host channel-5 interrupt register (OTG_FS_HCINT5)

Offset: 0x1A8, reset: 0x00000000, access: read-write

0/9 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DTERR
rw
FRMOR
rw
BBERR
rw
TXERR
rw
ACK
rw
NAK
rw
STALL
rw
CHH
rw
XFRC
rw
Toggle Fields.

XFRC

Bit 0: Transfer completed.

CHH

Bit 1: Channel halted.

STALL

Bit 3: STALL response received interrupt.

NAK

Bit 4: NAK response received interrupt.

ACK

Bit 5: ACK response received/transmitted interrupt.

TXERR

Bit 7: Transaction error.

BBERR

Bit 8: Babble error.

FRMOR

Bit 9: Frame overrun.

DTERR

Bit 10: Data toggle error.

FS_HCINTMSK5

OTG_FS host channel-5 mask register (OTG_FS_HCINTMSK5)

Offset: 0x1AC, reset: 0x00000000, access: read-write

0/10 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DTERRM
rw
FRMORM
rw
BBERRM
rw
TXERRM
rw
NYET
rw
ACKM
rw
NAKM
rw
STALLM
rw
CHHM
rw
XFRCM
rw
Toggle Fields.

XFRCM

Bit 0: Transfer completed mask.

CHHM

Bit 1: Channel halted mask.

STALLM

Bit 3: STALL response received interrupt mask.

NAKM

Bit 4: NAK response received interrupt mask.

ACKM

Bit 5: ACK response received/transmitted interrupt mask.

NYET

Bit 6: response received interrupt mask.

TXERRM

Bit 7: Transaction error mask.

BBERRM

Bit 8: Babble error mask.

FRMORM

Bit 9: Frame overrun mask.

DTERRM

Bit 10: Data toggle error mask.

FS_HCTSIZ5

OTG_FS host channel-5 transfer size register

Offset: 0x1B0, reset: 0x00000000, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DPID
rw
PKTCNT
rw
XFRSIZ
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
XFRSIZ
rw
Toggle Fields.

XFRSIZ

Bits 0-18: Transfer size.

PKTCNT

Bits 19-28: Packet count.

DPID

Bits 29-30: Data PID.

FS_HCCHAR6

OTG_FS host channel-6 characteristics register (OTG_FS_HCCHAR6)

Offset: 0x1C0, reset: 0x00000000, access: read-write

0/10 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CHENA
rw
CHDIS
rw
ODDFRM
rw
DAD
rw
MCNT
rw
EPTYP
rw
LSDEV
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
EPDIR
rw
EPNUM
rw
MPSIZ
rw
Toggle Fields.

MPSIZ

Bits 0-10: Maximum packet size.

EPNUM

Bits 11-14: Endpoint number.

EPDIR

Bit 15: Endpoint direction.

LSDEV

Bit 17: Low-speed device.

EPTYP

Bits 18-19: Endpoint type.

MCNT

Bits 20-21: Multicount.

DAD

Bits 22-28: Device address.

ODDFRM

Bit 29: Odd frame.

CHDIS

Bit 30: Channel disable.

CHENA

Bit 31: Channel enable.

FS_HCINT6

OTG_FS host channel-6 interrupt register (OTG_FS_HCINT6)

Offset: 0x1C8, reset: 0x00000000, access: read-write

0/9 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DTERR
rw
FRMOR
rw
BBERR
rw
TXERR
rw
ACK
rw
NAK
rw
STALL
rw
CHH
rw
XFRC
rw
Toggle Fields.

XFRC

Bit 0: Transfer completed.

CHH

Bit 1: Channel halted.

STALL

Bit 3: STALL response received interrupt.

NAK

Bit 4: NAK response received interrupt.

ACK

Bit 5: ACK response received/transmitted interrupt.

TXERR

Bit 7: Transaction error.

BBERR

Bit 8: Babble error.

FRMOR

Bit 9: Frame overrun.

DTERR

Bit 10: Data toggle error.

FS_HCINTMSK6

OTG_FS host channel-6 mask register (OTG_FS_HCINTMSK6)

Offset: 0x1CC, reset: 0x00000000, access: read-write

0/10 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DTERRM
rw
FRMORM
rw
BBERRM
rw
TXERRM
rw
NYET
rw
ACKM
rw
NAKM
rw
STALLM
rw
CHHM
rw
XFRCM
rw
Toggle Fields.

XFRCM

Bit 0: Transfer completed mask.

CHHM

Bit 1: Channel halted mask.

STALLM

Bit 3: STALL response received interrupt mask.

NAKM

Bit 4: NAK response received interrupt mask.

ACKM

Bit 5: ACK response received/transmitted interrupt mask.

NYET

Bit 6: response received interrupt mask.

TXERRM

Bit 7: Transaction error mask.

BBERRM

Bit 8: Babble error mask.

FRMORM

Bit 9: Frame overrun mask.

DTERRM

Bit 10: Data toggle error mask.

FS_HCTSIZ6

OTG_FS host channel-6 transfer size register

Offset: 0x1D0, reset: 0x00000000, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DPID
rw
PKTCNT
rw
XFRSIZ
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
XFRSIZ
rw
Toggle Fields.

XFRSIZ

Bits 0-18: Transfer size.

PKTCNT

Bits 19-28: Packet count.

DPID

Bits 29-30: Data PID.

FS_HCCHAR7

OTG_FS host channel-7 characteristics register (OTG_FS_HCCHAR7)

Offset: 0x1E0, reset: 0x00000000, access: read-write

0/10 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CHENA
rw
CHDIS
rw
ODDFRM
rw
DAD
rw
MCNT
rw
EPTYP
rw
LSDEV
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
EPDIR
rw
EPNUM
rw
MPSIZ
rw
Toggle Fields.

MPSIZ

Bits 0-10: Maximum packet size.

EPNUM

Bits 11-14: Endpoint number.

EPDIR

Bit 15: Endpoint direction.

LSDEV

Bit 17: Low-speed device.

EPTYP

Bits 18-19: Endpoint type.

MCNT

Bits 20-21: Multicount.

DAD

Bits 22-28: Device address.

ODDFRM

Bit 29: Odd frame.

CHDIS

Bit 30: Channel disable.

CHENA

Bit 31: Channel enable.

FS_HCINT7

OTG_FS host channel-7 interrupt register (OTG_FS_HCINT7)

Offset: 0x1E8, reset: 0x00000000, access: read-write

0/9 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DTERR
rw
FRMOR
rw
BBERR
rw
TXERR
rw
ACK
rw
NAK
rw
STALL
rw
CHH
rw
XFRC
rw
Toggle Fields.

XFRC

Bit 0: Transfer completed.

CHH

Bit 1: Channel halted.

STALL

Bit 3: STALL response received interrupt.

NAK

Bit 4: NAK response received interrupt.

ACK

Bit 5: ACK response received/transmitted interrupt.

TXERR

Bit 7: Transaction error.

BBERR

Bit 8: Babble error.

FRMOR

Bit 9: Frame overrun.

DTERR

Bit 10: Data toggle error.

FS_HCINTMSK7

OTG_FS host channel-7 mask register (OTG_FS_HCINTMSK7)

Offset: 0x1EC, reset: 0x00000000, access: read-write

0/10 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DTERRM
rw
FRMORM
rw
BBERRM
rw
TXERRM
rw
NYET
rw
ACKM
rw
NAKM
rw
STALLM
rw
CHHM
rw
XFRCM
rw
Toggle Fields.

XFRCM

Bit 0: Transfer completed mask.

CHHM

Bit 1: Channel halted mask.

STALLM

Bit 3: STALL response received interrupt mask.

NAKM

Bit 4: NAK response received interrupt mask.

ACKM

Bit 5: ACK response received/transmitted interrupt mask.

NYET

Bit 6: response received interrupt mask.

TXERRM

Bit 7: Transaction error mask.

BBERRM

Bit 8: Babble error mask.

FRMORM

Bit 9: Frame overrun mask.

DTERRM

Bit 10: Data toggle error mask.

FS_HCTSIZ7

OTG_FS host channel-7 transfer size register

Offset: 0x1F0, reset: 0x00000000, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DPID
rw
PKTCNT
rw
XFRSIZ
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
XFRSIZ
rw
Toggle Fields.

XFRSIZ

Bits 0-18: Transfer size.

PKTCNT

Bits 19-28: Packet count.

DPID

Bits 29-30: Data PID.

OTG_FS_PWRCLK

0x50000E00: USB on the go full speed

0/3 fields covered. Toggle Registers.

FS_PCGCCTL

OTG_FS power and clock gating control register

Offset: 0x0, reset: 0x00000000, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PHYSUSP
rw
GATEHCLK
rw
STPPCLK
rw
Toggle Fields.

STPPCLK

Bit 0: Stop PHY clock.

GATEHCLK

Bit 1: Gate HCLK.

PHYSUSP

Bit 4: PHY Suspended.

PWR

0x40007000: Power control

4/11 fields covered. Toggle Registers.

CR

Power control register (PWR_CR)

Offset: 0x0, reset: 0x00000000, access: read-write

1/7 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DBP
rw
PLS
rw
PVDE
rw
CSBF
rw
CWUF
rw
PDDS
rw
LPDS
rw
Toggle Fields.

LPDS

Bit 0: Low Power Deep Sleep.

PDDS

Bit 1: Power Down Deep Sleep.

Allowed values:
0: STOP_MODE: Enter Stop mode when the CPU enters deepsleep
1: STANDBY_MODE: Enter Standby mode when the CPU enters deepsleep

CWUF

Bit 2: Clear Wake-up Flag.

CSBF

Bit 3: Clear STANDBY Flag.

PVDE

Bit 4: Power Voltage Detector Enable.

PLS

Bits 5-7: PVD Level Selection.

DBP

Bit 8: Disable Backup Domain write protection.

CSR

Power control register (PWR_CR)

Offset: 0x4, reset: 0x00000000, access: Unspecified

3/4 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
EWUP
rw
PVDO
r
SBF
r
WUF
r
Toggle Fields.

WUF

Bit 0: Wake-Up Flag.

SBF

Bit 1: STANDBY Flag.

PVDO

Bit 2: PVD Output.

EWUP

Bit 8: Enable WKUP pin.

RCC

0x40021000: Reset and clock control

142/142 fields covered. Toggle Registers.

CR

Clock control register

Offset: 0x0, reset: 0x00000083, access: Unspecified

10/10 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
PLLRDY
r
PLLON
rw
CSSON
rw
HSEBYP
rw
HSERDY
r
HSEON
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
HSICAL
r
HSITRIM
rw
HSIRDY
r
HSION
rw
Toggle Fields.

HSION

Bit 0: Internal High Speed clock enable.

Allowed values:
0: Off: Clock Off
1: On: Clock On

HSIRDY

Bit 1: Internal High Speed clock ready flag.

Allowed values:
0: NotReady: Clock not ready
1: Ready: Clock ready

HSITRIM

Bits 3-7: Internal High Speed clock trimming.

Allowed values: 0-31

HSICAL

Bits 8-15: Internal High Speed clock Calibration.

Allowed values: 0-255

HSEON

Bit 16: External High Speed clock enable.

Allowed values:
0: Off: Clock Off
1: On: Clock On

HSERDY

Bit 17: External High Speed clock ready flag.

Allowed values:
0: NotReady: Clock not ready
1: Ready: Clock ready

HSEBYP

Bit 18: External High Speed clock Bypass.

Allowed values:
0: NotBypassed: HSE crystal oscillator not bypassed
1: Bypassed: HSE crystal oscillator bypassed with external clock

CSSON

Bit 19: Clock Security System enable.

Allowed values:
0: Off: Clock security system disabled (clock detector OFF)
1: On: Clock security system enable (clock detector ON if the HSE is ready, OFF if not)

PLLON

Bit 24: PLL enable.

Allowed values:
0: Off: Clock Off
1: On: Clock On

PLLRDY

Bit 25: PLL clock ready flag.

Allowed values:
0: NotReady: Clock not ready
1: Ready: Clock ready

CFGR

Clock configuration register (RCC_CFGR)

Offset: 0x4, reset: 0x00000000, access: Unspecified

11/11 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
MCO
rw
USBPRE
rw
PLLMUL
rw
PLLXTPRE
rw
PLLSRC
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ADCPRE
rw
PPRE2
rw
PPRE1
rw
HPRE
rw
SWS
r
SW
rw
Toggle Fields.

SW

Bits 0-1: System clock Switch.

Allowed values:
0: HSI: HSI selected as system clock
1: HSE: HSE selected as system clock
2: PLL: PLL selected as system clock

SWS

Bits 2-3: System Clock Switch Status.

Allowed values:
0: HSI: HSE oscillator used as system clock
1: HSE: HSI oscillator used as system clock
2: PLL: PLL used as system clock

HPRE

Bits 4-7: AHB prescaler.

Allowed values:
0: Div1: SYSCLK not divided
8: Div2: SYSCLK divided by 2
9: Div4: SYSCLK divided by 4
10: Div8: SYSCLK divided by 8
11: Div16: SYSCLK divided by 16
12: Div64: SYSCLK divided by 64
13: Div128: SYSCLK divided by 128
14: Div256: SYSCLK divided by 256
15: Div512: SYSCLK divided by 512

PPRE1

Bits 8-10: APB Low speed prescaler (APB1).

Allowed values:
0: Div1: HCLK not divided
4: Div2: HCLK divided by 2
5: Div4: HCLK divided by 4
6: Div8: HCLK divided by 8
7: Div16: HCLK divided by 16

PPRE2

Bits 11-13: APB High speed prescaler (APB2).

Allowed values:
0: Div1: HCLK not divided
4: Div2: HCLK divided by 2
5: Div4: HCLK divided by 4
6: Div8: HCLK divided by 8
7: Div16: HCLK divided by 16

ADCPRE

Bits 14-15: ADC prescaler.

Allowed values:
0: Div2: PCLK2 divided by 2
1: Div4: PCLK2 divided by 4
2: Div6: PCLK2 divided by 8
3: Div8: PCLK2 divided by 16

PLLSRC

Bit 16: PLL entry clock source.

Allowed values:
0: HSI_Div2: HSI divided by 2 selected as PLL input clock
1: HSE_Div_PREDIV: HSE divided by PREDIV selected as PLL input clock

PLLXTPRE

Bit 17: HSE divider for PLL entry.

Allowed values:
0: Div1: HSE clock not divided
1: Div2: HSE clock divided by 2

PLLMUL

Bits 18-21: PLL Multiplication Factor.

Allowed values:
0: Mul2: PLL input clock x2
1: Mul3: PLL input clock x3
2: Mul4: PLL input clock x4
3: Mul5: PLL input clock x5
4: Mul6: PLL input clock x6
5: Mul7: PLL input clock x7
6: Mul8: PLL input clock x8
7: Mul9: PLL input clock x9
8: Mul10: PLL input clock x10
9: Mul11: PLL input clock x11
10: Mul12: PLL input clock x12
11: Mul13: PLL input clock x13
12: Mul14: PLL input clock x14
13: Mul15: PLL input clock x15
14: Mul16: PLL input clock x16
15: Mul16x: PLL input clock x16

USBPRE

Bit 22: USB prescaler.

Allowed values:
0: DIV1_5: PLL clock is divided by 1.5
1: DIV1: PLL clock is not divided

MCO

Bits 24-26: Microcontroller clock output.

Allowed values:
0: NoMCO: MCO output disabled, no clock on MCO
4: SYSCLK: System clock selected
5: HSI: HSI oscillator clock selected
6: HSE: HSE oscillator clock selected
7: PLL: PLL clock selected (divided by 1 or 2, depending en PLLNODIV)

CIR

Clock interrupt register (RCC_CIR)

Offset: 0x8, reset: 0x00000000, access: Unspecified

17/17 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CSSC
w
PLLRDYC
w
HSERDYC
w
HSIRDYC
w
LSERDYC
w
LSIRDYC
w
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PLLRDYIE
rw
HSERDYIE
rw
HSIRDYIE
rw
LSERDYIE
rw
LSIRDYIE
rw
CSSF
r
PLLRDYF
r
HSERDYF
r
HSIRDYF
r
LSERDYF
r
LSIRDYF
r
Toggle Fields.

LSIRDYF

Bit 0: LSI Ready Interrupt flag.

Allowed values:
0: NotInterrupted: No clock ready interrupt
1: Interrupted: Clock ready interrupt

LSERDYF

Bit 1: LSE Ready Interrupt flag.

Allowed values:
0: NotInterrupted: No clock ready interrupt
1: Interrupted: Clock ready interrupt

HSIRDYF

Bit 2: HSI Ready Interrupt flag.

Allowed values:
0: NotInterrupted: No clock ready interrupt
1: Interrupted: Clock ready interrupt

HSERDYF

Bit 3: HSE Ready Interrupt flag.

Allowed values:
0: NotInterrupted: No clock ready interrupt
1: Interrupted: Clock ready interrupt

PLLRDYF

Bit 4: PLL Ready Interrupt flag.

Allowed values:
0: NotInterrupted: No clock ready interrupt
1: Interrupted: Clock ready interrupt

CSSF

Bit 7: Clock Security System Interrupt flag.

Allowed values:
0: NotInterrupted: No clock security interrupt caused by HSE clock failure
1: Interrupted: Clock security interrupt caused by HSE clock failure

LSIRDYIE

Bit 8: LSI Ready Interrupt Enable.

Allowed values:
0: Disabled: Interrupt disabled
1: Enabled: Interrupt enabled

LSERDYIE

Bit 9: LSE Ready Interrupt Enable.

Allowed values:
0: Disabled: Interrupt disabled
1: Enabled: Interrupt enabled

HSIRDYIE

Bit 10: HSI Ready Interrupt Enable.

Allowed values:
0: Disabled: Interrupt disabled
1: Enabled: Interrupt enabled

HSERDYIE

Bit 11: HSE Ready Interrupt Enable.

Allowed values:
0: Disabled: Interrupt disabled
1: Enabled: Interrupt enabled

PLLRDYIE

Bit 12: PLL Ready Interrupt Enable.

Allowed values:
0: Disabled: Interrupt disabled
1: Enabled: Interrupt enabled

LSIRDYC

Bit 16: LSI Ready Interrupt Clear.

Allowed values:
1: Clear: Clear interrupt flag

LSERDYC

Bit 17: LSE Ready Interrupt Clear.

Allowed values:
1: Clear: Clear interrupt flag

HSIRDYC

Bit 18: HSI Ready Interrupt Clear.

Allowed values:
1: Clear: Clear interrupt flag

HSERDYC

Bit 19: HSE Ready Interrupt Clear.

Allowed values:
1: Clear: Clear interrupt flag

PLLRDYC

Bit 20: PLL Ready Interrupt Clear.

Allowed values:
1: Clear: Clear interrupt flag

CSSC

Bit 23: Clock security system interrupt clear.

Allowed values:
1: Clear: Clear CSSF flag

APB2RSTR

APB2 peripheral reset register (RCC_APB2RSTR)

Offset: 0xC, reset: 0x000000000, access: read-write

18/18 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
TIM11RST
rw
TIM10RST
rw
TIM9RST
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ADC3RST
rw
USART1RST
rw
TIM8RST
rw
SPI1RST
rw
TIM1RST
rw
ADC2RST
rw
ADC1RST
rw
IOPGRST
rw
IOPFRST
rw
IOPERST
rw
IOPDRST
rw
IOPCRST
rw
IOPBRST
rw
IOPARST
rw
AFIORST
rw
Toggle Fields.

AFIORST

Bit 0: Alternate function I/O reset.

Allowed values:
1: Reset: Reset the selected module

IOPARST

Bit 2: IO port A reset.

Allowed values:
1: Reset: Reset the selected module

IOPBRST

Bit 3: IO port B reset.

Allowed values:
1: Reset: Reset the selected module

IOPCRST

Bit 4: IO port C reset.

Allowed values:
1: Reset: Reset the selected module

IOPDRST

Bit 5: IO port D reset.

Allowed values:
1: Reset: Reset the selected module

IOPERST

Bit 6: IO port E reset.

Allowed values:
1: Reset: Reset the selected module

IOPFRST

Bit 7: IO port F reset.

Allowed values:
1: Reset: Reset the selected module

IOPGRST

Bit 8: IO port G reset.

Allowed values:
1: Reset: Reset the selected module

ADC1RST

Bit 9: ADC 1 interface reset.

Allowed values:
1: Reset: Reset the selected module

ADC2RST

Bit 10: ADC 2 interface reset.

Allowed values:
1: Reset: Reset the selected module

TIM1RST

Bit 11: TIM1 timer reset.

Allowed values:
1: Reset: Reset the selected module

SPI1RST

Bit 12: SPI 1 reset.

Allowed values:
1: Reset: Reset the selected module

TIM8RST

Bit 13: TIM8 timer reset.

Allowed values:
1: Reset: Reset the selected module

USART1RST

Bit 14: USART1 reset.

Allowed values:
1: Reset: Reset the selected module

ADC3RST

Bit 15: ADC 3 interface reset.

Allowed values:
1: Reset: Reset the selected module

TIM9RST

Bit 19: TIM9 timer reset.

Allowed values:
1: Reset: Reset the selected module

TIM10RST

Bit 20: TIM10 timer reset.

Allowed values:
1: Reset: Reset the selected module

TIM11RST

Bit 21: TIM11 timer reset.

Allowed values:
1: Reset: Reset the selected module

APB1RSTR

APB1 peripheral reset register (RCC_APB1RSTR)

Offset: 0x10, reset: 0x00000000, access: read-write

23/23 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DACRST
rw
PWRRST
rw
BKPRST
rw
CANRST
rw
USBRST
rw
I2C2RST
rw
I2C1RST
rw
UART5RST
rw
UART4RST
rw
USART3RST
rw
USART2RST
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SPI3RST
rw
SPI2RST
rw
WWDGRST
rw
TIM14RST
rw
TIM13RST
rw
TIM12RST
rw
TIM7RST
rw
TIM6RST
rw
TIM5RST
rw
TIM4RST
rw
TIM3RST
rw
TIM2RST
rw
Toggle Fields.

TIM2RST

Bit 0: Timer 2 reset.

Allowed values:
1: Reset: Reset the selected module

TIM3RST

Bit 1: Timer 3 reset.

Allowed values:
1: Reset: Reset the selected module

TIM4RST

Bit 2: Timer 4 reset.

Allowed values:
1: Reset: Reset the selected module

TIM5RST

Bit 3: Timer 5 reset.

Allowed values:
1: Reset: Reset the selected module

TIM6RST

Bit 4: Timer 6 reset.

Allowed values:
1: Reset: Reset the selected module

TIM7RST

Bit 5: Timer 7 reset.

Allowed values:
1: Reset: Reset the selected module

TIM12RST

Bit 6: Timer 12 reset.

Allowed values:
1: Reset: Reset the selected module

TIM13RST

Bit 7: Timer 13 reset.

Allowed values:
1: Reset: Reset the selected module

TIM14RST

Bit 8: Timer 14 reset.

Allowed values:
1: Reset: Reset the selected module

WWDGRST

Bit 11: Window watchdog reset.

Allowed values:
1: Reset: Reset the selected module

SPI2RST

Bit 14: SPI2 reset.

Allowed values:
1: Reset: Reset the selected module

SPI3RST

Bit 15: SPI3 reset.

Allowed values:
1: Reset: Reset the selected module

USART2RST

Bit 17: USART 2 reset.

Allowed values:
1: Reset: Reset the selected module

USART3RST

Bit 18: USART 3 reset.

Allowed values:
1: Reset: Reset the selected module

UART4RST

Bit 19: UART 4 reset.

Allowed values:
1: Reset: Reset the selected module

UART5RST

Bit 20: UART 5 reset.

Allowed values:
1: Reset: Reset the selected module

I2C1RST

Bit 21: I2C1 reset.

Allowed values:
1: Reset: Reset the selected module

I2C2RST

Bit 22: I2C2 reset.

Allowed values:
1: Reset: Reset the selected module

USBRST

Bit 23: USB reset.

Allowed values:
1: Reset: Reset the selected module

CANRST

Bit 25: CAN reset.

Allowed values:
1: Reset: Reset the selected module

BKPRST

Bit 27: Backup interface reset.

Allowed values:
1: Reset: Reset the selected module

PWRRST

Bit 28: Power interface reset.

Allowed values:
1: Reset: Reset the selected module

DACRST

Bit 29: DAC interface reset.

Allowed values:
1: Reset: Reset the selected module

AHBENR

AHB Peripheral Clock enable register (RCC_AHBENR)

Offset: 0x14, reset: 0x00000014, access: read-write

7/7 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SDIOEN
rw
FSMCEN
rw
CRCEN
rw
FLITFEN
rw
SRAMEN
rw
DMA2EN
rw
DMA1EN
rw
Toggle Fields.

DMA1EN

Bit 0: DMA1 clock enable.

Allowed values:
0: Disabled: The selected clock is disabled
1: Enabled: The selected clock is enabled

DMA2EN

Bit 1: DMA2 clock enable.

Allowed values:
0: Disabled: The selected clock is disabled
1: Enabled: The selected clock is enabled

SRAMEN

Bit 2: SRAM interface clock enable.

Allowed values:
0: Disabled: The selected clock is disabled
1: Enabled: The selected clock is enabled

FLITFEN

Bit 4: FLITF clock enable.

Allowed values:
0: Disabled: The selected clock is disabled
1: Enabled: The selected clock is enabled

CRCEN

Bit 6: CRC clock enable.

Allowed values:
0: Disabled: The selected clock is disabled
1: Enabled: The selected clock is enabled

FSMCEN

Bit 8: FSMC clock enable.

Allowed values:
0: Disabled: The selected clock is disabled
1: Enabled: The selected clock is enabled

SDIOEN

Bit 10: SDIO clock enable.

Allowed values:
0: Disabled: The selected clock is disabled
1: Enabled: The selected clock is enabled

APB2ENR

APB2 peripheral clock enable register (RCC_APB2ENR)

Offset: 0x18, reset: 0x00000000, access: read-write

18/18 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
TIM11EN
rw
TIM10EN
rw
TIM9EN
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ADC3EN
rw
USART1EN
rw
TIM8EN
rw
SPI1EN
rw
TIM1EN
rw
ADC2EN
rw
ADC1EN
rw
IOPGEN
rw
IOPFEN
rw
IOPEEN
rw
IOPDEN
rw
IOPCEN
rw
IOPBEN
rw
IOPAEN
rw
AFIOEN
rw
Toggle Fields.

AFIOEN

Bit 0: Alternate function I/O clock enable.

Allowed values:
0: Disabled: The selected clock is disabled
1: Enabled: The selected clock is enabled

IOPAEN

Bit 2: I/O port A clock enable.

Allowed values:
0: Disabled: The selected clock is disabled
1: Enabled: The selected clock is enabled

IOPBEN

Bit 3: I/O port B clock enable.

Allowed values:
0: Disabled: The selected clock is disabled
1: Enabled: The selected clock is enabled

IOPCEN

Bit 4: I/O port C clock enable.

Allowed values:
0: Disabled: The selected clock is disabled
1: Enabled: The selected clock is enabled

IOPDEN

Bit 5: I/O port D clock enable.

Allowed values:
0: Disabled: The selected clock is disabled
1: Enabled: The selected clock is enabled

IOPEEN

Bit 6: I/O port E clock enable.

Allowed values:
0: Disabled: The selected clock is disabled
1: Enabled: The selected clock is enabled

IOPFEN

Bit 7: I/O port F clock enable.

Allowed values:
0: Disabled: The selected clock is disabled
1: Enabled: The selected clock is enabled

IOPGEN

Bit 8: I/O port G clock enable.

Allowed values:
0: Disabled: The selected clock is disabled
1: Enabled: The selected clock is enabled

ADC1EN

Bit 9: ADC 1 interface clock enable.

Allowed values:
0: Disabled: The selected clock is disabled
1: Enabled: The selected clock is enabled

ADC2EN

Bit 10: ADC 2 interface clock enable.

Allowed values:
0: Disabled: The selected clock is disabled
1: Enabled: The selected clock is enabled

TIM1EN

Bit 11: TIM1 Timer clock enable.

Allowed values:
0: Disabled: The selected clock is disabled
1: Enabled: The selected clock is enabled

SPI1EN

Bit 12: SPI 1 clock enable.

Allowed values:
0: Disabled: The selected clock is disabled
1: Enabled: The selected clock is enabled

TIM8EN

Bit 13: TIM8 Timer clock enable.

Allowed values:
0: Disabled: The selected clock is disabled
1: Enabled: The selected clock is enabled

USART1EN

Bit 14: USART1 clock enable.

Allowed values:
0: Disabled: The selected clock is disabled
1: Enabled: The selected clock is enabled

ADC3EN

Bit 15: ADC3 interface clock enable.

Allowed values:
0: Disabled: The selected clock is disabled
1: Enabled: The selected clock is enabled

TIM9EN

Bit 19: TIM9 Timer clock enable.

Allowed values:
0: Disabled: The selected clock is disabled
1: Enabled: The selected clock is enabled

TIM10EN

Bit 20: TIM10 Timer clock enable.

Allowed values:
0: Disabled: The selected clock is disabled
1: Enabled: The selected clock is enabled

TIM11EN

Bit 21: TIM11 Timer clock enable.

Allowed values:
0: Disabled: The selected clock is disabled
1: Enabled: The selected clock is enabled

APB1ENR

APB1 peripheral clock enable register (RCC_APB1ENR)

Offset: 0x1C, reset: 0x00000000, access: read-write

23/23 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DACEN
rw
PWREN
rw
BKPEN
rw
CANEN
rw
USBEN
rw
I2C2EN
rw
I2C1EN
rw
UART5EN
rw
UART4EN
rw
USART3EN
rw
USART2EN
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SPI3EN
rw
SPI2EN
rw
WWDGEN
rw
TIM14EN
rw
TIM13EN
rw
TIM12EN
rw
TIM7EN
rw
TIM6EN
rw
TIM5EN
rw
TIM4EN
rw
TIM3EN
rw
TIM2EN
rw
Toggle Fields.

TIM2EN

Bit 0: Timer 2 clock enable.

Allowed values:
0: Disabled: The selected clock is disabled
1: Enabled: The selected clock is enabled

TIM3EN

Bit 1: Timer 3 clock enable.

Allowed values:
0: Disabled: The selected clock is disabled
1: Enabled: The selected clock is enabled

TIM4EN

Bit 2: Timer 4 clock enable.

Allowed values:
0: Disabled: The selected clock is disabled
1: Enabled: The selected clock is enabled

TIM5EN

Bit 3: Timer 5 clock enable.

Allowed values:
0: Disabled: The selected clock is disabled
1: Enabled: The selected clock is enabled

TIM6EN

Bit 4: Timer 6 clock enable.

Allowed values:
0: Disabled: The selected clock is disabled
1: Enabled: The selected clock is enabled

TIM7EN

Bit 5: Timer 7 clock enable.

Allowed values:
0: Disabled: The selected clock is disabled
1: Enabled: The selected clock is enabled

TIM12EN

Bit 6: Timer 12 clock enable.

Allowed values:
0: Disabled: The selected clock is disabled
1: Enabled: The selected clock is enabled

TIM13EN

Bit 7: Timer 13 clock enable.

Allowed values:
0: Disabled: The selected clock is disabled
1: Enabled: The selected clock is enabled

TIM14EN

Bit 8: Timer 14 clock enable.

Allowed values:
0: Disabled: The selected clock is disabled
1: Enabled: The selected clock is enabled

WWDGEN

Bit 11: Window watchdog clock enable.

Allowed values:
0: Disabled: The selected clock is disabled
1: Enabled: The selected clock is enabled

SPI2EN

Bit 14: SPI 2 clock enable.

Allowed values:
0: Disabled: The selected clock is disabled
1: Enabled: The selected clock is enabled

SPI3EN

Bit 15: SPI 3 clock enable.

Allowed values:
0: Disabled: The selected clock is disabled
1: Enabled: The selected clock is enabled

USART2EN

Bit 17: USART 2 clock enable.

Allowed values:
0: Disabled: The selected clock is disabled
1: Enabled: The selected clock is enabled

USART3EN

Bit 18: USART 3 clock enable.

Allowed values:
0: Disabled: The selected clock is disabled
1: Enabled: The selected clock is enabled

UART4EN

Bit 19: UART 4 clock enable.

Allowed values:
0: Disabled: The selected clock is disabled
1: Enabled: The selected clock is enabled

UART5EN

Bit 20: UART 5 clock enable.

Allowed values:
0: Disabled: The selected clock is disabled
1: Enabled: The selected clock is enabled

I2C1EN

Bit 21: I2C 1 clock enable.

Allowed values:
0: Disabled: The selected clock is disabled
1: Enabled: The selected clock is enabled

I2C2EN

Bit 22: I2C 2 clock enable.

Allowed values:
0: Disabled: The selected clock is disabled
1: Enabled: The selected clock is enabled

USBEN

Bit 23: USB clock enable.

Allowed values:
0: Disabled: The selected clock is disabled
1: Enabled: The selected clock is enabled

CANEN

Bit 25: CAN clock enable.

Allowed values:
0: Disabled: The selected clock is disabled
1: Enabled: The selected clock is enabled

BKPEN

Bit 27: Backup interface clock enable.

Allowed values:
0: Disabled: The selected clock is disabled
1: Enabled: The selected clock is enabled

PWREN

Bit 28: Power interface clock enable.

Allowed values:
0: Disabled: The selected clock is disabled
1: Enabled: The selected clock is enabled

DACEN

Bit 29: DAC interface clock enable.

Allowed values:
0: Disabled: The selected clock is disabled
1: Enabled: The selected clock is enabled

BDCR

Backup domain control register (RCC_BDCR)

Offset: 0x20, reset: 0x00000000, access: Unspecified

6/6 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
BDRST
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RTCEN
rw
RTCSEL
rw
LSEBYP
rw
LSERDY
r
LSEON
rw
Toggle Fields.

LSEON

Bit 0: External Low Speed oscillator enable.

Allowed values:
0: Off: LSE oscillator Off
1: On: LSE oscillator On

LSERDY

Bit 1: External Low Speed oscillator ready.

Allowed values:
0: NotReady: LSE oscillator not ready
1: Ready: LSE oscillator ready

LSEBYP

Bit 2: External Low Speed oscillator bypass.

Allowed values:
0: NotBypassed: LSE crystal oscillator not bypassed
1: Bypassed: LSE crystal oscillator bypassed with external clock

RTCSEL

Bits 8-9: RTC clock source selection.

Allowed values:
0: NoClock: No clock
1: LSE: LSE oscillator clock used as RTC clock
2: LSI: LSI oscillator clock used as RTC clock
3: HSE: HSE oscillator clock divided by a prescaler used as RTC clock

RTCEN

Bit 15: RTC clock enable.

Allowed values:
0: Disabled: RTC clock disabled
1: Enabled: RTC clock enabled

BDRST

Bit 16: Backup domain software reset.

Allowed values:
0: Disabled: Reset not activated
1: Enabled: Reset the entire RTC domain

CSR

Control/status register (RCC_CSR)

Offset: 0x24, reset: 0x0C000000, access: Unspecified

9/9 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LPWRRSTF
rw
WWDGRSTF
rw
IWDGRSTF
rw
SFTRSTF
rw
PORRSTF
rw
PINRSTF
rw
RMVF
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LSIRDY
r
LSION
rw
Toggle Fields.

LSION

Bit 0: Internal low speed oscillator enable.

Allowed values:
0: Off: LSI oscillator Off
1: On: LSI oscillator On

LSIRDY

Bit 1: Internal low speed oscillator ready.

Allowed values:
0: NotReady: LSI oscillator not ready
1: Ready: LSI oscillator ready

RMVF

Bit 24: Remove reset flag.

Allowed values:
1: Clear: Clears the reset flag

PINRSTF

Bit 26: PIN reset flag.

Allowed values:
0: NoReset: No reset has occured
1: Reset: A reset has occured

PORRSTF

Bit 27: POR/PDR reset flag.

Allowed values:
0: NoReset: No reset has occured
1: Reset: A reset has occured

SFTRSTF

Bit 28: Software reset flag.

Allowed values:
0: NoReset: No reset has occured
1: Reset: A reset has occured

IWDGRSTF

Bit 29: Independent watchdog reset flag.

Allowed values:
0: NoReset: No reset has occured
1: Reset: A reset has occured

WWDGRSTF

Bit 30: Window watchdog reset flag.

Allowed values:
0: NoReset: No reset has occured
1: Reset: A reset has occured

LPWRRSTF

Bit 31: Low-power reset flag.

Allowed values:
0: NoReset: No reset has occured
1: Reset: A reset has occured

RTC

0x40002800: Real time clock

17/17 fields covered. Toggle Registers.

CRH

RTC Control Register High

Offset: 0x0, reset: 0x00000000, access: read-write

3/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
OWIE
rw
ALRIE
rw
SECIE
rw
Toggle Fields.

SECIE

Bit 0: Second interrupt Enable.

Allowed values:
0: Disabled: Second interrupt is masked
1: Enabled: Second interrupt is enabled

ALRIE

Bit 1: Alarm interrupt Enable.

Allowed values:
0: Disabled: Alarm interrupt is masked
1: Enabled: Alarm interrupt is enabled

OWIE

Bit 2: Overflow interrupt Enable.

Allowed values:
0: Disabled: Overflow interrupt is masked
1: Enabled: Overflow interrupt is enabled

CRL

RTC Control Register Low

Offset: 0x4, reset: 0x00000020, access: Unspecified

6/6 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RTOFF
r
CNF
rw
RSF
rw
OWF
rw
ALRF
rw
SECF
rw
Toggle Fields.

SECF

Bit 0: Second Flag.

Allowed values:
0: NoPrescalerOverflow: Second flag condition not met
1: PrescalerOverflow: Second flag condition met

ALRF

Bit 1: Alarm Flag.

Allowed values:
0: NoAlarm: Alarm not detected
1: Alarm: Alarm detected

OWF

Bit 2: Overflow Flag.

Allowed values:
0: NoOverflow: Overflow not detected
1: Overflow: 32-bit programmable counter overflow occurred

RSF

Bit 3: Registers Synchronized Flag.

Allowed values:
0: NotSynchronized: Registers not yet synchronized
1: Synchronized: Registers synchronized

CNF

Bit 4: Configuration Flag.

Allowed values:
0: Exit: Exit configuration mode (start update of RTC registers)
1: Enter: Enter configuration mode

RTOFF

Bit 5: RTC operation OFF.

Allowed values:
0: Enabled: Last write operation on RTC registers is still ongoing
1: Disabled: Last write operation on RTC registers terminated

PRLH

RTC Prescaler Load Register High

Offset: 0x8, reset: 0x00000000, access: write-only

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PRLH
w
Toggle Fields.

PRLH

Bits 0-3: RTC Prescaler Load Register High.

Allowed values: 0-15

PRLL

RTC Prescaler Load Register Low

Offset: 0xC, reset: 0x8000, access: write-only

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PRLL
w
Toggle Fields.

PRLL

Bits 0-15: RTC Prescaler Divider Register Low.

Allowed values: 0-65535

DIVH

RTC Prescaler Divider Register High

Offset: 0x10, reset: 0x00000000, access: read-only

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DIVH
r
Toggle Fields.

DIVH

Bits 0-3: RTC prescaler divider register high.

Allowed values: 0-15

DIVL

RTC Prescaler Divider Register Low

Offset: 0x14, reset: 0x8000, access: read-only

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DIVL
r
Toggle Fields.

DIVL

Bits 0-15: RTC prescaler divider register Low.

Allowed values: 0-65535

CNTH

RTC Counter Register High

Offset: 0x18, reset: 0x00000000, access: read-write

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CNTH
rw
Toggle Fields.

CNTH

Bits 0-15: RTC counter register high.

Allowed values: 0-65535

CNTL

RTC Counter Register Low

Offset: 0x1C, reset: 0x00000000, access: read-write

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CNTL
rw
Toggle Fields.

CNTL

Bits 0-15: RTC counter register Low.

Allowed values: 0-65535

ALRH

RTC Alarm Register High

Offset: 0x20, reset: 0xFFFF, access: write-only

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ALRH
w
Toggle Fields.

ALRH

Bits 0-15: RTC alarm register high.

Allowed values: 0-65535

ALRL

RTC Alarm Register Low

Offset: 0x24, reset: 0xFFFF, access: write-only

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ALRL
w
Toggle Fields.

ALRL

Bits 0-15: RTC alarm register low.

Allowed values: 0-65535

SCB

0xE000ED00: System control block

5/74 fields covered. Toggle Registers.

CPUID

CPUID base register

Offset: 0x0, reset: 0x410FC241, access: read-only

5/5 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Implementer
r
Variant
r
Constant
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PartNo
r
Revision
r
Toggle Fields.

Revision

Bits 0-3: Revision number.

PartNo

Bits 4-15: Part number of the processor.

Constant

Bits 16-19: Reads as 0xF.

Variant

Bits 20-23: Variant number.

Implementer

Bits 24-31: Implementer code.

ICSR

Interrupt control and state register

Offset: 0x4, reset: 0x00000000, access: read-write

0/9 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
NMIPENDSET
rw
PENDSVSET
rw
PENDSVCLR
rw
PENDSTSET
rw
PENDSTCLR
rw
ISRPENDING
rw
VECTPENDING
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
VECTPENDING
rw
RETTOBASE
rw
VECTACTIVE
rw
Toggle Fields.

VECTACTIVE

Bits 0-8: Active vector.

RETTOBASE

Bit 11: Return to base level.

VECTPENDING

Bits 12-18: Pending vector.

ISRPENDING

Bit 22: Interrupt pending flag.

PENDSTCLR

Bit 25: SysTick exception clear-pending bit.

PENDSTSET

Bit 26: SysTick exception set-pending bit.

PENDSVCLR

Bit 27: PendSV clear-pending bit.

PENDSVSET

Bit 28: PendSV set-pending bit.

NMIPENDSET

Bit 31: NMI set-pending bit..

VTOR

Vector table offset register

Offset: 0x8, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
TBLOFF
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TBLOFF
rw
Toggle Fields.

TBLOFF

Bits 9-29: Vector table base offset field.

AIRCR

Application interrupt and reset control register

Offset: 0xC, reset: 0x00000000, access: read-write

0/6 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
VECTKEYSTAT
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ENDIANESS
rw
PRIGROUP
rw
SYSRESETREQ
rw
VECTCLRACTIVE
rw
VECTRESET
rw
Toggle Fields.

VECTRESET

Bit 0: VECTRESET.

VECTCLRACTIVE

Bit 1: VECTCLRACTIVE.

SYSRESETREQ

Bit 2: SYSRESETREQ.

PRIGROUP

Bits 8-10: PRIGROUP.

ENDIANESS

Bit 15: ENDIANESS.

VECTKEYSTAT

Bits 16-31: Register key.

SCR

System control register

Offset: 0x10, reset: 0x00000000, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SEVEONPEND
rw
SLEEPDEEP
rw
SLEEPONEXIT
rw
Toggle Fields.

SLEEPONEXIT

Bit 1: SLEEPONEXIT.

SLEEPDEEP

Bit 2: SLEEPDEEP.

SEVEONPEND

Bit 4: Send Event on Pending bit.

CCR

Configuration and control register

Offset: 0x14, reset: 0x00000000, access: read-write

0/6 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
STKALIGN
rw
BFHFNMIGN
rw
DIV_0_TRP
rw
UNALIGN__TRP
rw
USERSETMPEND
rw
NONBASETHRDENA
rw
Toggle Fields.

NONBASETHRDENA

Bit 0: Configures how the processor enters Thread mode.

USERSETMPEND

Bit 1: USERSETMPEND.

UNALIGN__TRP

Bit 3: UNALIGN_ TRP.

DIV_0_TRP

Bit 4: DIV_0_TRP.

BFHFNMIGN

Bit 8: BFHFNMIGN.

STKALIGN

Bit 9: STKALIGN.

SHPR1

System handler priority registers

Offset: 0x18, reset: 0x00000000, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
PRI_6
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PRI_5
rw
PRI_4
rw
Toggle Fields.

PRI_4

Bits 0-7: Priority of system handler 4.

PRI_5

Bits 8-15: Priority of system handler 5.

PRI_6

Bits 16-23: Priority of system handler 6.

SHPR2

System handler priority registers

Offset: 0x1C, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
PRI_11
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Toggle Fields.

PRI_11

Bits 24-31: Priority of system handler 11.

SHPR3

System handler priority registers

Offset: 0x20, reset: 0x00000000, access: read-write

0/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
PRI_15
rw
PRI_14
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Toggle Fields.

PRI_14

Bits 16-23: Priority of system handler 14.

PRI_15

Bits 24-31: Priority of system handler 15.

SHCRS

System handler control and state register

Offset: 0x24, reset: 0x00000000, access: read-write

0/14 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
USGFAULTENA
rw
BUSFAULTENA
rw
MEMFAULTENA
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SVCALLPENDED
rw
BUSFAULTPENDED
rw
MEMFAULTPENDED
rw
USGFAULTPENDED
rw
SYSTICKACT
rw
PENDSVACT
rw
MONITORACT
rw
SVCALLACT
rw
USGFAULTACT
rw
BUSFAULTACT
rw
MEMFAULTACT
rw
Toggle Fields.

MEMFAULTACT

Bit 0: Memory management fault exception active bit.

BUSFAULTACT

Bit 1: Bus fault exception active bit.

USGFAULTACT

Bit 3: Usage fault exception active bit.

SVCALLACT

Bit 7: SVC call active bit.

MONITORACT

Bit 8: Debug monitor active bit.

PENDSVACT

Bit 10: PendSV exception active bit.

SYSTICKACT

Bit 11: SysTick exception active bit.

USGFAULTPENDED

Bit 12: Usage fault exception pending bit.

MEMFAULTPENDED

Bit 13: Memory management fault exception pending bit.

BUSFAULTPENDED

Bit 14: Bus fault exception pending bit.

SVCALLPENDED

Bit 15: SVC call pending bit.

MEMFAULTENA

Bit 16: Memory management fault enable bit.

BUSFAULTENA

Bit 17: Bus fault enable bit.

USGFAULTENA

Bit 18: Usage fault enable bit.

CFSR_UFSR_BFSR_MMFSR

Configurable fault status register

Offset: 0x28, reset: 0x00000000, access: read-write

0/19 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DIVBYZERO
rw
UNALIGNED
rw
NOCP
rw
INVPC
rw
INVSTATE
rw
UNDEFINSTR
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
BFARVALID
rw
LSPERR
rw
STKERR
rw
UNSTKERR
rw
IMPRECISERR
rw
PRECISERR
rw
IBUSERR
rw
MMARVALID
rw
MLSPERR
rw
MSTKERR
rw
MUNSTKERR
rw
DACCVIOL
rw
IACCVIOL
rw
Toggle Fields.

IACCVIOL

Bit 0: IACCVIOL.

DACCVIOL

Bit 1: DACCVIOL.

MUNSTKERR

Bit 3: MUNSTKERR.

MSTKERR

Bit 4: MSTKERR.

MLSPERR

Bit 5: MLSPERR.

MMARVALID

Bit 7: MMARVALID.

IBUSERR

Bit 8: Instruction bus error.

PRECISERR

Bit 9: Precise data bus error.

IMPRECISERR

Bit 10: Imprecise data bus error.

UNSTKERR

Bit 11: Bus fault on unstacking for a return from exception.

STKERR

Bit 12: Bus fault on stacking for exception entry.

LSPERR

Bit 13: Bus fault on floating-point lazy state preservation.

BFARVALID

Bit 15: Bus Fault Address Register (BFAR) valid flag.

UNDEFINSTR

Bit 16: Undefined instruction usage fault.

INVSTATE

Bit 17: Invalid state usage fault.

INVPC

Bit 18: Invalid PC load usage fault.

NOCP

Bit 19: No coprocessor usage fault..

UNALIGNED

Bit 24: Unaligned access usage fault.

DIVBYZERO

Bit 25: Divide by zero usage fault.

HFSR

Hard fault status register

Offset: 0x2C, reset: 0x00000000, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DEBUG_VT
rw
FORCED
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
VECTTBL
rw
Toggle Fields.

VECTTBL

Bit 1: Vector table hard fault.

FORCED

Bit 30: Forced hard fault.

DEBUG_VT

Bit 31: Reserved for Debug use.

MMFAR

Memory management fault address register

Offset: 0x34, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
MMFAR
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MMFAR
rw
Toggle Fields.

MMFAR

Bits 0-31: Memory management fault address.

BFAR

Bus fault address register

Offset: 0x38, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
BFAR
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
BFAR
rw
Toggle Fields.

BFAR

Bits 0-31: Bus fault address.

SCB_ACTRL

0xE000E008: System control block ACTLR

0/4 fields covered. Toggle Registers.

ACTRL

Auxiliary control register

Offset: 0x0, reset: 0x00000000, access: read-write

0/4 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DISITMATBFLUSH
rw
DISRAMODE
rw
FPEXCODIS
rw
DISFOLD
rw
Toggle Fields.

DISFOLD

Bit 2: DISFOLD.

FPEXCODIS

Bit 10: FPEXCODIS.

DISRAMODE

Bit 11: DISRAMODE.

DISITMATBFLUSH

Bit 12: DISITMATBFLUSH.

SDIO

0x40018000: Secure digital input/output interface

29/96 fields covered. Toggle Registers.

POWER

Bits 1:0 = PWRCTRL: Power supply control bits

Offset: 0x0, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PWRCTRL
rw
Toggle Fields.

PWRCTRL

Bits 0-1: PWRCTRL.

CLKCR

SDI clock control register (SDIO_CLKCR)

Offset: 0x4, reset: 0x00000000, access: read-write

0/7 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
HWFC_EN
rw
NEGEDGE
rw
WIDBUS
rw
BYPASS
rw
PWRSAV
rw
CLKEN
rw
CLKDIV
rw
Toggle Fields.

CLKDIV

Bits 0-7: Clock divide factor.

CLKEN

Bit 8: Clock enable bit.

PWRSAV

Bit 9: Power saving configuration bit.

BYPASS

Bit 10: Clock divider bypass enable bit.

WIDBUS

Bits 11-12: Wide bus mode enable bit.

NEGEDGE

Bit 13: SDIO_CK dephasing selection bit.

HWFC_EN

Bit 14: HW Flow Control enable.

ARG

Bits 31:0 = : Command argument

Offset: 0x8, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CMDARG
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CMDARG
rw
Toggle Fields.

CMDARG

Bits 0-31: Command argument.

CMD

SDIO command register (SDIO_CMD)

Offset: 0xC, reset: 0x00000000, access: read-write

0/9 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CE_ATACMD
rw
nIEN
rw
ENCMDcompl
rw
SDIOSuspend
rw
CPSMEN
rw
WAITPEND
rw
WAITINT
rw
WAITRESP
rw
CMDINDEX
rw
Toggle Fields.

CMDINDEX

Bits 0-5: CMDINDEX.

WAITRESP

Bits 6-7: WAITRESP.

WAITINT

Bit 8: WAITINT.

WAITPEND

Bit 9: WAITPEND.

CPSMEN

Bit 10: CPSMEN.

SDIOSuspend

Bit 11: SDIOSuspend.

ENCMDcompl

Bit 12: ENCMDcompl.

nIEN

Bit 13: nIEN.

CE_ATACMD

Bit 14: CE_ATACMD.

RESPCMD

SDIO command register

Offset: 0x10, reset: 0x00000000, access: read-only

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RESPCMD
r
Toggle Fields.

RESPCMD

Bits 0-5: RESPCMD.

RESPI1

Bits 31:0 = CARDSTATUS1

Offset: 0x14, reset: 0x00000000, access: read-only

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CARDSTATUS1
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CARDSTATUS1
r
Toggle Fields.

CARDSTATUS1

Bits 0-31: CARDSTATUS1.

RESP%s

Bits 31:0 = CARDSTATUS2

Offset: 0x18, reset: 0x00000000, access: read-only

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CARDSTATUS2
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CARDSTATUS2
r
Toggle Fields.

CARDSTATUS2

Bits 0-31: CARDSTATUS2.

DTIMER

Bits 31:0 = DATATIME: Data timeout period

Offset: 0x24, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DATATIME
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DATATIME
rw
Toggle Fields.

DATATIME

Bits 0-31: Data timeout period.

DLEN

Bits 24:0 = DATALENGTH: Data length value

Offset: 0x28, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DATALENGTH
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DATALENGTH
rw
Toggle Fields.

DATALENGTH

Bits 0-24: Data length value.

DCTRL

SDIO data control register (SDIO_DCTRL)

Offset: 0x2C, reset: 0x00000000, access: read-write

0/9 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SDIOEN
rw
RWMOD
rw
PWSTOP
rw
PWSTART
rw
DBLOCKSIZE
rw
DMAEN
rw
DTMODE
rw
DTDIR
rw
DTEN
rw
Toggle Fields.

DTEN

Bit 0: DTEN.

DTDIR

Bit 1: DTDIR.

DTMODE

Bit 2: DTMODE.

DMAEN

Bit 3: DMAEN.

DBLOCKSIZE

Bits 4-7: DBLOCKSIZE.

PWSTART

Bit 8: PWSTART.

PWSTOP

Bit 9: PWSTOP.

RWMOD

Bit 10: RWMOD.

SDIOEN

Bit 11: SDIOEN.

DCOUNT

Bits 24:0 = DATACOUNT: Data count value

Offset: 0x30, reset: 0x00000000, access: read-only

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DATACOUNT
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DATACOUNT
r
Toggle Fields.

DATACOUNT

Bits 0-24: Data count value.

STA

SDIO status register (SDIO_STA)

Offset: 0x34, reset: 0x00000000, access: read-only

24/24 fields covered.

CCRCFAIL

Bit 0: CCRCFAIL.

DCRCFAIL

Bit 1: DCRCFAIL.

CTIMEOUT

Bit 2: CTIMEOUT.

DTIMEOUT

Bit 3: DTIMEOUT.

TXUNDERR

Bit 4: TXUNDERR.

RXOVERR

Bit 5: RXOVERR.

CMDREND

Bit 6: CMDREND.

CMDSENT

Bit 7: CMDSENT.

DATAEND

Bit 8: DATAEND.

STBITERR

Bit 9: STBITERR.

DBCKEND

Bit 10: DBCKEND.

CMDACT

Bit 11: CMDACT.

TXACT

Bit 12: TXACT.

RXACT

Bit 13: RXACT.

TXFIFOHE

Bit 14: TXFIFOHE.

RXFIFOHF

Bit 15: RXFIFOHF.

TXFIFOF

Bit 16: TXFIFOF.

RXFIFOF

Bit 17: RXFIFOF.

TXFIFOE

Bit 18: TXFIFOE.

RXFIFOE

Bit 19: RXFIFOE.

TXDAVL

Bit 20: TXDAVL.

RXDAVL

Bit 21: RXDAVL.

SDIOIT

Bit 22: SDIOIT.

CEATAEND

Bit 23: CEATAEND.

ICR

SDIO interrupt clear register (SDIO_ICR)

Offset: 0x38, reset: 0x00000000, access: read-write

0/13 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CEATAENDC
rw
SDIOITC
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DBCKENDC
rw
STBITERRC
rw
DATAENDC
rw
CMDSENTC
rw
CMDRENDC
rw
RXOVERRC
rw
TXUNDERRC
rw
DTIMEOUTC
rw
CTIMEOUTC
rw
DCRCFAILC
rw
CCRCFAILC
rw
Toggle Fields.

CCRCFAILC

Bit 0: CCRCFAILC.

DCRCFAILC

Bit 1: DCRCFAILC.

CTIMEOUTC

Bit 2: CTIMEOUTC.

DTIMEOUTC

Bit 3: DTIMEOUTC.

TXUNDERRC

Bit 4: TXUNDERRC.

RXOVERRC

Bit 5: RXOVERRC.

CMDRENDC

Bit 6: CMDRENDC.

CMDSENTC

Bit 7: CMDSENTC.

DATAENDC

Bit 8: DATAENDC.

STBITERRC

Bit 9: STBITERRC.

DBCKENDC

Bit 10: DBCKENDC.

SDIOITC

Bit 22: SDIOITC.

CEATAENDC

Bit 23: CEATAENDC.

MASK

SDIO mask register (SDIO_MASK)

Offset: 0x3C, reset: 0x00000000, access: read-write

0/24 fields covered.

CCRCFAILIE

Bit 0: CCRCFAILIE.

DCRCFAILIE

Bit 1: DCRCFAILIE.

CTIMEOUTIE

Bit 2: CTIMEOUTIE.

DTIMEOUTIE

Bit 3: DTIMEOUTIE.

TXUNDERRIE

Bit 4: TXUNDERRIE.

RXOVERRIE

Bit 5: RXOVERRIE.

CMDRENDIE

Bit 6: CMDRENDIE.

CMDSENTIE

Bit 7: CMDSENTIE.

DATAENDIE

Bit 8: DATAENDIE.

STBITERRIE

Bit 9: STBITERRIE.

DBACKENDIE

Bit 10: DBACKENDIE.

CMDACTIE

Bit 11: CMDACTIE.

TXACTIE

Bit 12: TXACTIE.

RXACTIE

Bit 13: RXACTIE.

TXFIFOHEIE

Bit 14: TXFIFOHEIE.

RXFIFOHFIE

Bit 15: RXFIFOHFIE.

TXFIFOFIE

Bit 16: TXFIFOFIE.

RXFIFOFIE

Bit 17: RXFIFOFIE.

TXFIFOEIE

Bit 18: TXFIFOEIE.

RXFIFOEIE

Bit 19: RXFIFOEIE.

TXDAVLIE

Bit 20: TXDAVLIE.

RXDAVLIE

Bit 21: RXDAVLIE.

SDIOITIE

Bit 22: SDIOITIE.

CEATENDIE

Bit 23: CEATENDIE.

FIFOCNT

Bits 23:0 = FIFOCOUNT: Remaining number of words to be written to or read from the FIFO

Offset: 0x48, reset: 0x00000000, access: read-only

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
FIF0COUNT
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FIF0COUNT
r
Toggle Fields.

FIF0COUNT

Bits 0-23: FIF0COUNT.

FIFO

bits 31:0 = FIFOData: Receive and transmit FIFO data

Offset: 0x80, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
FIFOData
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FIFOData
rw
Toggle Fields.

FIFOData

Bits 0-31: FIFOData.

SPI1

0x40013000: Serial peripheral interface

43/43 fields covered. Toggle Registers.

CR1

control register 1

Offset: 0x0, reset: 0x0000, access: read-write

14/14 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
BIDIMODE
rw
BIDIOE
rw
CRCEN
rw
CRCNEXT
rw
DFF
rw
RXONLY
rw
SSM
rw
SSI
rw
LSBFIRST
rw
SPE
rw
BR
rw
MSTR
rw
CPOL
rw
CPHA
rw
Toggle Fields.

CPHA

Bit 0: Clock phase.

Allowed values:
0: FirstEdge: The first clock transition is the first data capture edge
1: SecondEdge: The second clock transition is the first data capture edge

CPOL

Bit 1: Clock polarity.

Allowed values:
0: IdleLow: CK to 0 when idle
1: IdleHigh: CK to 1 when idle

MSTR

Bit 2: Master selection.

Allowed values:
0: Slave: Slave configuration
1: Master: Master configuration

BR

Bits 3-5: Baud rate control.

Allowed values:
0: Div2: f_PCLK / 2
1: Div4: f_PCLK / 4
2: Div8: f_PCLK / 8
3: Div16: f_PCLK / 16
4: Div32: f_PCLK / 32
5: Div64: f_PCLK / 64
6: Div128: f_PCLK / 128
7: Div256: f_PCLK / 256

SPE

Bit 6: SPI enable.

Allowed values:
0: Disabled: Peripheral disabled
1: Enabled: Peripheral enabled

LSBFIRST

Bit 7: Frame format.

Allowed values:
0: MSBFirst: Data is transmitted/received with the MSB first
1: LSBFirst: Data is transmitted/received with the LSB first

SSI

Bit 8: Internal slave select.

Allowed values:
0: SlaveSelected: 0 is forced onto the NSS pin and the I/O value of the NSS pin is ignored
1: SlaveNotSelected: 1 is forced onto the NSS pin and the I/O value of the NSS pin is ignored

SSM

Bit 9: Software slave management.

Allowed values:
0: Disabled: Software slave management disabled
1: Enabled: Software slave management enabled

RXONLY

Bit 10: Receive only.

Allowed values:
0: FullDuplex: Full duplex (Transmit and receive)
1: OutputDisabled: Output disabled (Receive-only mode)

DFF

Bit 11: Data frame format.

Allowed values:
0: EightBit: 8-bit data frame format is selected for transmission/reception
1: SixteenBit: 16-bit data frame format is selected for transmission/reception

CRCNEXT

Bit 12: CRC transfer next.

Allowed values:
0: TxBuffer: Next transmit value is from Tx buffer
1: CRC: Next transmit value is from Tx CRC register

CRCEN

Bit 13: Hardware CRC calculation enable.

Allowed values:
0: Disabled: CRC calculation disabled
1: Enabled: CRC calculation enabled

BIDIOE

Bit 14: Output enable in bidirectional mode.

Allowed values:
0: OutputDisabled: Output disabled (receive-only mode)
1: OutputEnabled: Output enabled (transmit-only mode)

BIDIMODE

Bit 15: Bidirectional data mode enable.

Allowed values:
0: Unidirectional: 2-line unidirectional data mode selected
1: Bidirectional: 1-line bidirectional data mode selected

CR2

control register 2

Offset: 0x4, reset: 0x0000, access: read-write

6/6 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TXEIE
rw
RXNEIE
rw
ERRIE
rw
SSOE
rw
TXDMAEN
rw
RXDMAEN
rw
Toggle Fields.

RXDMAEN

Bit 0: Rx buffer DMA enable.

Allowed values:
0: Disabled: Rx buffer DMA disabled
1: Enabled: Rx buffer DMA enabled

TXDMAEN

Bit 1: Tx buffer DMA enable.

Allowed values:
0: Disabled: Tx buffer DMA disabled
1: Enabled: Tx buffer DMA enabled

SSOE

Bit 2: SS output enable.

Allowed values:
0: Disabled: SS output is disabled in master mode
1: Enabled: SS output is enabled in master mode

ERRIE

Bit 5: Error interrupt enable.

Allowed values:
0: Masked: Error interrupt masked
1: NotMasked: Error interrupt not masked

RXNEIE

Bit 6: RX buffer not empty interrupt enable.

Allowed values:
0: Masked: RXE interrupt masked
1: NotMasked: RXE interrupt not masked

TXEIE

Bit 7: Tx buffer empty interrupt enable.

Allowed values:
0: Masked: TXE interrupt masked
1: NotMasked: TXE interrupt not masked

SR

status register

Offset: 0x8, reset: 0x0002, access: Unspecified

8/8 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
BSY
r
OVR
r
MODF
r
CRCERR
rw
UDR
r
CHSIDE
r
TXE
r
RXNE
r
Toggle Fields.

RXNE

Bit 0: Receive buffer not empty.

Allowed values:
0: Empty: Rx buffer empty
1: NotEmpty: Rx buffer not empty

TXE

Bit 1: Transmit buffer empty.

Allowed values:
0: NotEmpty: Tx buffer not empty
1: Empty: Tx buffer empty

CHSIDE

Bit 2: Channel side.

Allowed values:
0: Left: Channel left has to be transmitted or has been received
1: Right: Channel right has to be transmitted or has been received

UDR

Bit 3: Underrun flag.

Allowed values:
0: NoUnderrun: No underrun occurred
1: Underrun: Underrun occurred

CRCERR

Bit 4: CRC error flag.

Allowed values:
0: Match: CRC value received matches the SPIx_RXCRCR value
1: NoMatch: CRC value received does not match the SPIx_RXCRCR value

MODF

Bit 5: Mode fault.

Allowed values:
0: NoFault: No mode fault occurred
1: Fault: Mode fault occurred

OVR

Bit 6: Overrun flag.

Allowed values:
0: NoOverrun: No overrun occurred
1: Overrun: Overrun occurred

BSY

Bit 7: Busy flag.

Allowed values:
0: NotBusy: SPI not busy
1: Busy: SPI busy

DR

data register

Offset: 0xC, reset: 0x0000, access: read-write

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DR
rw
Toggle Fields.

DR

Bits 0-15: Data register.

Allowed values: 0-65535

CRCPR

CRC polynomial register

Offset: 0x10, reset: 0x0007, access: read-write

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CRCPOLY
rw
Toggle Fields.

CRCPOLY

Bits 0-15: CRC polynomial register.

Allowed values: 0-65535

RXCRCR

RX CRC register

Offset: 0x14, reset: 0x0000, access: read-only

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RxCRC
r
Toggle Fields.

RxCRC

Bits 0-15: Rx CRC register.

Allowed values: 0-65535

TXCRCR

TX CRC register

Offset: 0x18, reset: 0x0000, access: read-only

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TxCRC
r
Toggle Fields.

TxCRC

Bits 0-15: Tx CRC register.

Allowed values: 0-65535

I2SCFGR

I2S configuration register

Offset: 0x1C, reset: 0x0000, access: read-write

8/8 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
I2SMOD
rw
I2SE
rw
I2SCFG
rw
PCMSYNC
rw
I2SSTD
rw
CKPOL
rw
DATLEN
rw
CHLEN
rw
Toggle Fields.

CHLEN

Bit 0: Channel length (number of bits per audio channel).

Allowed values:
0: SixteenBit: 16-bit wide
1: ThirtyTwoBit: 32-bit wide

DATLEN

Bits 1-2: Data length to be transferred.

Allowed values:
0: SixteenBit: 16-bit data length
1: TwentyFourBit: 24-bit data length
2: ThirtyTwoBit: 32-bit data length

CKPOL

Bit 3: Steady state clock polarity.

Allowed values:
0: IdleLow: I2S clock inactive state is low level
1: IdleHigh: I2S clock inactive state is high level

I2SSTD

Bits 4-5: I2S standard selection.

Allowed values:
0: Philips: I2S Philips standard
1: MSB: MSB justified standard
2: LSB: LSB justified standard
3: PCM: PCM standard

PCMSYNC

Bit 7: PCM frame synchronization.

Allowed values:
0: Short: Short frame synchronisation
1: Long: Long frame synchronisation

I2SCFG

Bits 8-9: I2S configuration mode.

Allowed values:
0: SlaveTx: Slave - transmit
1: SlaveRx: Slave - receive
2: MasterTx: Master - transmit
3: MasterRx: Master - receive

I2SE

Bit 10: I2S Enable.

Allowed values:
0: Disabled: I2S peripheral is disabled
1: Enabled: I2S peripheral is enabled

I2SMOD

Bit 11: I2S mode selection.

Allowed values:
0: SPIMode: SPI mode is selected
1: I2SMode: I2S mode is selected

I2SPR

I2S prescaler register

Offset: 0x20, reset: 00000010, access: read-write

3/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MCKOE
rw
ODD
rw
I2SDIV
rw
Toggle Fields.

I2SDIV

Bits 0-7: I2S Linear prescaler.

Allowed values: 2-255

ODD

Bit 8: Odd factor for the prescaler.

Allowed values:
0: Even: Real divider value is I2SDIV * 2
1: Odd: Real divider value is (I2SDIV * 2) + 1

MCKOE

Bit 9: Master clock output enable.

Allowed values:
0: Disabled: Master clock output is disabled
1: Enabled: Master clock output is enabled

SPI2

0x40003800: Serial peripheral interface

43/43 fields covered. Toggle Registers.

CR1

control register 1

Offset: 0x0, reset: 0x0000, access: read-write

14/14 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
BIDIMODE
rw
BIDIOE
rw
CRCEN
rw
CRCNEXT
rw
DFF
rw
RXONLY
rw
SSM
rw
SSI
rw
LSBFIRST
rw
SPE
rw
BR
rw
MSTR
rw
CPOL
rw
CPHA
rw
Toggle Fields.

CPHA

Bit 0: Clock phase.

Allowed values:
0: FirstEdge: The first clock transition is the first data capture edge
1: SecondEdge: The second clock transition is the first data capture edge

CPOL

Bit 1: Clock polarity.

Allowed values:
0: IdleLow: CK to 0 when idle
1: IdleHigh: CK to 1 when idle

MSTR

Bit 2: Master selection.

Allowed values:
0: Slave: Slave configuration
1: Master: Master configuration

BR

Bits 3-5: Baud rate control.

Allowed values:
0: Div2: f_PCLK / 2
1: Div4: f_PCLK / 4
2: Div8: f_PCLK / 8
3: Div16: f_PCLK / 16
4: Div32: f_PCLK / 32
5: Div64: f_PCLK / 64
6: Div128: f_PCLK / 128
7: Div256: f_PCLK / 256

SPE

Bit 6: SPI enable.

Allowed values:
0: Disabled: Peripheral disabled
1: Enabled: Peripheral enabled

LSBFIRST

Bit 7: Frame format.

Allowed values:
0: MSBFirst: Data is transmitted/received with the MSB first
1: LSBFirst: Data is transmitted/received with the LSB first

SSI

Bit 8: Internal slave select.

Allowed values:
0: SlaveSelected: 0 is forced onto the NSS pin and the I/O value of the NSS pin is ignored
1: SlaveNotSelected: 1 is forced onto the NSS pin and the I/O value of the NSS pin is ignored

SSM

Bit 9: Software slave management.

Allowed values:
0: Disabled: Software slave management disabled
1: Enabled: Software slave management enabled

RXONLY

Bit 10: Receive only.

Allowed values:
0: FullDuplex: Full duplex (Transmit and receive)
1: OutputDisabled: Output disabled (Receive-only mode)

DFF

Bit 11: Data frame format.

Allowed values:
0: EightBit: 8-bit data frame format is selected for transmission/reception
1: SixteenBit: 16-bit data frame format is selected for transmission/reception

CRCNEXT

Bit 12: CRC transfer next.

Allowed values:
0: TxBuffer: Next transmit value is from Tx buffer
1: CRC: Next transmit value is from Tx CRC register

CRCEN

Bit 13: Hardware CRC calculation enable.

Allowed values:
0: Disabled: CRC calculation disabled
1: Enabled: CRC calculation enabled

BIDIOE

Bit 14: Output enable in bidirectional mode.

Allowed values:
0: OutputDisabled: Output disabled (receive-only mode)
1: OutputEnabled: Output enabled (transmit-only mode)

BIDIMODE

Bit 15: Bidirectional data mode enable.

Allowed values:
0: Unidirectional: 2-line unidirectional data mode selected
1: Bidirectional: 1-line bidirectional data mode selected

CR2

control register 2

Offset: 0x4, reset: 0x0000, access: read-write

6/6 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TXEIE
rw
RXNEIE
rw
ERRIE
rw
SSOE
rw
TXDMAEN
rw
RXDMAEN
rw
Toggle Fields.

RXDMAEN

Bit 0: Rx buffer DMA enable.

Allowed values:
0: Disabled: Rx buffer DMA disabled
1: Enabled: Rx buffer DMA enabled

TXDMAEN

Bit 1: Tx buffer DMA enable.

Allowed values:
0: Disabled: Tx buffer DMA disabled
1: Enabled: Tx buffer DMA enabled

SSOE

Bit 2: SS output enable.

Allowed values:
0: Disabled: SS output is disabled in master mode
1: Enabled: SS output is enabled in master mode

ERRIE

Bit 5: Error interrupt enable.

Allowed values:
0: Masked: Error interrupt masked
1: NotMasked: Error interrupt not masked

RXNEIE

Bit 6: RX buffer not empty interrupt enable.

Allowed values:
0: Masked: RXE interrupt masked
1: NotMasked: RXE interrupt not masked

TXEIE

Bit 7: Tx buffer empty interrupt enable.

Allowed values:
0: Masked: TXE interrupt masked
1: NotMasked: TXE interrupt not masked

SR

status register

Offset: 0x8, reset: 0x0002, access: Unspecified

8/8 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
BSY
r
OVR
r
MODF
r
CRCERR
rw
UDR
r
CHSIDE
r
TXE
r
RXNE
r
Toggle Fields.

RXNE

Bit 0: Receive buffer not empty.

Allowed values:
0: Empty: Rx buffer empty
1: NotEmpty: Rx buffer not empty

TXE

Bit 1: Transmit buffer empty.

Allowed values:
0: NotEmpty: Tx buffer not empty
1: Empty: Tx buffer empty

CHSIDE

Bit 2: Channel side.

Allowed values:
0: Left: Channel left has to be transmitted or has been received
1: Right: Channel right has to be transmitted or has been received

UDR

Bit 3: Underrun flag.

Allowed values:
0: NoUnderrun: No underrun occurred
1: Underrun: Underrun occurred

CRCERR

Bit 4: CRC error flag.

Allowed values:
0: Match: CRC value received matches the SPIx_RXCRCR value
1: NoMatch: CRC value received does not match the SPIx_RXCRCR value

MODF

Bit 5: Mode fault.

Allowed values:
0: NoFault: No mode fault occurred
1: Fault: Mode fault occurred

OVR

Bit 6: Overrun flag.

Allowed values:
0: NoOverrun: No overrun occurred
1: Overrun: Overrun occurred

BSY

Bit 7: Busy flag.

Allowed values:
0: NotBusy: SPI not busy
1: Busy: SPI busy

DR

data register

Offset: 0xC, reset: 0x0000, access: read-write

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DR
rw
Toggle Fields.

DR

Bits 0-15: Data register.

Allowed values: 0-65535

CRCPR

CRC polynomial register

Offset: 0x10, reset: 0x0007, access: read-write

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CRCPOLY
rw
Toggle Fields.

CRCPOLY

Bits 0-15: CRC polynomial register.

Allowed values: 0-65535

RXCRCR

RX CRC register

Offset: 0x14, reset: 0x0000, access: read-only

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RxCRC
r
Toggle Fields.

RxCRC

Bits 0-15: Rx CRC register.

Allowed values: 0-65535

TXCRCR

TX CRC register

Offset: 0x18, reset: 0x0000, access: read-only

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TxCRC
r
Toggle Fields.

TxCRC

Bits 0-15: Tx CRC register.

Allowed values: 0-65535

I2SCFGR

I2S configuration register

Offset: 0x1C, reset: 0x0000, access: read-write

8/8 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
I2SMOD
rw
I2SE
rw
I2SCFG
rw
PCMSYNC
rw
I2SSTD
rw
CKPOL
rw
DATLEN
rw
CHLEN
rw
Toggle Fields.

CHLEN

Bit 0: Channel length (number of bits per audio channel).

Allowed values:
0: SixteenBit: 16-bit wide
1: ThirtyTwoBit: 32-bit wide

DATLEN

Bits 1-2: Data length to be transferred.

Allowed values:
0: SixteenBit: 16-bit data length
1: TwentyFourBit: 24-bit data length
2: ThirtyTwoBit: 32-bit data length

CKPOL

Bit 3: Steady state clock polarity.

Allowed values:
0: IdleLow: I2S clock inactive state is low level
1: IdleHigh: I2S clock inactive state is high level

I2SSTD

Bits 4-5: I2S standard selection.

Allowed values:
0: Philips: I2S Philips standard
1: MSB: MSB justified standard
2: LSB: LSB justified standard
3: PCM: PCM standard

PCMSYNC

Bit 7: PCM frame synchronization.

Allowed values:
0: Short: Short frame synchronisation
1: Long: Long frame synchronisation

I2SCFG

Bits 8-9: I2S configuration mode.

Allowed values:
0: SlaveTx: Slave - transmit
1: SlaveRx: Slave - receive
2: MasterTx: Master - transmit
3: MasterRx: Master - receive

I2SE

Bit 10: I2S Enable.

Allowed values:
0: Disabled: I2S peripheral is disabled
1: Enabled: I2S peripheral is enabled

I2SMOD

Bit 11: I2S mode selection.

Allowed values:
0: SPIMode: SPI mode is selected
1: I2SMode: I2S mode is selected

I2SPR

I2S prescaler register

Offset: 0x20, reset: 00000010, access: read-write

3/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MCKOE
rw
ODD
rw
I2SDIV
rw
Toggle Fields.

I2SDIV

Bits 0-7: I2S Linear prescaler.

Allowed values: 2-255

ODD

Bit 8: Odd factor for the prescaler.

Allowed values:
0: Even: Real divider value is I2SDIV * 2
1: Odd: Real divider value is (I2SDIV * 2) + 1

MCKOE

Bit 9: Master clock output enable.

Allowed values:
0: Disabled: Master clock output is disabled
1: Enabled: Master clock output is enabled

SPI3

0x40003C00: Serial peripheral interface

43/43 fields covered. Toggle Registers.

CR1

control register 1

Offset: 0x0, reset: 0x0000, access: read-write

14/14 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
BIDIMODE
rw
BIDIOE
rw
CRCEN
rw
CRCNEXT
rw
DFF
rw
RXONLY
rw
SSM
rw
SSI
rw
LSBFIRST
rw
SPE
rw
BR
rw
MSTR
rw
CPOL
rw
CPHA
rw
Toggle Fields.

CPHA

Bit 0: Clock phase.

Allowed values:
0: FirstEdge: The first clock transition is the first data capture edge
1: SecondEdge: The second clock transition is the first data capture edge

CPOL

Bit 1: Clock polarity.

Allowed values:
0: IdleLow: CK to 0 when idle
1: IdleHigh: CK to 1 when idle

MSTR

Bit 2: Master selection.

Allowed values:
0: Slave: Slave configuration
1: Master: Master configuration

BR

Bits 3-5: Baud rate control.

Allowed values:
0: Div2: f_PCLK / 2
1: Div4: f_PCLK / 4
2: Div8: f_PCLK / 8
3: Div16: f_PCLK / 16
4: Div32: f_PCLK / 32
5: Div64: f_PCLK / 64
6: Div128: f_PCLK / 128
7: Div256: f_PCLK / 256

SPE

Bit 6: SPI enable.

Allowed values:
0: Disabled: Peripheral disabled
1: Enabled: Peripheral enabled

LSBFIRST

Bit 7: Frame format.

Allowed values:
0: MSBFirst: Data is transmitted/received with the MSB first
1: LSBFirst: Data is transmitted/received with the LSB first

SSI

Bit 8: Internal slave select.

Allowed values:
0: SlaveSelected: 0 is forced onto the NSS pin and the I/O value of the NSS pin is ignored
1: SlaveNotSelected: 1 is forced onto the NSS pin and the I/O value of the NSS pin is ignored

SSM

Bit 9: Software slave management.

Allowed values:
0: Disabled: Software slave management disabled
1: Enabled: Software slave management enabled

RXONLY

Bit 10: Receive only.

Allowed values:
0: FullDuplex: Full duplex (Transmit and receive)
1: OutputDisabled: Output disabled (Receive-only mode)

DFF

Bit 11: Data frame format.

Allowed values:
0: EightBit: 8-bit data frame format is selected for transmission/reception
1: SixteenBit: 16-bit data frame format is selected for transmission/reception

CRCNEXT

Bit 12: CRC transfer next.

Allowed values:
0: TxBuffer: Next transmit value is from Tx buffer
1: CRC: Next transmit value is from Tx CRC register

CRCEN

Bit 13: Hardware CRC calculation enable.

Allowed values:
0: Disabled: CRC calculation disabled
1: Enabled: CRC calculation enabled

BIDIOE

Bit 14: Output enable in bidirectional mode.

Allowed values:
0: OutputDisabled: Output disabled (receive-only mode)
1: OutputEnabled: Output enabled (transmit-only mode)

BIDIMODE

Bit 15: Bidirectional data mode enable.

Allowed values:
0: Unidirectional: 2-line unidirectional data mode selected
1: Bidirectional: 1-line bidirectional data mode selected

CR2

control register 2

Offset: 0x4, reset: 0x0000, access: read-write

6/6 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TXEIE
rw
RXNEIE
rw
ERRIE
rw
SSOE
rw
TXDMAEN
rw
RXDMAEN
rw
Toggle Fields.

RXDMAEN

Bit 0: Rx buffer DMA enable.

Allowed values:
0: Disabled: Rx buffer DMA disabled
1: Enabled: Rx buffer DMA enabled

TXDMAEN

Bit 1: Tx buffer DMA enable.

Allowed values:
0: Disabled: Tx buffer DMA disabled
1: Enabled: Tx buffer DMA enabled

SSOE

Bit 2: SS output enable.

Allowed values:
0: Disabled: SS output is disabled in master mode
1: Enabled: SS output is enabled in master mode

ERRIE

Bit 5: Error interrupt enable.

Allowed values:
0: Masked: Error interrupt masked
1: NotMasked: Error interrupt not masked

RXNEIE

Bit 6: RX buffer not empty interrupt enable.

Allowed values:
0: Masked: RXE interrupt masked
1: NotMasked: RXE interrupt not masked

TXEIE

Bit 7: Tx buffer empty interrupt enable.

Allowed values:
0: Masked: TXE interrupt masked
1: NotMasked: TXE interrupt not masked

SR

status register

Offset: 0x8, reset: 0x0002, access: Unspecified

8/8 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
BSY
r
OVR
r
MODF
r
CRCERR
rw
UDR
r
CHSIDE
r
TXE
r
RXNE
r
Toggle Fields.

RXNE

Bit 0: Receive buffer not empty.

Allowed values:
0: Empty: Rx buffer empty
1: NotEmpty: Rx buffer not empty

TXE

Bit 1: Transmit buffer empty.

Allowed values:
0: NotEmpty: Tx buffer not empty
1: Empty: Tx buffer empty

CHSIDE

Bit 2: Channel side.

Allowed values:
0: Left: Channel left has to be transmitted or has been received
1: Right: Channel right has to be transmitted or has been received

UDR

Bit 3: Underrun flag.

Allowed values:
0: NoUnderrun: No underrun occurred
1: Underrun: Underrun occurred

CRCERR

Bit 4: CRC error flag.

Allowed values:
0: Match: CRC value received matches the SPIx_RXCRCR value
1: NoMatch: CRC value received does not match the SPIx_RXCRCR value

MODF

Bit 5: Mode fault.

Allowed values:
0: NoFault: No mode fault occurred
1: Fault: Mode fault occurred

OVR

Bit 6: Overrun flag.

Allowed values:
0: NoOverrun: No overrun occurred
1: Overrun: Overrun occurred

BSY

Bit 7: Busy flag.

Allowed values:
0: NotBusy: SPI not busy
1: Busy: SPI busy

DR

data register

Offset: 0xC, reset: 0x0000, access: read-write

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DR
rw
Toggle Fields.

DR

Bits 0-15: Data register.

Allowed values: 0-65535

CRCPR

CRC polynomial register

Offset: 0x10, reset: 0x0007, access: read-write

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CRCPOLY
rw
Toggle Fields.

CRCPOLY

Bits 0-15: CRC polynomial register.

Allowed values: 0-65535

RXCRCR

RX CRC register

Offset: 0x14, reset: 0x0000, access: read-only

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RxCRC
r
Toggle Fields.

RxCRC

Bits 0-15: Rx CRC register.

Allowed values: 0-65535

TXCRCR

TX CRC register

Offset: 0x18, reset: 0x0000, access: read-only

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TxCRC
r
Toggle Fields.

TxCRC

Bits 0-15: Tx CRC register.

Allowed values: 0-65535

I2SCFGR

I2S configuration register

Offset: 0x1C, reset: 0x0000, access: read-write

8/8 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
I2SMOD
rw
I2SE
rw
I2SCFG
rw
PCMSYNC
rw
I2SSTD
rw
CKPOL
rw
DATLEN
rw
CHLEN
rw
Toggle Fields.

CHLEN

Bit 0: Channel length (number of bits per audio channel).

Allowed values:
0: SixteenBit: 16-bit wide
1: ThirtyTwoBit: 32-bit wide

DATLEN

Bits 1-2: Data length to be transferred.

Allowed values:
0: SixteenBit: 16-bit data length
1: TwentyFourBit: 24-bit data length
2: ThirtyTwoBit: 32-bit data length

CKPOL

Bit 3: Steady state clock polarity.

Allowed values:
0: IdleLow: I2S clock inactive state is low level
1: IdleHigh: I2S clock inactive state is high level

I2SSTD

Bits 4-5: I2S standard selection.

Allowed values:
0: Philips: I2S Philips standard
1: MSB: MSB justified standard
2: LSB: LSB justified standard
3: PCM: PCM standard

PCMSYNC

Bit 7: PCM frame synchronization.

Allowed values:
0: Short: Short frame synchronisation
1: Long: Long frame synchronisation

I2SCFG

Bits 8-9: I2S configuration mode.

Allowed values:
0: SlaveTx: Slave - transmit
1: SlaveRx: Slave - receive
2: MasterTx: Master - transmit
3: MasterRx: Master - receive

I2SE

Bit 10: I2S Enable.

Allowed values:
0: Disabled: I2S peripheral is disabled
1: Enabled: I2S peripheral is enabled

I2SMOD

Bit 11: I2S mode selection.

Allowed values:
0: SPIMode: SPI mode is selected
1: I2SMode: I2S mode is selected

I2SPR

I2S prescaler register

Offset: 0x20, reset: 00000010, access: read-write

3/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MCKOE
rw
ODD
rw
I2SDIV
rw
Toggle Fields.

I2SDIV

Bits 0-7: I2S Linear prescaler.

Allowed values: 2-255

ODD

Bit 8: Odd factor for the prescaler.

Allowed values:
0: Even: Real divider value is I2SDIV * 2
1: Odd: Real divider value is (I2SDIV * 2) + 1

MCKOE

Bit 9: Master clock output enable.

Allowed values:
0: Disabled: Master clock output is disabled
1: Enabled: Master clock output is enabled

STK

0xE000E010: SysTick timer

0/7 fields covered. Toggle Registers.

CTRL

SysTick control and status register

Offset: 0x0, reset: 0X00000000, access: read-write

0/4 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
COUNTFLAG
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CLKSOURCE
rw
TICKINT
rw
ENABLE
rw
Toggle Fields.

ENABLE

Bit 0: Counter enable.

TICKINT

Bit 1: SysTick exception request enable.

CLKSOURCE

Bit 2: Clock source selection.

COUNTFLAG

Bit 16: COUNTFLAG.

LOAD_

SysTick reload value register

Offset: 0x4, reset: 0X00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
RELOAD
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RELOAD
rw
Toggle Fields.

RELOAD

Bits 0-23: RELOAD value.

VAL

SysTick current value register

Offset: 0x8, reset: 0X00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CURRENT
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CURRENT
rw
Toggle Fields.

CURRENT

Bits 0-23: Current counter value.

CALIB

SysTick calibration value register

Offset: 0xC, reset: 0X00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
TENMS
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TENMS
rw
Toggle Fields.

TENMS

Bits 0-23: Calibration value.

TIM1

0x40012C00: Advanced timer

77/124 fields covered. Toggle Registers.

CR1

control register 1

Offset: 0x0, reset: 0x0000, access: read-write

8/8 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CKD
rw
ARPE
rw
CMS
rw
DIR
rw
OPM
rw
URS
rw
UDIS
rw
CEN
rw
Toggle Fields.

CEN

Bit 0: Counter enable.

Allowed values:
0: Disabled: Counter disabled
1: Enabled: Counter enabled

UDIS

Bit 1: Update disable.

Allowed values:
0: Enabled: Update event enabled
1: Disabled: Update event disabled

URS

Bit 2: Update request source.

Allowed values:
0: AnyEvent: Any of counter overflow/underflow, setting UG, or update through slave mode, generates an update interrupt or DMA request
1: CounterOnly: Only counter overflow/underflow generates an update interrupt or DMA request

OPM

Bit 3: One-pulse mode.

Allowed values:
0: Disabled: Counter is not stopped at update event
1: Enabled: Counter stops counting at the next update event (clearing the CEN bit)

DIR

Bit 4: Direction.

Allowed values:
0: Up: Counter used as upcounter
1: Down: Counter used as downcounter

CMS

Bits 5-6: Center-aligned mode selection.

Allowed values:
0: EdgeAligned: The counter counts up or down depending on the direction bit
1: CenterAligned1: The counter counts up and down alternatively. Output compare interrupt flags are set only when the counter is counting down.
2: CenterAligned2: The counter counts up and down alternatively. Output compare interrupt flags are set only when the counter is counting up.
3: CenterAligned3: The counter counts up and down alternatively. Output compare interrupt flags are set both when the counter is counting up or down.

ARPE

Bit 7: Auto-reload preload enable.

Allowed values:
0: Disabled: TIMx_APRR register is not buffered
1: Enabled: TIMx_APRR register is buffered

CKD

Bits 8-9: Clock division.

Allowed values:
0: Div1: t_DTS = t_CK_INT
1: Div2: t_DTS = 2 × t_CK_INT
2: Div4: t_DTS = 4 × t_CK_INT

CR2

control register 2

Offset: 0x4, reset: 0x0000, access: read-write

3/12 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
OIS4
rw
OIS3N
rw
OIS3
rw
OIS2N
rw
OIS2
rw
OIS1N
rw
OIS1
rw
TI1S
rw
MMS
rw
CCDS
rw
CCUS
rw
CCPC
rw
Toggle Fields.

CCPC

Bit 0: Capture/compare preloaded control.

CCUS

Bit 2: Capture/compare control update selection.

CCDS

Bit 3: Capture/compare DMA selection.

Allowed values:
0: OnCompare: CCx DMA request sent when CCx event occurs
1: OnUpdate: CCx DMA request sent when update event occurs

MMS

Bits 4-6: Master mode selection.

Allowed values:
0: Reset: The UG bit from the TIMx_EGR register is used as trigger output
1: Enable: The counter enable signal, CNT_EN, is used as trigger output
2: Update: The update event is selected as trigger output
3: ComparePulse: The trigger output send a positive pulse when the CC1IF flag it to be set, as soon as a capture or a compare match occurred
4: CompareOC1: OC1REF signal is used as trigger output
5: CompareOC2: OC2REF signal is used as trigger output
6: CompareOC3: OC3REF signal is used as trigger output
7: CompareOC4: OC4REF signal is used as trigger output

TI1S

Bit 7: TI1 selection.

Allowed values:
0: Normal: The TIMx_CH1 pin is connected to TI1 input
1: XOR: The TIMx_CH1, CH2, CH3 pins are connected to TI1 input

OIS1

Bit 8: Output Idle state 1.

OIS1N

Bit 9: Output Idle state 1.

OIS2

Bit 10: Output Idle state 2.

OIS2N

Bit 11: Output Idle state 2.

OIS3

Bit 12: Output Idle state 3.

OIS3N

Bit 13: Output Idle state 3.

OIS4

Bit 14: Output Idle state 4.

SMCR

slave mode control register

Offset: 0x8, reset: 0x0000, access: read-write

7/7 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ETP
rw
ECE
rw
ETPS
rw
ETF
rw
MSM
rw
TS
rw
SMS
rw
Toggle Fields.

SMS

Bits 0-2: Slave mode selection.

Allowed values:
0: Disabled: Slave mode disabled - if CEN = ‘1 then the prescaler is clocked directly by the internal clock.
1: Encoder_Mode_1: Encoder mode 1 - Counter counts up/down on TI2FP1 edge depending on TI1FP2 level.
2: Encoder_Mode_2: Encoder mode 2 - Counter counts up/down on TI1FP2 edge depending on TI2FP1 level.
3: Encoder_Mode_3: Encoder mode 3 - Counter counts up/down on both TI1FP1 and TI2FP2 edges depending on the level of the other input.
4: Reset_Mode: Reset Mode - Rising edge of the selected trigger input (TRGI) reinitializes the counter and generates an update of the registers.
5: Gated_Mode: Gated Mode - The counter clock is enabled when the trigger input (TRGI) is high. The counter stops (but is not reset) as soon as the trigger becomes low. Both start and stop of the counter are controlled.
6: Trigger_Mode: Trigger Mode - The counter starts at a rising edge of the trigger TRGI (but it is not reset). Only the start of the counter is controlled.
7: Ext_Clock_Mode: External Clock Mode 1 - Rising edges of the selected trigger (TRGI) clock the counter.

TS

Bits 4-6: Trigger selection.

Allowed values:
0: ITR0: Internal Trigger 0 (ITR0)
1: ITR1: Internal Trigger 1 (ITR1)
2: ITR2: Internal Trigger 2 (ITR2)
4: TI1F_ED: TI1 Edge Detector (TI1F_ED)
5: TI1FP1: Filtered Timer Input 1 (TI1FP1)
6: TI2FP2: Filtered Timer Input 2 (TI2FP2)
7: ETRF: External Trigger input (ETRF)

MSM

Bit 7: Master/Slave mode.

Allowed values:
0: NoSync: No action
1: Sync: The effect of an event on the trigger input (TRGI) is delayed to allow a perfect synchronization between the current timer and its slaves (through TRGO). It is useful if we want to synchronize several timers on a single external event.

ETF

Bits 8-11: External trigger filter.

Allowed values:
0: NoFilter: No filter, sampling is done at fDTS
1: FCK_INT_N2: fSAMPLING=fCK_INT, N=2
2: FCK_INT_N4: fSAMPLING=fCK_INT, N=4
3: FCK_INT_N8: fSAMPLING=fCK_INT, N=8
4: FDTS_Div2_N6: fSAMPLING=fDTS/2, N=6
5: FDTS_Div2_N8: fSAMPLING=fDTS/2, N=8
6: FDTS_Div4_N6: fSAMPLING=fDTS/4, N=6
7: FDTS_Div4_N8: fSAMPLING=fDTS/4, N=8
8: FDTS_Div8_N6: fSAMPLING=fDTS/8, N=6
9: FDTS_Div8_N8: fSAMPLING=fDTS/8, N=8
10: FDTS_Div16_N5: fSAMPLING=fDTS/16, N=5
11: FDTS_Div16_N6: fSAMPLING=fDTS/16, N=6
12: FDTS_Div16_N8: fSAMPLING=fDTS/16, N=8
13: FDTS_Div32_N5: fSAMPLING=fDTS/32, N=5
14: FDTS_Div32_N6: fSAMPLING=fDTS/32, N=6
15: FDTS_Div32_N8: fSAMPLING=fDTS/32, N=8

ETPS

Bits 12-13: External trigger prescaler.

Allowed values:
0: Div1: Prescaler OFF
1: Div2: ETRP frequency divided by 2
2: Div4: ETRP frequency divided by 4
3: Div8: ETRP frequency divided by 8

ECE

Bit 14: External clock enable.

Allowed values:
0: Disabled: External clock mode 2 disabled
1: Enabled: External clock mode 2 enabled. The counter is clocked by any active edge on the ETRF signal.

ETP

Bit 15: External trigger polarity.

Allowed values:
0: NotInverted: ETR is noninverted, active at high level or rising edge
1: Inverted: ETR is inverted, active at low level or falling edge

DIER

DMA/Interrupt enable register

Offset: 0xC, reset: 0x0000, access: read-write

12/15 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TDE
rw
COMDE
rw
CC4DE
rw
CC3DE
rw
CC2DE
rw
CC1DE
rw
UDE
rw
BIE
rw
TIE
rw
COMIE
rw
CC4IE
rw
CC3IE
rw
CC2IE
rw
CC1IE
rw
UIE
rw
Toggle Fields.

UIE

Bit 0: Update interrupt enable.

Allowed values:
0: Disabled: Update interrupt disabled
1: Enabled: Update interrupt enabled

CC1IE

Bit 1: Capture/Compare 1 interrupt enable.

Allowed values:
0: Disabled: CCx interrupt disabled
1: Enabled: CCx interrupt enabled

CC2IE

Bit 2: Capture/Compare 2 interrupt enable.

Allowed values:
0: Disabled: CCx interrupt disabled
1: Enabled: CCx interrupt enabled

CC3IE

Bit 3: Capture/Compare 3 interrupt enable.

Allowed values:
0: Disabled: CCx interrupt disabled
1: Enabled: CCx interrupt enabled

CC4IE

Bit 4: Capture/Compare 4 interrupt enable.

Allowed values:
0: Disabled: CCx interrupt disabled
1: Enabled: CCx interrupt enabled

COMIE

Bit 5: COM interrupt enable.

TIE

Bit 6: Trigger interrupt enable.

Allowed values:
0: Disabled: Trigger interrupt disabled
1: Enabled: Trigger interrupt enabled

BIE

Bit 7: Break interrupt enable.

UDE

Bit 8: Update DMA request enable.

Allowed values:
0: Disabled: Update DMA request disabled
1: Enabled: Update DMA request enabled

CC1DE

Bit 9: Capture/Compare 1 DMA request enable.

Allowed values:
0: Disabled: CCx DMA request disabled
1: Enabled: CCx DMA request enabled

CC2DE

Bit 10: Capture/Compare 2 DMA request enable.

Allowed values:
0: Disabled: CCx DMA request disabled
1: Enabled: CCx DMA request enabled

CC3DE

Bit 11: Capture/Compare 3 DMA request enable.

Allowed values:
0: Disabled: CCx DMA request disabled
1: Enabled: CCx DMA request enabled

CC4DE

Bit 12: Capture/Compare 4 DMA request enable.

Allowed values:
0: Disabled: CCx DMA request disabled
1: Enabled: CCx DMA request enabled

COMDE

Bit 13: COM DMA request enable.

TDE

Bit 14: Trigger DMA request enable.

Allowed values:
0: Disabled: Trigger DMA request disabled
1: Enabled: Trigger DMA request enabled

SR

status register

Offset: 0x10, reset: 0x0000, access: read-write

10/12 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CC4OF
rw
CC3OF
rw
CC2OF
rw
CC1OF
rw
BIF
rw
TIF
rw
COMIF
rw
CC4IF
rw
CC3IF
rw
CC2IF
rw
CC1IF
rw
UIF
rw
Toggle Fields.

UIF

Bit 0: Update interrupt flag.

Allowed values:
0: Clear: No update occurred
1: UpdatePending: Update interrupt pending.

CC1IF

Bit 1: Capture/compare 1 interrupt flag.

Allowed values:
1: Match: If CC1 is an output: The content of the counter TIMx_CNT matches the content of the TIMx_CCR1 register. If CC1 is an input: The counter value has been captured in TIMx_CCR1 register.

CC2IF

Bit 2: Capture/Compare 2 interrupt flag.

Allowed values:
1: Match: If CC1 is an output: The content of the counter TIMx_CNT matches the content of the TIMx_CCR1 register. If CC1 is an input: The counter value has been captured in TIMx_CCR1 register.

CC3IF

Bit 3: Capture/Compare 3 interrupt flag.

Allowed values:
1: Match: If CC1 is an output: The content of the counter TIMx_CNT matches the content of the TIMx_CCR1 register. If CC1 is an input: The counter value has been captured in TIMx_CCR1 register.

CC4IF

Bit 4: Capture/Compare 4 interrupt flag.

Allowed values:
1: Match: If CC1 is an output: The content of the counter TIMx_CNT matches the content of the TIMx_CCR1 register. If CC1 is an input: The counter value has been captured in TIMx_CCR1 register.

COMIF

Bit 5: COM interrupt flag.

TIF

Bit 6: Trigger interrupt flag.

Allowed values:
0: NoTrigger: No trigger event occurred
1: Trigger: Trigger interrupt pending

BIF

Bit 7: Break interrupt flag.

CC1OF

Bit 9: Capture/Compare 1 overcapture flag.

Allowed values:
1: Overcapture: The counter value has been captured in TIMx_CCRx register while CCxIF flag was already set

CC2OF

Bit 10: Capture/compare 2 overcapture flag.

Allowed values:
1: Overcapture: The counter value has been captured in TIMx_CCRx register while CCxIF flag was already set

CC3OF

Bit 11: Capture/Compare 3 overcapture flag.

Allowed values:
1: Overcapture: The counter value has been captured in TIMx_CCRx register while CCxIF flag was already set

CC4OF

Bit 12: Capture/Compare 4 overcapture flag.

Allowed values:
1: Overcapture: The counter value has been captured in TIMx_CCRx register while CCxIF flag was already set

EGR

event generation register

Offset: 0x14, reset: 0x0000, access: write-only

6/8 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
BG
w
TG
w
COMG
w
CC4G
w
CC3G
w
CC2G
w
CC1G
w
UG
w
Toggle Fields.

UG

Bit 0: Update generation.

Allowed values:
1: Update: Re-initializes the timer counter and generates an update of the reigsters.

CC1G

Bit 1: Capture/compare 1 generation.

Allowed values:
1: Trigger: If CC1 is an output: CC1IF flag is set, Corresponding interrupt or DMA request is sent if enabled. If CC1 is an input: The current value of the counter is captured in TIMx_CCR1 register.

CC2G

Bit 2: Capture/compare 2 generation.

Allowed values:
1: Trigger: If CC1 is an output: CC1IF flag is set, Corresponding interrupt or DMA request is sent if enabled. If CC1 is an input: The current value of the counter is captured in TIMx_CCR1 register.

CC3G

Bit 3: Capture/compare 3 generation.

Allowed values:
1: Trigger: If CC1 is an output: CC1IF flag is set, Corresponding interrupt or DMA request is sent if enabled. If CC1 is an input: The current value of the counter is captured in TIMx_CCR1 register.

CC4G

Bit 4: Capture/compare 4 generation.

Allowed values:
1: Trigger: If CC1 is an output: CC1IF flag is set, Corresponding interrupt or DMA request is sent if enabled. If CC1 is an input: The current value of the counter is captured in TIMx_CCR1 register.

COMG

Bit 5: Capture/Compare control update generation.

TG

Bit 6: Trigger generation.

Allowed values:
1: Trigger: The TIF flag is set in TIMx_SR register. Related interrupt or DMA transfer can occur if enabled.

BG

Bit 7: Break generation.

CCMR1_Input

capture/compare mode register 1 (input mode)

Offset: 0x18, reset: 0x00000000, access: read-write

4/6 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
IC2F
rw
IC2PSC
rw
CC2S
rw
IC1F
rw
IC1PSC
rw
CC1S
rw
Toggle Fields.

CC1S

Bits 0-1: Capture/Compare 1 selection.

Allowed values:
1: TI1: CC1 channel is configured as input, IC1 is mapped on TI1
2: TI2: CC1 channel is configured as input, IC1 is mapped on TI2
3: TRC: CC1 channel is configured as input, IC1 is mapped on TRC

IC1PSC

Bits 2-3: Input capture 1 prescaler.

IC1F

Bits 4-7: Input capture 1 filter.

Allowed values:
0: NoFilter: No filter, sampling is done at fDTS
1: FCK_INT_N2: fSAMPLING=fCK_INT, N=2
2: FCK_INT_N4: fSAMPLING=fCK_INT, N=4
3: FCK_INT_N8: fSAMPLING=fCK_INT, N=8
4: FDTS_Div2_N6: fSAMPLING=fDTS/2, N=6
5: FDTS_Div2_N8: fSAMPLING=fDTS/2, N=8
6: FDTS_Div4_N6: fSAMPLING=fDTS/4, N=6
7: FDTS_Div4_N8: fSAMPLING=fDTS/4, N=8
8: FDTS_Div8_N6: fSAMPLING=fDTS/8, N=6
9: FDTS_Div8_N8: fSAMPLING=fDTS/8, N=8
10: FDTS_Div16_N5: fSAMPLING=fDTS/16, N=5
11: FDTS_Div16_N6: fSAMPLING=fDTS/16, N=6
12: FDTS_Div16_N8: fSAMPLING=fDTS/16, N=8
13: FDTS_Div32_N5: fSAMPLING=fDTS/32, N=5
14: FDTS_Div32_N6: fSAMPLING=fDTS/32, N=6
15: FDTS_Div32_N8: fSAMPLING=fDTS/32, N=8

CC2S

Bits 8-9: Capture/Compare 2 selection.

Allowed values:
1: TI2: CC2 channel is configured as input, IC2 is mapped on TI2
2: TI1: CC2 channel is configured as input, IC2 is mapped on TI1
3: TRC: CC2 channel is configured as input, IC2 is mapped on TRC

IC2PSC

Bits 10-11: Input capture 2 prescaler.

IC2F

Bits 12-15: Input capture 2 filter.

Allowed values: 0-15

CCMR2_Input

capture/compare mode register 2 (input mode)

Offset: 0x1C, reset: 0x00000000, access: read-write

6/6 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
IC4F
rw
IC4PSC
rw
CC4S
rw
IC3F
rw
IC3PSC
rw
CC3S
rw
Toggle Fields.

CC3S

Bits 0-1: Capture/compare 3 selection.

Allowed values:
1: TI3: CC3 channel is configured as input, IC3 is mapped on TI3
2: TI4: CC3 channel is configured as input, IC3 is mapped on TI4
3: TRC: CC3 channel is configured as input, IC3 is mapped on TRC

IC3PSC

Bits 2-3: Input capture 3 prescaler.

Allowed values: 0-3

IC3F

Bits 4-7: Input capture 3 filter.

Allowed values: 0-15

CC4S

Bits 8-9: Capture/Compare 4 selection.

Allowed values:
1: TI4: CC4 channel is configured as input, IC4 is mapped on TI4
2: TI3: CC4 channel is configured as input, IC4 is mapped on TI3
3: TRC: CC4 channel is configured as input, IC4 is mapped on TRC

IC4PSC

Bits 10-11: Input capture 4 prescaler.

Allowed values: 0-3

IC4F

Bits 12-15: Input capture 4 filter.

Allowed values: 0-15

CCER

capture/compare enable register

Offset: 0x20, reset: 0x0000, access: read-write

0/14 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CC4P
rw
CC4E
rw
CC3NP
rw
CC3NE
rw
CC3P
rw
CC3E
rw
CC2NP
rw
CC2NE
rw
CC2P
rw
CC2E
rw
CC1NP
rw
CC1NE
rw
CC1P
rw
CC1E
rw
Toggle Fields.

CC1E

Bit 0: Capture/Compare 1 output enable.

CC1P

Bit 1: Capture/Compare 1 output Polarity.

CC1NE

Bit 2: Capture/Compare 1 complementary output enable.

CC1NP

Bit 3: Capture/Compare 1 output Polarity.

CC2E

Bit 4: Capture/Compare 2 output enable.

CC2P

Bit 5: Capture/Compare 2 output Polarity.

CC2NE

Bit 6: Capture/Compare 2 complementary output enable.

CC2NP

Bit 7: Capture/Compare 2 output Polarity.

CC3E

Bit 8: Capture/Compare 3 output enable.

CC3P

Bit 9: Capture/Compare 3 output Polarity.

CC3NE

Bit 10: Capture/Compare 3 complementary output enable.

CC3NP

Bit 11: Capture/Compare 3 output Polarity.

CC4E

Bit 12: Capture/Compare 4 output enable.

CC4P

Bit 13: Capture/Compare 3 output Polarity.

CNT

counter

Offset: 0x24, reset: 0x00000000, access: read-write

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CNT
rw
Toggle Fields.

CNT

Bits 0-15: counter value.

Allowed values: 0-65535

PSC

prescaler

Offset: 0x28, reset: 0x0000, access: read-write

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PSC
rw
Toggle Fields.

PSC

Bits 0-15: Prescaler value.

Allowed values: 0-65535

ARR

auto-reload register

Offset: 0x2C, reset: 0x00000000, access: read-write

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ARR
rw
Toggle Fields.

ARR

Bits 0-15: Auto-reload value.

Allowed values: 0-65535

RCR

repetition counter register

Offset: 0x30, reset: 0x0000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
REP
rw
Toggle Fields.

REP

Bits 0-7: Repetition counter value.

CCR%s

capture/compare register 1

Offset: 0x34, reset: 0x00000000, access: read-write

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CCR
rw
Toggle Fields.

CCR

Bits 0-15: Capture/Compare 1 value.

Allowed values: 0-65535

BDTR

break and dead-time register

Offset: 0x44, reset: 0x0000, access: read-write

3/8 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MOE
rw
AOE
rw
BKP
rw
BKE
rw
OSSR
rw
OSSI
rw
LOCK
rw
DTG
rw
Toggle Fields.

DTG

Bits 0-7: Dead-time generator setup.

LOCK

Bits 8-9: Lock configuration.

OSSI

Bit 10: Off-state selection for Idle mode.

Allowed values:
0: Disabled: When inactive, OC/OCN outputs are disabled
1: IdleLevel: When inactive, OC/OCN outputs are forced to idle level

OSSR

Bit 11: Off-state selection for Run mode.

Allowed values:
0: Disabled: When inactive, OC/OCN outputs are disabled
1: IdleLevel: When inactive, OC/OCN outputs are enabled with their inactive level

BKE

Bit 12: Break enable.

BKP

Bit 13: Break polarity.

AOE

Bit 14: Automatic output enable.

MOE

Bit 15: Main output enable.

Allowed values:
0: DisabledIdle: OC/OCN are disabled or forced idle depending on OSSI
1: Enabled: OC/OCN are enabled if CCxE/CCxNE are set

DCR

DMA control register

Offset: 0x48, reset: 0x0000, access: read-write

2/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DBL
rw
DBA
rw
Toggle Fields.

DBA

Bits 0-4: DMA base address.

Allowed values: 0-31

DBL

Bits 8-12: DMA burst length.

Allowed values: 0-18

DMAR

DMA address for full transfer

Offset: 0x4C, reset: 0x0000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DMAB
rw
Toggle Fields.

DMAB

Bits 0-15: DMA register for burst accesses.

TIM10

0x40015000: General purpose timer

9/26 fields covered. Toggle Registers.

CR1

control register 1

Offset: 0x0, reset: 0x0000, access: read-write

5/5 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CKD
rw
ARPE
rw
URS
rw
UDIS
rw
CEN
rw
Toggle Fields.

CEN

Bit 0: Counter enable.

Allowed values:
0: Disabled: Counter disabled
1: Enabled: Counter enabled

UDIS

Bit 1: Update disable.

Allowed values:
0: Enabled: Update event enabled
1: Disabled: Update event disabled

URS

Bit 2: Update request source.

Allowed values:
0: AnyEvent: Any of counter overflow/underflow, setting UG, or update through slave mode, generates an update interrupt or DMA request
1: CounterOnly: Only counter overflow/underflow generates an update interrupt or DMA request

ARPE

Bit 7: Auto-reload preload enable.

Allowed values:
0: Disabled: TIMx_APRR register is not buffered
1: Enabled: TIMx_APRR register is buffered

CKD

Bits 8-9: Clock division.

Allowed values:
0: Div1: t_DTS = t_CK_INT
1: Div2: t_DTS = 2 × t_CK_INT
2: Div4: t_DTS = 4 × t_CK_INT

CR2

control register 2

Offset: 0x4, reset: 0x0000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MMS
rw
Toggle Fields.

MMS

Bits 4-6: Master mode selection.

DIER

DMA/Interrupt enable register

Offset: 0xC, reset: 0x0000, access: read-write

1/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CC1IE
rw
UIE
rw
Toggle Fields.

UIE

Bit 0: Update interrupt enable.

Allowed values:
0: Disabled: Update interrupt disabled
1: Enabled: Update interrupt enabled

CC1IE

Bit 1: Capture/Compare 1 interrupt enable.

SR

status register

Offset: 0x10, reset: 0x0000, access: read-write

1/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CC1OF
rw
CC1IF
rw
UIF
rw
Toggle Fields.

UIF

Bit 0: Update interrupt flag.

Allowed values:
0: Clear: No update occurred
1: UpdatePending: Update interrupt pending.

CC1IF

Bit 1: Capture/compare 1 interrupt flag.

CC1OF

Bit 9: Capture/Compare 1 overcapture flag.

EGR

event generation register

Offset: 0x14, reset: 0x0000, access: write-only

1/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CC1G
w
UG
w
Toggle Fields.

UG

Bit 0: Update generation.

Allowed values:
1: Update: Re-initializes the timer counter and generates an update of the reigsters.

CC1G

Bit 1: Capture/compare 1 generation.

CCMR1_Input

capture/compare mode register (input mode)

Offset: 0x18, reset: 0x00000000, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
IC1F
rw
IC1PSC
rw
CC1S
rw
Toggle Fields.

CC1S

Bits 0-1: Capture/Compare 1 selection.

IC1PSC

Bits 2-3: Input capture 1 prescaler.

IC1F

Bits 4-7: Input capture 1 filter.

CCER

capture/compare enable register

Offset: 0x20, reset: 0x0000, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CC1NP
rw
CC1P
rw
CC1E
rw
Toggle Fields.

CC1E

Bit 0: Capture/Compare 1 output enable.

CC1P

Bit 1: Capture/Compare 1 output Polarity.

CC1NP

Bit 3: Capture/Compare 1 output Polarity.

CNT

counter

Offset: 0x24, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CNT
rw
Toggle Fields.

CNT

Bits 0-15: counter value.

PSC

prescaler

Offset: 0x28, reset: 0x0000, access: read-write

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PSC
rw
Toggle Fields.

PSC

Bits 0-15: Prescaler value.

Allowed values: 0-65535

ARR

auto-reload register

Offset: 0x2C, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ARR
rw
Toggle Fields.

ARR

Bits 0-15: Auto-reload value.

CCR%s

capture/compare register 1

Offset: 0x34, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CCR
rw
Toggle Fields.

CCR

Bits 0-15: Capture/Compare 1 value.

TIM11

0x40015400: General purpose timer

9/26 fields covered. Toggle Registers.

CR1

control register 1

Offset: 0x0, reset: 0x0000, access: read-write

5/5 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CKD
rw
ARPE
rw
URS
rw
UDIS
rw
CEN
rw
Toggle Fields.

CEN

Bit 0: Counter enable.

Allowed values:
0: Disabled: Counter disabled
1: Enabled: Counter enabled

UDIS

Bit 1: Update disable.

Allowed values:
0: Enabled: Update event enabled
1: Disabled: Update event disabled

URS

Bit 2: Update request source.

Allowed values:
0: AnyEvent: Any of counter overflow/underflow, setting UG, or update through slave mode, generates an update interrupt or DMA request
1: CounterOnly: Only counter overflow/underflow generates an update interrupt or DMA request

ARPE

Bit 7: Auto-reload preload enable.

Allowed values:
0: Disabled: TIMx_APRR register is not buffered
1: Enabled: TIMx_APRR register is buffered

CKD

Bits 8-9: Clock division.

Allowed values:
0: Div1: t_DTS = t_CK_INT
1: Div2: t_DTS = 2 × t_CK_INT
2: Div4: t_DTS = 4 × t_CK_INT

CR2

control register 2

Offset: 0x4, reset: 0x0000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MMS
rw
Toggle Fields.

MMS

Bits 4-6: Master mode selection.

DIER

DMA/Interrupt enable register

Offset: 0xC, reset: 0x0000, access: read-write

1/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CC1IE
rw
UIE
rw
Toggle Fields.

UIE

Bit 0: Update interrupt enable.

Allowed values:
0: Disabled: Update interrupt disabled
1: Enabled: Update interrupt enabled

CC1IE

Bit 1: Capture/Compare 1 interrupt enable.

SR

status register

Offset: 0x10, reset: 0x0000, access: read-write

1/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CC1OF
rw
CC1IF
rw
UIF
rw
Toggle Fields.

UIF

Bit 0: Update interrupt flag.

Allowed values:
0: Clear: No update occurred
1: UpdatePending: Update interrupt pending.

CC1IF

Bit 1: Capture/compare 1 interrupt flag.

CC1OF

Bit 9: Capture/Compare 1 overcapture flag.

EGR

event generation register

Offset: 0x14, reset: 0x0000, access: write-only

1/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CC1G
w
UG
w
Toggle Fields.

UG

Bit 0: Update generation.

Allowed values:
1: Update: Re-initializes the timer counter and generates an update of the reigsters.

CC1G

Bit 1: Capture/compare 1 generation.

CCMR1_Input

capture/compare mode register (input mode)

Offset: 0x18, reset: 0x00000000, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
IC1F
rw
IC1PSC
rw
CC1S
rw
Toggle Fields.

CC1S

Bits 0-1: Capture/Compare 1 selection.

IC1PSC

Bits 2-3: Input capture 1 prescaler.

IC1F

Bits 4-7: Input capture 1 filter.

CCER

capture/compare enable register

Offset: 0x20, reset: 0x0000, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CC1NP
rw
CC1P
rw
CC1E
rw
Toggle Fields.

CC1E

Bit 0: Capture/Compare 1 output enable.

CC1P

Bit 1: Capture/Compare 1 output Polarity.

CC1NP

Bit 3: Capture/Compare 1 output Polarity.

CNT

counter

Offset: 0x24, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CNT
rw
Toggle Fields.

CNT

Bits 0-15: counter value.

PSC

prescaler

Offset: 0x28, reset: 0x0000, access: read-write

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PSC
rw
Toggle Fields.

PSC

Bits 0-15: Prescaler value.

Allowed values: 0-65535

ARR

auto-reload register

Offset: 0x2C, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ARR
rw
Toggle Fields.

ARR

Bits 0-15: Auto-reload value.

CCR%s

capture/compare register 1

Offset: 0x34, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CCR
rw
Toggle Fields.

CCR

Bits 0-15: Capture/Compare 1 value.

TIM12

0x40001800: General purpose timer

10/48 fields covered. Toggle Registers.

CR1

control register 1

Offset: 0x0, reset: 0x0000, access: read-write

6/6 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CKD
rw
ARPE
rw
OPM
rw
URS
rw
UDIS
rw
CEN
rw
Toggle Fields.

CEN

Bit 0: Counter enable.

Allowed values:
0: Disabled: Counter disabled
1: Enabled: Counter enabled

UDIS

Bit 1: Update disable.

Allowed values:
0: Enabled: Update event enabled
1: Disabled: Update event disabled

URS

Bit 2: Update request source.

Allowed values:
0: AnyEvent: Any of counter overflow/underflow, setting UG, or update through slave mode, generates an update interrupt or DMA request
1: CounterOnly: Only counter overflow/underflow generates an update interrupt or DMA request

OPM

Bit 3: One-pulse mode.

Allowed values:
0: Disabled: Counter is not stopped at update event
1: Enabled: Counter stops counting at the next update event (clearing the CEN bit)

ARPE

Bit 7: Auto-reload preload enable.

Allowed values:
0: Disabled: TIMx_APRR register is not buffered
1: Enabled: TIMx_APRR register is buffered

CKD

Bits 8-9: Clock division.

Allowed values:
0: Div1: t_DTS = t_CK_INT
1: Div2: t_DTS = 2 × t_CK_INT
2: Div4: t_DTS = 4 × t_CK_INT

CR2

control register 2

Offset: 0x4, reset: 0x0000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MMS
rw
Toggle Fields.

MMS

Bits 4-6: Master mode selection.

SMCR

slave mode control register

Offset: 0x8, reset: 0x0000, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MSM
rw
TS
rw
SMS
rw
Toggle Fields.

SMS

Bits 0-2: Slave mode selection.

TS

Bits 4-6: Trigger selection.

MSM

Bit 7: Master/Slave mode.

DIER

DMA/Interrupt enable register

Offset: 0xC, reset: 0x0000, access: read-write

1/4 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TIE
rw
CC2IE
rw
CC1IE
rw
UIE
rw
Toggle Fields.

UIE

Bit 0: Update interrupt enable.

Allowed values:
0: Disabled: Update interrupt disabled
1: Enabled: Update interrupt enabled

CC1IE

Bit 1: Capture/Compare 1 interrupt enable.

CC2IE

Bit 2: Capture/Compare 2 interrupt enable.

TIE

Bit 6: Trigger interrupt enable.

SR

status register

Offset: 0x10, reset: 0x0000, access: read-write

1/6 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CC2OF
rw
CC1OF
rw
TIF
rw
CC2IF
rw
CC1IF
rw
UIF
rw
Toggle Fields.

UIF

Bit 0: Update interrupt flag.

Allowed values:
0: Clear: No update occurred
1: UpdatePending: Update interrupt pending.

CC1IF

Bit 1: Capture/compare 1 interrupt flag.

CC2IF

Bit 2: Capture/Compare 2 interrupt flag.

TIF

Bit 6: Trigger interrupt flag.

CC1OF

Bit 9: Capture/Compare 1 overcapture flag.

CC2OF

Bit 10: Capture/compare 2 overcapture flag.

EGR

event generation register

Offset: 0x14, reset: 0x0000, access: write-only

1/4 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TG
w
CC2G
w
CC1G
w
UG
w
Toggle Fields.

UG

Bit 0: Update generation.

Allowed values:
1: Update: Re-initializes the timer counter and generates an update of the reigsters.

CC1G

Bit 1: Capture/compare 1 generation.

CC2G

Bit 2: Capture/compare 2 generation.

TG

Bit 6: Trigger generation.

CCMR1_Input

capture/compare mode register 1 (input mode)

Offset: 0x18, reset: 0x00000000, access: read-write

0/6 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
IC2F
rw
IC2PSC
rw
CC2S
rw
IC1F
rw
IC1PSC
rw
CC1S
rw
Toggle Fields.

CC1S

Bits 0-1: Capture/Compare 1 selection.

IC1PSC

Bits 2-3: Input capture 1 prescaler.

IC1F

Bits 4-7: Input capture 1 filter.

CC2S

Bits 8-9: Capture/Compare 2 selection.

IC2PSC

Bits 10-11: Input capture 2 prescaler.

IC2F

Bits 12-15: Input capture 2 filter.

CCER

capture/compare enable register

Offset: 0x20, reset: 0x0000, access: read-write

0/6 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CC2NP
rw
CC2P
rw
CC2E
rw
CC1NP
rw
CC1P
rw
CC1E
rw
Toggle Fields.

CC1E

Bit 0: Capture/Compare 1 output enable.

CC1P

Bit 1: Capture/Compare 1 output Polarity.

CC1NP

Bit 3: Capture/Compare 1 output Polarity.

CC2E

Bit 4: Capture/Compare 2 output enable.

CC2P

Bit 5: Capture/Compare 2 output Polarity.

CC2NP

Bit 7: Capture/Compare 2 output Polarity.

CNT

counter

Offset: 0x24, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CNT
rw
Toggle Fields.

CNT

Bits 0-15: counter value.

PSC

prescaler

Offset: 0x28, reset: 0x0000, access: read-write

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PSC
rw
Toggle Fields.

PSC

Bits 0-15: Prescaler value.

Allowed values: 0-65535

ARR

auto-reload register

Offset: 0x2C, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ARR
rw
Toggle Fields.

ARR

Bits 0-15: Auto-reload value.

CCR%s

capture/compare register 1

Offset: 0x34, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CCR
rw
Toggle Fields.

CCR

Bits 0-15: Capture/Compare 1 value.

TIM13

0x40001C00: General purpose timer

9/26 fields covered. Toggle Registers.

CR1

control register 1

Offset: 0x0, reset: 0x0000, access: read-write

5/5 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CKD
rw
ARPE
rw
URS
rw
UDIS
rw
CEN
rw
Toggle Fields.

CEN

Bit 0: Counter enable.

Allowed values:
0: Disabled: Counter disabled
1: Enabled: Counter enabled

UDIS

Bit 1: Update disable.

Allowed values:
0: Enabled: Update event enabled
1: Disabled: Update event disabled

URS

Bit 2: Update request source.

Allowed values:
0: AnyEvent: Any of counter overflow/underflow, setting UG, or update through slave mode, generates an update interrupt or DMA request
1: CounterOnly: Only counter overflow/underflow generates an update interrupt or DMA request

ARPE

Bit 7: Auto-reload preload enable.

Allowed values:
0: Disabled: TIMx_APRR register is not buffered
1: Enabled: TIMx_APRR register is buffered

CKD

Bits 8-9: Clock division.

Allowed values:
0: Div1: t_DTS = t_CK_INT
1: Div2: t_DTS = 2 × t_CK_INT
2: Div4: t_DTS = 4 × t_CK_INT

CR2

control register 2

Offset: 0x4, reset: 0x0000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MMS
rw
Toggle Fields.

MMS

Bits 4-6: Master mode selection.

DIER

DMA/Interrupt enable register

Offset: 0xC, reset: 0x0000, access: read-write

1/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CC1IE
rw
UIE
rw
Toggle Fields.

UIE

Bit 0: Update interrupt enable.

Allowed values:
0: Disabled: Update interrupt disabled
1: Enabled: Update interrupt enabled

CC1IE

Bit 1: Capture/Compare 1 interrupt enable.

SR

status register

Offset: 0x10, reset: 0x0000, access: read-write

1/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CC1OF
rw
CC1IF
rw
UIF
rw
Toggle Fields.

UIF

Bit 0: Update interrupt flag.

Allowed values:
0: Clear: No update occurred
1: UpdatePending: Update interrupt pending.

CC1IF

Bit 1: Capture/compare 1 interrupt flag.

CC1OF

Bit 9: Capture/Compare 1 overcapture flag.

EGR

event generation register

Offset: 0x14, reset: 0x0000, access: write-only

1/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CC1G
w
UG
w
Toggle Fields.

UG

Bit 0: Update generation.

Allowed values:
1: Update: Re-initializes the timer counter and generates an update of the reigsters.

CC1G

Bit 1: Capture/compare 1 generation.

CCMR1_Input

capture/compare mode register (input mode)

Offset: 0x18, reset: 0x00000000, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
IC1F
rw
IC1PSC
rw
CC1S
rw
Toggle Fields.

CC1S

Bits 0-1: Capture/Compare 1 selection.

IC1PSC

Bits 2-3: Input capture 1 prescaler.

IC1F

Bits 4-7: Input capture 1 filter.

CCER

capture/compare enable register

Offset: 0x20, reset: 0x0000, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CC1NP
rw
CC1P
rw
CC1E
rw
Toggle Fields.

CC1E

Bit 0: Capture/Compare 1 output enable.

CC1P

Bit 1: Capture/Compare 1 output Polarity.

CC1NP

Bit 3: Capture/Compare 1 output Polarity.

CNT

counter

Offset: 0x24, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CNT
rw
Toggle Fields.

CNT

Bits 0-15: counter value.

PSC

prescaler

Offset: 0x28, reset: 0x0000, access: read-write

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PSC
rw
Toggle Fields.

PSC

Bits 0-15: Prescaler value.

Allowed values: 0-65535

ARR

auto-reload register

Offset: 0x2C, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ARR
rw
Toggle Fields.

ARR

Bits 0-15: Auto-reload value.

CCR%s

capture/compare register 1

Offset: 0x34, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CCR
rw
Toggle Fields.

CCR

Bits 0-15: Capture/Compare 1 value.

TIM14

0x40002000: General purpose timer

9/26 fields covered. Toggle Registers.

CR1

control register 1

Offset: 0x0, reset: 0x0000, access: read-write

5/5 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CKD
rw
ARPE
rw
URS
rw
UDIS
rw
CEN
rw
Toggle Fields.

CEN

Bit 0: Counter enable.

Allowed values:
0: Disabled: Counter disabled
1: Enabled: Counter enabled

UDIS

Bit 1: Update disable.

Allowed values:
0: Enabled: Update event enabled
1: Disabled: Update event disabled

URS

Bit 2: Update request source.

Allowed values:
0: AnyEvent: Any of counter overflow/underflow, setting UG, or update through slave mode, generates an update interrupt or DMA request
1: CounterOnly: Only counter overflow/underflow generates an update interrupt or DMA request

ARPE

Bit 7: Auto-reload preload enable.

Allowed values:
0: Disabled: TIMx_APRR register is not buffered
1: Enabled: TIMx_APRR register is buffered

CKD

Bits 8-9: Clock division.

Allowed values:
0: Div1: t_DTS = t_CK_INT
1: Div2: t_DTS = 2 × t_CK_INT
2: Div4: t_DTS = 4 × t_CK_INT

CR2

control register 2

Offset: 0x4, reset: 0x0000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MMS
rw
Toggle Fields.

MMS

Bits 4-6: Master mode selection.

DIER

DMA/Interrupt enable register

Offset: 0xC, reset: 0x0000, access: read-write

1/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CC1IE
rw
UIE
rw
Toggle Fields.

UIE

Bit 0: Update interrupt enable.

Allowed values:
0: Disabled: Update interrupt disabled
1: Enabled: Update interrupt enabled

CC1IE

Bit 1: Capture/Compare 1 interrupt enable.

SR

status register

Offset: 0x10, reset: 0x0000, access: read-write

1/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CC1OF
rw
CC1IF
rw
UIF
rw
Toggle Fields.

UIF

Bit 0: Update interrupt flag.

Allowed values:
0: Clear: No update occurred
1: UpdatePending: Update interrupt pending.

CC1IF

Bit 1: Capture/compare 1 interrupt flag.

CC1OF

Bit 9: Capture/Compare 1 overcapture flag.

EGR

event generation register

Offset: 0x14, reset: 0x0000, access: write-only

1/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CC1G
w
UG
w
Toggle Fields.

UG

Bit 0: Update generation.

Allowed values:
1: Update: Re-initializes the timer counter and generates an update of the reigsters.

CC1G

Bit 1: Capture/compare 1 generation.

CCMR1_Input

capture/compare mode register (input mode)

Offset: 0x18, reset: 0x00000000, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
IC1F
rw
IC1PSC
rw
CC1S
rw
Toggle Fields.

CC1S

Bits 0-1: Capture/Compare 1 selection.

IC1PSC

Bits 2-3: Input capture 1 prescaler.

IC1F

Bits 4-7: Input capture 1 filter.

CCER

capture/compare enable register

Offset: 0x20, reset: 0x0000, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CC1NP
rw
CC1P
rw
CC1E
rw
Toggle Fields.

CC1E

Bit 0: Capture/Compare 1 output enable.

CC1P

Bit 1: Capture/Compare 1 output Polarity.

CC1NP

Bit 3: Capture/Compare 1 output Polarity.

CNT

counter

Offset: 0x24, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CNT
rw
Toggle Fields.

CNT

Bits 0-15: counter value.

PSC

prescaler

Offset: 0x28, reset: 0x0000, access: read-write

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PSC
rw
Toggle Fields.

PSC

Bits 0-15: Prescaler value.

Allowed values: 0-65535

ARR

auto-reload register

Offset: 0x2C, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ARR
rw
Toggle Fields.

ARR

Bits 0-15: Auto-reload value.

CCR%s

capture/compare register 1

Offset: 0x34, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CCR
rw
Toggle Fields.

CCR

Bits 0-15: Capture/Compare 1 value.

TIM2

0x40000000: General purpose timer

74/93 fields covered. Toggle Registers.

CR1

control register 1

Offset: 0x0, reset: 0x0000, access: read-write

8/8 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CKD
rw
ARPE
rw
CMS
rw
DIR
rw
OPM
rw
URS
rw
UDIS
rw
CEN
rw
Toggle Fields.

CEN

Bit 0: Counter enable.

Allowed values:
0: Disabled: Counter disabled
1: Enabled: Counter enabled

UDIS

Bit 1: Update disable.

Allowed values:
0: Enabled: Update event enabled
1: Disabled: Update event disabled

URS

Bit 2: Update request source.

Allowed values:
0: AnyEvent: Any of counter overflow/underflow, setting UG, or update through slave mode, generates an update interrupt or DMA request
1: CounterOnly: Only counter overflow/underflow generates an update interrupt or DMA request

OPM

Bit 3: One-pulse mode.

Allowed values:
0: Disabled: Counter is not stopped at update event
1: Enabled: Counter stops counting at the next update event (clearing the CEN bit)

DIR

Bit 4: Direction.

Allowed values:
0: Up: Counter used as upcounter
1: Down: Counter used as downcounter

CMS

Bits 5-6: Center-aligned mode selection.

Allowed values:
0: EdgeAligned: The counter counts up or down depending on the direction bit
1: CenterAligned1: The counter counts up and down alternatively. Output compare interrupt flags are set only when the counter is counting down.
2: CenterAligned2: The counter counts up and down alternatively. Output compare interrupt flags are set only when the counter is counting up.
3: CenterAligned3: The counter counts up and down alternatively. Output compare interrupt flags are set both when the counter is counting up or down.

ARPE

Bit 7: Auto-reload preload enable.

Allowed values:
0: Disabled: TIMx_APRR register is not buffered
1: Enabled: TIMx_APRR register is buffered

CKD

Bits 8-9: Clock division.

Allowed values:
0: Div1: t_DTS = t_CK_INT
1: Div2: t_DTS = 2 × t_CK_INT
2: Div4: t_DTS = 4 × t_CK_INT

CR2

control register 2

Offset: 0x4, reset: 0x0000, access: read-write

3/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TI1S
rw
MMS
rw
CCDS
rw
Toggle Fields.

CCDS

Bit 3: Capture/compare DMA selection.

Allowed values:
0: OnCompare: CCx DMA request sent when CCx event occurs
1: OnUpdate: CCx DMA request sent when update event occurs

MMS

Bits 4-6: Master mode selection.

Allowed values:
0: Reset: The UG bit from the TIMx_EGR register is used as trigger output
1: Enable: The counter enable signal, CNT_EN, is used as trigger output
2: Update: The update event is selected as trigger output
3: ComparePulse: The trigger output send a positive pulse when the CC1IF flag it to be set, as soon as a capture or a compare match occurred
4: CompareOC1: OC1REF signal is used as trigger output
5: CompareOC2: OC2REF signal is used as trigger output
6: CompareOC3: OC3REF signal is used as trigger output
7: CompareOC4: OC4REF signal is used as trigger output

TI1S

Bit 7: TI1 selection.

Allowed values:
0: Normal: The TIMx_CH1 pin is connected to TI1 input
1: XOR: The TIMx_CH1, CH2, CH3 pins are connected to TI1 input

SMCR

slave mode control register

Offset: 0x8, reset: 0x0000, access: read-write

7/7 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ETP
rw
ECE
rw
ETPS
rw
ETF
rw
MSM
rw
TS
rw
SMS
rw
Toggle Fields.

SMS

Bits 0-2: Slave mode selection.

Allowed values:
0: Disabled: Slave mode disabled - if CEN = ‘1 then the prescaler is clocked directly by the internal clock.
1: Encoder_Mode_1: Encoder mode 1 - Counter counts up/down on TI2FP1 edge depending on TI1FP2 level.
2: Encoder_Mode_2: Encoder mode 2 - Counter counts up/down on TI1FP2 edge depending on TI2FP1 level.
3: Encoder_Mode_3: Encoder mode 3 - Counter counts up/down on both TI1FP1 and TI2FP2 edges depending on the level of the other input.
4: Reset_Mode: Reset Mode - Rising edge of the selected trigger input (TRGI) reinitializes the counter and generates an update of the registers.
5: Gated_Mode: Gated Mode - The counter clock is enabled when the trigger input (TRGI) is high. The counter stops (but is not reset) as soon as the trigger becomes low. Both start and stop of the counter are controlled.
6: Trigger_Mode: Trigger Mode - The counter starts at a rising edge of the trigger TRGI (but it is not reset). Only the start of the counter is controlled.
7: Ext_Clock_Mode: External Clock Mode 1 - Rising edges of the selected trigger (TRGI) clock the counter.

TS

Bits 4-6: Trigger selection.

Allowed values:
0: ITR0: Internal Trigger 0 (ITR0)
1: ITR1: Internal Trigger 1 (ITR1)
2: ITR2: Internal Trigger 2 (ITR2)
4: TI1F_ED: TI1 Edge Detector (TI1F_ED)
5: TI1FP1: Filtered Timer Input 1 (TI1FP1)
6: TI2FP2: Filtered Timer Input 2 (TI2FP2)
7: ETRF: External Trigger input (ETRF)

MSM

Bit 7: Master/Slave mode.

Allowed values:
0: NoSync: No action
1: Sync: The effect of an event on the trigger input (TRGI) is delayed to allow a perfect synchronization between the current timer and its slaves (through TRGO). It is useful if we want to synchronize several timers on a single external event.

ETF

Bits 8-11: External trigger filter.

Allowed values:
0: NoFilter: No filter, sampling is done at fDTS
1: FCK_INT_N2: fSAMPLING=fCK_INT, N=2
2: FCK_INT_N4: fSAMPLING=fCK_INT, N=4
3: FCK_INT_N8: fSAMPLING=fCK_INT, N=8
4: FDTS_Div2_N6: fSAMPLING=fDTS/2, N=6
5: FDTS_Div2_N8: fSAMPLING=fDTS/2, N=8
6: FDTS_Div4_N6: fSAMPLING=fDTS/4, N=6
7: FDTS_Div4_N8: fSAMPLING=fDTS/4, N=8
8: FDTS_Div8_N6: fSAMPLING=fDTS/8, N=6
9: FDTS_Div8_N8: fSAMPLING=fDTS/8, N=8
10: FDTS_Div16_N5: fSAMPLING=fDTS/16, N=5
11: FDTS_Div16_N6: fSAMPLING=fDTS/16, N=6
12: FDTS_Div16_N8: fSAMPLING=fDTS/16, N=8
13: FDTS_Div32_N5: fSAMPLING=fDTS/32, N=5
14: FDTS_Div32_N6: fSAMPLING=fDTS/32, N=6
15: FDTS_Div32_N8: fSAMPLING=fDTS/32, N=8

ETPS

Bits 12-13: External trigger prescaler.

Allowed values:
0: Div1: Prescaler OFF
1: Div2: ETRP frequency divided by 2
2: Div4: ETRP frequency divided by 4
3: Div8: ETRP frequency divided by 8

ECE

Bit 14: External clock enable.

Allowed values:
0: Disabled: External clock mode 2 disabled
1: Enabled: External clock mode 2 enabled. The counter is clocked by any active edge on the ETRF signal.

ETP

Bit 15: External trigger polarity.

Allowed values:
0: NotInverted: ETR is noninverted, active at high level or rising edge
1: Inverted: ETR is inverted, active at low level or falling edge

DIER

DMA/Interrupt enable register

Offset: 0xC, reset: 0x0000, access: read-write

12/12 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TDE
rw
CC4DE
rw
CC3DE
rw
CC2DE
rw
CC1DE
rw
UDE
rw
TIE
rw
CC4IE
rw
CC3IE
rw
CC2IE
rw
CC1IE
rw
UIE
rw
Toggle Fields.

UIE

Bit 0: Update interrupt enable.

Allowed values:
0: Disabled: Update interrupt disabled
1: Enabled: Update interrupt enabled

CC1IE

Bit 1: Capture/Compare 1 interrupt enable.

Allowed values:
0: Disabled: CCx interrupt disabled
1: Enabled: CCx interrupt enabled

CC2IE

Bit 2: Capture/Compare 2 interrupt enable.

Allowed values:
0: Disabled: CCx interrupt disabled
1: Enabled: CCx interrupt enabled

CC3IE

Bit 3: Capture/Compare 3 interrupt enable.

Allowed values:
0: Disabled: CCx interrupt disabled
1: Enabled: CCx interrupt enabled

CC4IE

Bit 4: Capture/Compare 4 interrupt enable.

Allowed values:
0: Disabled: CCx interrupt disabled
1: Enabled: CCx interrupt enabled

TIE

Bit 6: Trigger interrupt enable.

Allowed values:
0: Disabled: Trigger interrupt disabled
1: Enabled: Trigger interrupt enabled

UDE

Bit 8: Update DMA request enable.

Allowed values:
0: Disabled: Update DMA request disabled
1: Enabled: Update DMA request enabled

CC1DE

Bit 9: Capture/Compare 1 DMA request enable.

Allowed values:
0: Disabled: CCx DMA request disabled
1: Enabled: CCx DMA request enabled

CC2DE

Bit 10: Capture/Compare 2 DMA request enable.

Allowed values:
0: Disabled: CCx DMA request disabled
1: Enabled: CCx DMA request enabled

CC3DE

Bit 11: Capture/Compare 3 DMA request enable.

Allowed values:
0: Disabled: CCx DMA request disabled
1: Enabled: CCx DMA request enabled

CC4DE

Bit 12: Capture/Compare 4 DMA request enable.

Allowed values:
0: Disabled: CCx DMA request disabled
1: Enabled: CCx DMA request enabled

TDE

Bit 14: Trigger DMA request enable.

Allowed values:
0: Disabled: Trigger DMA request disabled
1: Enabled: Trigger DMA request enabled

SR

status register

Offset: 0x10, reset: 0x0000, access: read-write

10/10 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CC4OF
rw
CC3OF
rw
CC2OF
rw
CC1OF
rw
TIF
rw
CC4IF
rw
CC3IF
rw
CC2IF
rw
CC1IF
rw
UIF
rw
Toggle Fields.

UIF

Bit 0: Update interrupt flag.

Allowed values:
0: Clear: No update occurred
1: UpdatePending: Update interrupt pending.

CC1IF

Bit 1: Capture/compare 1 interrupt flag.

Allowed values:
1: Match: If CC1 is an output: The content of the counter TIMx_CNT matches the content of the TIMx_CCR1 register. If CC1 is an input: The counter value has been captured in TIMx_CCR1 register.

CC2IF

Bit 2: Capture/Compare 2 interrupt flag.

Allowed values:
1: Match: If CC1 is an output: The content of the counter TIMx_CNT matches the content of the TIMx_CCR1 register. If CC1 is an input: The counter value has been captured in TIMx_CCR1 register.

CC3IF

Bit 3: Capture/Compare 3 interrupt flag.

Allowed values:
1: Match: If CC1 is an output: The content of the counter TIMx_CNT matches the content of the TIMx_CCR1 register. If CC1 is an input: The counter value has been captured in TIMx_CCR1 register.

CC4IF

Bit 4: Capture/Compare 4 interrupt flag.

Allowed values:
1: Match: If CC1 is an output: The content of the counter TIMx_CNT matches the content of the TIMx_CCR1 register. If CC1 is an input: The counter value has been captured in TIMx_CCR1 register.

TIF

Bit 6: Trigger interrupt flag.

Allowed values:
0: NoTrigger: No trigger event occurred
1: Trigger: Trigger interrupt pending

CC1OF

Bit 9: Capture/Compare 1 overcapture flag.

Allowed values:
1: Overcapture: The counter value has been captured in TIMx_CCRx register while CCxIF flag was already set

CC2OF

Bit 10: Capture/compare 2 overcapture flag.

Allowed values:
1: Overcapture: The counter value has been captured in TIMx_CCRx register while CCxIF flag was already set

CC3OF

Bit 11: Capture/Compare 3 overcapture flag.

Allowed values:
1: Overcapture: The counter value has been captured in TIMx_CCRx register while CCxIF flag was already set

CC4OF

Bit 12: Capture/Compare 4 overcapture flag.

Allowed values:
1: Overcapture: The counter value has been captured in TIMx_CCRx register while CCxIF flag was already set

EGR

event generation register

Offset: 0x14, reset: 0x0000, access: write-only

6/6 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TG
w
CC4G
w
CC3G
w
CC2G
w
CC1G
w
UG
w
Toggle Fields.

UG

Bit 0: Update generation.

Allowed values:
1: Update: Re-initializes the timer counter and generates an update of the reigsters.

CC1G

Bit 1: Capture/compare 1 generation.

Allowed values:
1: Trigger: If CC1 is an output: CC1IF flag is set, Corresponding interrupt or DMA request is sent if enabled. If CC1 is an input: The current value of the counter is captured in TIMx_CCR1 register.

CC2G

Bit 2: Capture/compare 2 generation.

Allowed values:
1: Trigger: If CC1 is an output: CC1IF flag is set, Corresponding interrupt or DMA request is sent if enabled. If CC1 is an input: The current value of the counter is captured in TIMx_CCR1 register.

CC3G

Bit 3: Capture/compare 3 generation.

Allowed values:
1: Trigger: If CC1 is an output: CC1IF flag is set, Corresponding interrupt or DMA request is sent if enabled. If CC1 is an input: The current value of the counter is captured in TIMx_CCR1 register.

CC4G

Bit 4: Capture/compare 4 generation.

Allowed values:
1: Trigger: If CC1 is an output: CC1IF flag is set, Corresponding interrupt or DMA request is sent if enabled. If CC1 is an input: The current value of the counter is captured in TIMx_CCR1 register.

TG

Bit 6: Trigger generation.

Allowed values:
1: Trigger: The TIF flag is set in TIMx_SR register. Related interrupt or DMA transfer can occur if enabled.

CCMR1_Input

capture/compare mode register 1 (input mode)

Offset: 0x18, reset: 0x00000000, access: read-write

4/6 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
IC2F
rw
IC2PSC
rw
CC2S
rw
IC1F
rw
IC1PSC
rw
CC1S
rw
Toggle Fields.

CC1S

Bits 0-1: Capture/Compare 1 selection.

Allowed values:
1: TI1: CC1 channel is configured as input, IC1 is mapped on TI1
2: TI2: CC1 channel is configured as input, IC1 is mapped on TI2
3: TRC: CC1 channel is configured as input, IC1 is mapped on TRC

IC1PSC

Bits 2-3: Input capture 1 prescaler.

IC1F

Bits 4-7: Input capture 1 filter.

Allowed values:
0: NoFilter: No filter, sampling is done at fDTS
1: FCK_INT_N2: fSAMPLING=fCK_INT, N=2
2: FCK_INT_N4: fSAMPLING=fCK_INT, N=4
3: FCK_INT_N8: fSAMPLING=fCK_INT, N=8
4: FDTS_Div2_N6: fSAMPLING=fDTS/2, N=6
5: FDTS_Div2_N8: fSAMPLING=fDTS/2, N=8
6: FDTS_Div4_N6: fSAMPLING=fDTS/4, N=6
7: FDTS_Div4_N8: fSAMPLING=fDTS/4, N=8
8: FDTS_Div8_N6: fSAMPLING=fDTS/8, N=6
9: FDTS_Div8_N8: fSAMPLING=fDTS/8, N=8
10: FDTS_Div16_N5: fSAMPLING=fDTS/16, N=5
11: FDTS_Div16_N6: fSAMPLING=fDTS/16, N=6
12: FDTS_Div16_N8: fSAMPLING=fDTS/16, N=8
13: FDTS_Div32_N5: fSAMPLING=fDTS/32, N=5
14: FDTS_Div32_N6: fSAMPLING=fDTS/32, N=6
15: FDTS_Div32_N8: fSAMPLING=fDTS/32, N=8

CC2S

Bits 8-9: Capture/compare 2 selection.

Allowed values:
1: TI2: CC2 channel is configured as input, IC2 is mapped on TI2
2: TI1: CC2 channel is configured as input, IC2 is mapped on TI1
3: TRC: CC2 channel is configured as input, IC2 is mapped on TRC

IC2PSC

Bits 10-11: Input capture 2 prescaler.

IC2F

Bits 12-15: Input capture 2 filter.

Allowed values: 0-15

CCMR2_Input

capture/compare mode register 2 (input mode)

Offset: 0x1C, reset: 0x00000000, access: read-write

6/6 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
IC4F
rw
IC4PSC
rw
CC4S
rw
IC3F
rw
IC3PSC
rw
CC3S
rw
Toggle Fields.

CC3S

Bits 0-1: Capture/Compare 3 selection.

Allowed values:
1: TI3: CC3 channel is configured as input, IC3 is mapped on TI3
2: TI4: CC3 channel is configured as input, IC3 is mapped on TI4
3: TRC: CC3 channel is configured as input, IC3 is mapped on TRC

IC3PSC

Bits 2-3: Input capture 3 prescaler.

Allowed values: 0-3

IC3F

Bits 4-7: Input capture 3 filter.

Allowed values: 0-15

CC4S

Bits 8-9: Capture/Compare 4 selection.

Allowed values:
1: TI4: CC4 channel is configured as input, IC4 is mapped on TI4
2: TI3: CC4 channel is configured as input, IC4 is mapped on TI3
3: TRC: CC4 channel is configured as input, IC4 is mapped on TRC

IC4PSC

Bits 10-11: Input capture 4 prescaler.

Allowed values: 0-3

IC4F

Bits 12-15: Input capture 4 filter.

Allowed values: 0-15

CCER

capture/compare enable register

Offset: 0x20, reset: 0x0000, access: read-write

0/8 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CC4P
rw
CC4E
rw
CC3P
rw
CC3E
rw
CC2P
rw
CC2E
rw
CC1P
rw
CC1E
rw
Toggle Fields.

CC1E

Bit 0: Capture/Compare 1 output enable.

CC1P

Bit 1: Capture/Compare 1 output Polarity.

CC2E

Bit 4: Capture/Compare 2 output enable.

CC2P

Bit 5: Capture/Compare 2 output Polarity.

CC3E

Bit 8: Capture/Compare 3 output enable.

CC3P

Bit 9: Capture/Compare 3 output Polarity.

CC4E

Bit 12: Capture/Compare 4 output enable.

CC4P

Bit 13: Capture/Compare 3 output Polarity.

CNT

counter

Offset: 0x24, reset: 0x00000000, access: read-write

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CNT
rw
Toggle Fields.

CNT

Bits 0-15: counter value.

Allowed values: 0-65535

PSC

prescaler

Offset: 0x28, reset: 0x0000, access: read-write

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PSC
rw
Toggle Fields.

PSC

Bits 0-15: Prescaler value.

Allowed values: 0-65535

ARR

auto-reload register

Offset: 0x2C, reset: 0x00000000, access: read-write

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ARR
rw
Toggle Fields.

ARR

Bits 0-15: Auto-reload value.

Allowed values: 0-65535

CCR%s

capture/compare register 1

Offset: 0x34, reset: 0x00000000, access: read-write

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CCR
rw
Toggle Fields.

CCR

Bits 0-15: Capture/Compare 1 value.

Allowed values: 0-65535

DCR

DMA control register

Offset: 0x48, reset: 0x0000, access: read-write

2/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DBL
rw
DBA
rw
Toggle Fields.

DBA

Bits 0-4: DMA base address.

Allowed values: 0-31

DBL

Bits 8-12: DMA burst length.

Allowed values: 0-18

DMAR

DMA address for full transfer

Offset: 0x4C, reset: 0x0000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DMAB
rw
Toggle Fields.

DMAB

Bits 0-15: DMA register for burst accesses.

TIM3

0x40000400: General purpose timer

74/93 fields covered. Toggle Registers.

CR1

control register 1

Offset: 0x0, reset: 0x0000, access: read-write

8/8 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CKD
rw
ARPE
rw
CMS
rw
DIR
rw
OPM
rw
URS
rw
UDIS
rw
CEN
rw
Toggle Fields.

CEN

Bit 0: Counter enable.

Allowed values:
0: Disabled: Counter disabled
1: Enabled: Counter enabled

UDIS

Bit 1: Update disable.

Allowed values:
0: Enabled: Update event enabled
1: Disabled: Update event disabled

URS

Bit 2: Update request source.

Allowed values:
0: AnyEvent: Any of counter overflow/underflow, setting UG, or update through slave mode, generates an update interrupt or DMA request
1: CounterOnly: Only counter overflow/underflow generates an update interrupt or DMA request

OPM

Bit 3: One-pulse mode.

Allowed values:
0: Disabled: Counter is not stopped at update event
1: Enabled: Counter stops counting at the next update event (clearing the CEN bit)

DIR

Bit 4: Direction.

Allowed values:
0: Up: Counter used as upcounter
1: Down: Counter used as downcounter

CMS

Bits 5-6: Center-aligned mode selection.

Allowed values:
0: EdgeAligned: The counter counts up or down depending on the direction bit
1: CenterAligned1: The counter counts up and down alternatively. Output compare interrupt flags are set only when the counter is counting down.
2: CenterAligned2: The counter counts up and down alternatively. Output compare interrupt flags are set only when the counter is counting up.
3: CenterAligned3: The counter counts up and down alternatively. Output compare interrupt flags are set both when the counter is counting up or down.

ARPE

Bit 7: Auto-reload preload enable.

Allowed values:
0: Disabled: TIMx_APRR register is not buffered
1: Enabled: TIMx_APRR register is buffered

CKD

Bits 8-9: Clock division.

Allowed values:
0: Div1: t_DTS = t_CK_INT
1: Div2: t_DTS = 2 × t_CK_INT
2: Div4: t_DTS = 4 × t_CK_INT

CR2

control register 2

Offset: 0x4, reset: 0x0000, access: read-write

3/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TI1S
rw
MMS
rw
CCDS
rw
Toggle Fields.

CCDS

Bit 3: Capture/compare DMA selection.

Allowed values:
0: OnCompare: CCx DMA request sent when CCx event occurs
1: OnUpdate: CCx DMA request sent when update event occurs

MMS

Bits 4-6: Master mode selection.

Allowed values:
0: Reset: The UG bit from the TIMx_EGR register is used as trigger output
1: Enable: The counter enable signal, CNT_EN, is used as trigger output
2: Update: The update event is selected as trigger output
3: ComparePulse: The trigger output send a positive pulse when the CC1IF flag it to be set, as soon as a capture or a compare match occurred
4: CompareOC1: OC1REF signal is used as trigger output
5: CompareOC2: OC2REF signal is used as trigger output
6: CompareOC3: OC3REF signal is used as trigger output
7: CompareOC4: OC4REF signal is used as trigger output

TI1S

Bit 7: TI1 selection.

Allowed values:
0: Normal: The TIMx_CH1 pin is connected to TI1 input
1: XOR: The TIMx_CH1, CH2, CH3 pins are connected to TI1 input

SMCR

slave mode control register

Offset: 0x8, reset: 0x0000, access: read-write

7/7 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ETP
rw
ECE
rw
ETPS
rw
ETF
rw
MSM
rw
TS
rw
SMS
rw
Toggle Fields.

SMS

Bits 0-2: Slave mode selection.

Allowed values:
0: Disabled: Slave mode disabled - if CEN = ‘1 then the prescaler is clocked directly by the internal clock.
1: Encoder_Mode_1: Encoder mode 1 - Counter counts up/down on TI2FP1 edge depending on TI1FP2 level.
2: Encoder_Mode_2: Encoder mode 2 - Counter counts up/down on TI1FP2 edge depending on TI2FP1 level.
3: Encoder_Mode_3: Encoder mode 3 - Counter counts up/down on both TI1FP1 and TI2FP2 edges depending on the level of the other input.
4: Reset_Mode: Reset Mode - Rising edge of the selected trigger input (TRGI) reinitializes the counter and generates an update of the registers.
5: Gated_Mode: Gated Mode - The counter clock is enabled when the trigger input (TRGI) is high. The counter stops (but is not reset) as soon as the trigger becomes low. Both start and stop of the counter are controlled.
6: Trigger_Mode: Trigger Mode - The counter starts at a rising edge of the trigger TRGI (but it is not reset). Only the start of the counter is controlled.
7: Ext_Clock_Mode: External Clock Mode 1 - Rising edges of the selected trigger (TRGI) clock the counter.

TS

Bits 4-6: Trigger selection.

Allowed values:
0: ITR0: Internal Trigger 0 (ITR0)
1: ITR1: Internal Trigger 1 (ITR1)
2: ITR2: Internal Trigger 2 (ITR2)
4: TI1F_ED: TI1 Edge Detector (TI1F_ED)
5: TI1FP1: Filtered Timer Input 1 (TI1FP1)
6: TI2FP2: Filtered Timer Input 2 (TI2FP2)
7: ETRF: External Trigger input (ETRF)

MSM

Bit 7: Master/Slave mode.

Allowed values:
0: NoSync: No action
1: Sync: The effect of an event on the trigger input (TRGI) is delayed to allow a perfect synchronization between the current timer and its slaves (through TRGO). It is useful if we want to synchronize several timers on a single external event.

ETF

Bits 8-11: External trigger filter.

Allowed values:
0: NoFilter: No filter, sampling is done at fDTS
1: FCK_INT_N2: fSAMPLING=fCK_INT, N=2
2: FCK_INT_N4: fSAMPLING=fCK_INT, N=4
3: FCK_INT_N8: fSAMPLING=fCK_INT, N=8
4: FDTS_Div2_N6: fSAMPLING=fDTS/2, N=6
5: FDTS_Div2_N8: fSAMPLING=fDTS/2, N=8
6: FDTS_Div4_N6: fSAMPLING=fDTS/4, N=6
7: FDTS_Div4_N8: fSAMPLING=fDTS/4, N=8
8: FDTS_Div8_N6: fSAMPLING=fDTS/8, N=6
9: FDTS_Div8_N8: fSAMPLING=fDTS/8, N=8
10: FDTS_Div16_N5: fSAMPLING=fDTS/16, N=5
11: FDTS_Div16_N6: fSAMPLING=fDTS/16, N=6
12: FDTS_Div16_N8: fSAMPLING=fDTS/16, N=8
13: FDTS_Div32_N5: fSAMPLING=fDTS/32, N=5
14: FDTS_Div32_N6: fSAMPLING=fDTS/32, N=6
15: FDTS_Div32_N8: fSAMPLING=fDTS/32, N=8

ETPS

Bits 12-13: External trigger prescaler.

Allowed values:
0: Div1: Prescaler OFF
1: Div2: ETRP frequency divided by 2
2: Div4: ETRP frequency divided by 4
3: Div8: ETRP frequency divided by 8

ECE

Bit 14: External clock enable.

Allowed values:
0: Disabled: External clock mode 2 disabled
1: Enabled: External clock mode 2 enabled. The counter is clocked by any active edge on the ETRF signal.

ETP

Bit 15: External trigger polarity.

Allowed values:
0: NotInverted: ETR is noninverted, active at high level or rising edge
1: Inverted: ETR is inverted, active at low level or falling edge

DIER

DMA/Interrupt enable register

Offset: 0xC, reset: 0x0000, access: read-write

12/12 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TDE
rw
CC4DE
rw
CC3DE
rw
CC2DE
rw
CC1DE
rw
UDE
rw
TIE
rw
CC4IE
rw
CC3IE
rw
CC2IE
rw
CC1IE
rw
UIE
rw
Toggle Fields.

UIE

Bit 0: Update interrupt enable.

Allowed values:
0: Disabled: Update interrupt disabled
1: Enabled: Update interrupt enabled

CC1IE

Bit 1: Capture/Compare 1 interrupt enable.

Allowed values:
0: Disabled: CCx interrupt disabled
1: Enabled: CCx interrupt enabled

CC2IE

Bit 2: Capture/Compare 2 interrupt enable.

Allowed values:
0: Disabled: CCx interrupt disabled
1: Enabled: CCx interrupt enabled

CC3IE

Bit 3: Capture/Compare 3 interrupt enable.

Allowed values:
0: Disabled: CCx interrupt disabled
1: Enabled: CCx interrupt enabled

CC4IE

Bit 4: Capture/Compare 4 interrupt enable.

Allowed values:
0: Disabled: CCx interrupt disabled
1: Enabled: CCx interrupt enabled

TIE

Bit 6: Trigger interrupt enable.

Allowed values:
0: Disabled: Trigger interrupt disabled
1: Enabled: Trigger interrupt enabled

UDE

Bit 8: Update DMA request enable.

Allowed values:
0: Disabled: Update DMA request disabled
1: Enabled: Update DMA request enabled

CC1DE

Bit 9: Capture/Compare 1 DMA request enable.

Allowed values:
0: Disabled: CCx DMA request disabled
1: Enabled: CCx DMA request enabled

CC2DE

Bit 10: Capture/Compare 2 DMA request enable.

Allowed values:
0: Disabled: CCx DMA request disabled
1: Enabled: CCx DMA request enabled

CC3DE

Bit 11: Capture/Compare 3 DMA request enable.

Allowed values:
0: Disabled: CCx DMA request disabled
1: Enabled: CCx DMA request enabled

CC4DE

Bit 12: Capture/Compare 4 DMA request enable.

Allowed values:
0: Disabled: CCx DMA request disabled
1: Enabled: CCx DMA request enabled

TDE

Bit 14: Trigger DMA request enable.

Allowed values:
0: Disabled: Trigger DMA request disabled
1: Enabled: Trigger DMA request enabled

SR

status register

Offset: 0x10, reset: 0x0000, access: read-write

10/10 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CC4OF
rw
CC3OF
rw
CC2OF
rw
CC1OF
rw
TIF
rw
CC4IF
rw
CC3IF
rw
CC2IF
rw
CC1IF
rw
UIF
rw
Toggle Fields.

UIF

Bit 0: Update interrupt flag.

Allowed values:
0: Clear: No update occurred
1: UpdatePending: Update interrupt pending.

CC1IF

Bit 1: Capture/compare 1 interrupt flag.

Allowed values:
1: Match: If CC1 is an output: The content of the counter TIMx_CNT matches the content of the TIMx_CCR1 register. If CC1 is an input: The counter value has been captured in TIMx_CCR1 register.

CC2IF

Bit 2: Capture/Compare 2 interrupt flag.

Allowed values:
1: Match: If CC1 is an output: The content of the counter TIMx_CNT matches the content of the TIMx_CCR1 register. If CC1 is an input: The counter value has been captured in TIMx_CCR1 register.

CC3IF

Bit 3: Capture/Compare 3 interrupt flag.

Allowed values:
1: Match: If CC1 is an output: The content of the counter TIMx_CNT matches the content of the TIMx_CCR1 register. If CC1 is an input: The counter value has been captured in TIMx_CCR1 register.

CC4IF

Bit 4: Capture/Compare 4 interrupt flag.

Allowed values:
1: Match: If CC1 is an output: The content of the counter TIMx_CNT matches the content of the TIMx_CCR1 register. If CC1 is an input: The counter value has been captured in TIMx_CCR1 register.

TIF

Bit 6: Trigger interrupt flag.

Allowed values:
0: NoTrigger: No trigger event occurred
1: Trigger: Trigger interrupt pending

CC1OF

Bit 9: Capture/Compare 1 overcapture flag.

Allowed values:
1: Overcapture: The counter value has been captured in TIMx_CCRx register while CCxIF flag was already set

CC2OF

Bit 10: Capture/compare 2 overcapture flag.

Allowed values:
1: Overcapture: The counter value has been captured in TIMx_CCRx register while CCxIF flag was already set

CC3OF

Bit 11: Capture/Compare 3 overcapture flag.

Allowed values:
1: Overcapture: The counter value has been captured in TIMx_CCRx register while CCxIF flag was already set

CC4OF

Bit 12: Capture/Compare 4 overcapture flag.

Allowed values:
1: Overcapture: The counter value has been captured in TIMx_CCRx register while CCxIF flag was already set

EGR

event generation register

Offset: 0x14, reset: 0x0000, access: write-only

6/6 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TG
w
CC4G
w
CC3G
w
CC2G
w
CC1G
w
UG
w
Toggle Fields.

UG

Bit 0: Update generation.

Allowed values:
1: Update: Re-initializes the timer counter and generates an update of the reigsters.

CC1G

Bit 1: Capture/compare 1 generation.

Allowed values:
1: Trigger: If CC1 is an output: CC1IF flag is set, Corresponding interrupt or DMA request is sent if enabled. If CC1 is an input: The current value of the counter is captured in TIMx_CCR1 register.

CC2G

Bit 2: Capture/compare 2 generation.

Allowed values:
1: Trigger: If CC1 is an output: CC1IF flag is set, Corresponding interrupt or DMA request is sent if enabled. If CC1 is an input: The current value of the counter is captured in TIMx_CCR1 register.

CC3G

Bit 3: Capture/compare 3 generation.

Allowed values:
1: Trigger: If CC1 is an output: CC1IF flag is set, Corresponding interrupt or DMA request is sent if enabled. If CC1 is an input: The current value of the counter is captured in TIMx_CCR1 register.

CC4G

Bit 4: Capture/compare 4 generation.

Allowed values:
1: Trigger: If CC1 is an output: CC1IF flag is set, Corresponding interrupt or DMA request is sent if enabled. If CC1 is an input: The current value of the counter is captured in TIMx_CCR1 register.

TG

Bit 6: Trigger generation.

Allowed values:
1: Trigger: The TIF flag is set in TIMx_SR register. Related interrupt or DMA transfer can occur if enabled.

CCMR1_Input

capture/compare mode register 1 (input mode)

Offset: 0x18, reset: 0x00000000, access: read-write

4/6 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
IC2F
rw
IC2PSC
rw
CC2S
rw
IC1F
rw
IC1PSC
rw
CC1S
rw
Toggle Fields.

CC1S

Bits 0-1: Capture/Compare 1 selection.

Allowed values:
1: TI1: CC1 channel is configured as input, IC1 is mapped on TI1
2: TI2: CC1 channel is configured as input, IC1 is mapped on TI2
3: TRC: CC1 channel is configured as input, IC1 is mapped on TRC

IC1PSC

Bits 2-3: Input capture 1 prescaler.

IC1F

Bits 4-7: Input capture 1 filter.

Allowed values:
0: NoFilter: No filter, sampling is done at fDTS
1: FCK_INT_N2: fSAMPLING=fCK_INT, N=2
2: FCK_INT_N4: fSAMPLING=fCK_INT, N=4
3: FCK_INT_N8: fSAMPLING=fCK_INT, N=8
4: FDTS_Div2_N6: fSAMPLING=fDTS/2, N=6
5: FDTS_Div2_N8: fSAMPLING=fDTS/2, N=8
6: FDTS_Div4_N6: fSAMPLING=fDTS/4, N=6
7: FDTS_Div4_N8: fSAMPLING=fDTS/4, N=8
8: FDTS_Div8_N6: fSAMPLING=fDTS/8, N=6
9: FDTS_Div8_N8: fSAMPLING=fDTS/8, N=8
10: FDTS_Div16_N5: fSAMPLING=fDTS/16, N=5
11: FDTS_Div16_N6: fSAMPLING=fDTS/16, N=6
12: FDTS_Div16_N8: fSAMPLING=fDTS/16, N=8
13: FDTS_Div32_N5: fSAMPLING=fDTS/32, N=5
14: FDTS_Div32_N6: fSAMPLING=fDTS/32, N=6
15: FDTS_Div32_N8: fSAMPLING=fDTS/32, N=8

CC2S

Bits 8-9: Capture/compare 2 selection.

Allowed values:
1: TI2: CC2 channel is configured as input, IC2 is mapped on TI2
2: TI1: CC2 channel is configured as input, IC2 is mapped on TI1
3: TRC: CC2 channel is configured as input, IC2 is mapped on TRC

IC2PSC

Bits 10-11: Input capture 2 prescaler.

IC2F

Bits 12-15: Input capture 2 filter.

Allowed values: 0-15

CCMR2_Input

capture/compare mode register 2 (input mode)

Offset: 0x1C, reset: 0x00000000, access: read-write

6/6 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
IC4F
rw
IC4PSC
rw
CC4S
rw
IC3F
rw
IC3PSC
rw
CC3S
rw
Toggle Fields.

CC3S

Bits 0-1: Capture/Compare 3 selection.

Allowed values:
1: TI3: CC3 channel is configured as input, IC3 is mapped on TI3
2: TI4: CC3 channel is configured as input, IC3 is mapped on TI4
3: TRC: CC3 channel is configured as input, IC3 is mapped on TRC

IC3PSC

Bits 2-3: Input capture 3 prescaler.

Allowed values: 0-3

IC3F

Bits 4-7: Input capture 3 filter.

Allowed values: 0-15

CC4S

Bits 8-9: Capture/Compare 4 selection.

Allowed values:
1: TI4: CC4 channel is configured as input, IC4 is mapped on TI4
2: TI3: CC4 channel is configured as input, IC4 is mapped on TI3
3: TRC: CC4 channel is configured as input, IC4 is mapped on TRC

IC4PSC

Bits 10-11: Input capture 4 prescaler.

Allowed values: 0-3

IC4F

Bits 12-15: Input capture 4 filter.

Allowed values: 0-15

CCER

capture/compare enable register

Offset: 0x20, reset: 0x0000, access: read-write

0/8 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CC4P
rw
CC4E
rw
CC3P
rw
CC3E
rw
CC2P
rw
CC2E
rw
CC1P
rw
CC1E
rw
Toggle Fields.

CC1E

Bit 0: Capture/Compare 1 output enable.

CC1P

Bit 1: Capture/Compare 1 output Polarity.

CC2E

Bit 4: Capture/Compare 2 output enable.

CC2P

Bit 5: Capture/Compare 2 output Polarity.

CC3E

Bit 8: Capture/Compare 3 output enable.

CC3P

Bit 9: Capture/Compare 3 output Polarity.

CC4E

Bit 12: Capture/Compare 4 output enable.

CC4P

Bit 13: Capture/Compare 3 output Polarity.

CNT

counter

Offset: 0x24, reset: 0x00000000, access: read-write

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CNT
rw
Toggle Fields.

CNT

Bits 0-15: counter value.

Allowed values: 0-65535

PSC

prescaler

Offset: 0x28, reset: 0x0000, access: read-write

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PSC
rw
Toggle Fields.

PSC

Bits 0-15: Prescaler value.

Allowed values: 0-65535

ARR

auto-reload register

Offset: 0x2C, reset: 0x00000000, access: read-write

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ARR
rw
Toggle Fields.

ARR

Bits 0-15: Auto-reload value.

Allowed values: 0-65535

CCR%s

capture/compare register 1

Offset: 0x34, reset: 0x00000000, access: read-write

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CCR
rw
Toggle Fields.

CCR

Bits 0-15: Capture/Compare 1 value.

Allowed values: 0-65535

DCR

DMA control register

Offset: 0x48, reset: 0x0000, access: read-write

2/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DBL
rw
DBA
rw
Toggle Fields.

DBA

Bits 0-4: DMA base address.

Allowed values: 0-31

DBL

Bits 8-12: DMA burst length.

Allowed values: 0-18

DMAR

DMA address for full transfer

Offset: 0x4C, reset: 0x0000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DMAB
rw
Toggle Fields.

DMAB

Bits 0-15: DMA register for burst accesses.

TIM4

0x40000800: General purpose timer

74/93 fields covered. Toggle Registers.

CR1

control register 1

Offset: 0x0, reset: 0x0000, access: read-write

8/8 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CKD
rw
ARPE
rw
CMS
rw
DIR
rw
OPM
rw
URS
rw
UDIS
rw
CEN
rw
Toggle Fields.

CEN

Bit 0: Counter enable.

Allowed values:
0: Disabled: Counter disabled
1: Enabled: Counter enabled

UDIS

Bit 1: Update disable.

Allowed values:
0: Enabled: Update event enabled
1: Disabled: Update event disabled

URS

Bit 2: Update request source.

Allowed values:
0: AnyEvent: Any of counter overflow/underflow, setting UG, or update through slave mode, generates an update interrupt or DMA request
1: CounterOnly: Only counter overflow/underflow generates an update interrupt or DMA request

OPM

Bit 3: One-pulse mode.

Allowed values:
0: Disabled: Counter is not stopped at update event
1: Enabled: Counter stops counting at the next update event (clearing the CEN bit)

DIR

Bit 4: Direction.

Allowed values:
0: Up: Counter used as upcounter
1: Down: Counter used as downcounter

CMS

Bits 5-6: Center-aligned mode selection.

Allowed values:
0: EdgeAligned: The counter counts up or down depending on the direction bit
1: CenterAligned1: The counter counts up and down alternatively. Output compare interrupt flags are set only when the counter is counting down.
2: CenterAligned2: The counter counts up and down alternatively. Output compare interrupt flags are set only when the counter is counting up.
3: CenterAligned3: The counter counts up and down alternatively. Output compare interrupt flags are set both when the counter is counting up or down.

ARPE

Bit 7: Auto-reload preload enable.

Allowed values:
0: Disabled: TIMx_APRR register is not buffered
1: Enabled: TIMx_APRR register is buffered

CKD

Bits 8-9: Clock division.

Allowed values:
0: Div1: t_DTS = t_CK_INT
1: Div2: t_DTS = 2 × t_CK_INT
2: Div4: t_DTS = 4 × t_CK_INT

CR2

control register 2

Offset: 0x4, reset: 0x0000, access: read-write

3/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TI1S
rw
MMS
rw
CCDS
rw
Toggle Fields.

CCDS

Bit 3: Capture/compare DMA selection.

Allowed values:
0: OnCompare: CCx DMA request sent when CCx event occurs
1: OnUpdate: CCx DMA request sent when update event occurs

MMS

Bits 4-6: Master mode selection.

Allowed values:
0: Reset: The UG bit from the TIMx_EGR register is used as trigger output
1: Enable: The counter enable signal, CNT_EN, is used as trigger output
2: Update: The update event is selected as trigger output
3: ComparePulse: The trigger output send a positive pulse when the CC1IF flag it to be set, as soon as a capture or a compare match occurred
4: CompareOC1: OC1REF signal is used as trigger output
5: CompareOC2: OC2REF signal is used as trigger output
6: CompareOC3: OC3REF signal is used as trigger output
7: CompareOC4: OC4REF signal is used as trigger output

TI1S

Bit 7: TI1 selection.

Allowed values:
0: Normal: The TIMx_CH1 pin is connected to TI1 input
1: XOR: The TIMx_CH1, CH2, CH3 pins are connected to TI1 input

SMCR

slave mode control register

Offset: 0x8, reset: 0x0000, access: read-write

7/7 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ETP
rw
ECE
rw
ETPS
rw
ETF
rw
MSM
rw
TS
rw
SMS
rw
Toggle Fields.

SMS

Bits 0-2: Slave mode selection.

Allowed values:
0: Disabled: Slave mode disabled - if CEN = ‘1 then the prescaler is clocked directly by the internal clock.
1: Encoder_Mode_1: Encoder mode 1 - Counter counts up/down on TI2FP1 edge depending on TI1FP2 level.
2: Encoder_Mode_2: Encoder mode 2 - Counter counts up/down on TI1FP2 edge depending on TI2FP1 level.
3: Encoder_Mode_3: Encoder mode 3 - Counter counts up/down on both TI1FP1 and TI2FP2 edges depending on the level of the other input.
4: Reset_Mode: Reset Mode - Rising edge of the selected trigger input (TRGI) reinitializes the counter and generates an update of the registers.
5: Gated_Mode: Gated Mode - The counter clock is enabled when the trigger input (TRGI) is high. The counter stops (but is not reset) as soon as the trigger becomes low. Both start and stop of the counter are controlled.
6: Trigger_Mode: Trigger Mode - The counter starts at a rising edge of the trigger TRGI (but it is not reset). Only the start of the counter is controlled.
7: Ext_Clock_Mode: External Clock Mode 1 - Rising edges of the selected trigger (TRGI) clock the counter.

TS

Bits 4-6: Trigger selection.

Allowed values:
0: ITR0: Internal Trigger 0 (ITR0)
1: ITR1: Internal Trigger 1 (ITR1)
2: ITR2: Internal Trigger 2 (ITR2)
4: TI1F_ED: TI1 Edge Detector (TI1F_ED)
5: TI1FP1: Filtered Timer Input 1 (TI1FP1)
6: TI2FP2: Filtered Timer Input 2 (TI2FP2)
7: ETRF: External Trigger input (ETRF)

MSM

Bit 7: Master/Slave mode.

Allowed values:
0: NoSync: No action
1: Sync: The effect of an event on the trigger input (TRGI) is delayed to allow a perfect synchronization between the current timer and its slaves (through TRGO). It is useful if we want to synchronize several timers on a single external event.

ETF

Bits 8-11: External trigger filter.

Allowed values:
0: NoFilter: No filter, sampling is done at fDTS
1: FCK_INT_N2: fSAMPLING=fCK_INT, N=2
2: FCK_INT_N4: fSAMPLING=fCK_INT, N=4
3: FCK_INT_N8: fSAMPLING=fCK_INT, N=8
4: FDTS_Div2_N6: fSAMPLING=fDTS/2, N=6
5: FDTS_Div2_N8: fSAMPLING=fDTS/2, N=8
6: FDTS_Div4_N6: fSAMPLING=fDTS/4, N=6
7: FDTS_Div4_N8: fSAMPLING=fDTS/4, N=8
8: FDTS_Div8_N6: fSAMPLING=fDTS/8, N=6
9: FDTS_Div8_N8: fSAMPLING=fDTS/8, N=8
10: FDTS_Div16_N5: fSAMPLING=fDTS/16, N=5
11: FDTS_Div16_N6: fSAMPLING=fDTS/16, N=6
12: FDTS_Div16_N8: fSAMPLING=fDTS/16, N=8
13: FDTS_Div32_N5: fSAMPLING=fDTS/32, N=5
14: FDTS_Div32_N6: fSAMPLING=fDTS/32, N=6
15: FDTS_Div32_N8: fSAMPLING=fDTS/32, N=8

ETPS

Bits 12-13: External trigger prescaler.

Allowed values:
0: Div1: Prescaler OFF
1: Div2: ETRP frequency divided by 2
2: Div4: ETRP frequency divided by 4
3: Div8: ETRP frequency divided by 8

ECE

Bit 14: External clock enable.

Allowed values:
0: Disabled: External clock mode 2 disabled
1: Enabled: External clock mode 2 enabled. The counter is clocked by any active edge on the ETRF signal.

ETP

Bit 15: External trigger polarity.

Allowed values:
0: NotInverted: ETR is noninverted, active at high level or rising edge
1: Inverted: ETR is inverted, active at low level or falling edge

DIER

DMA/Interrupt enable register

Offset: 0xC, reset: 0x0000, access: read-write

12/12 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TDE
rw
CC4DE
rw
CC3DE
rw
CC2DE
rw
CC1DE
rw
UDE
rw
TIE
rw
CC4IE
rw
CC3IE
rw
CC2IE
rw
CC1IE
rw
UIE
rw
Toggle Fields.

UIE

Bit 0: Update interrupt enable.

Allowed values:
0: Disabled: Update interrupt disabled
1: Enabled: Update interrupt enabled

CC1IE

Bit 1: Capture/Compare 1 interrupt enable.

Allowed values:
0: Disabled: CCx interrupt disabled
1: Enabled: CCx interrupt enabled

CC2IE

Bit 2: Capture/Compare 2 interrupt enable.

Allowed values:
0: Disabled: CCx interrupt disabled
1: Enabled: CCx interrupt enabled

CC3IE

Bit 3: Capture/Compare 3 interrupt enable.

Allowed values:
0: Disabled: CCx interrupt disabled
1: Enabled: CCx interrupt enabled

CC4IE

Bit 4: Capture/Compare 4 interrupt enable.

Allowed values:
0: Disabled: CCx interrupt disabled
1: Enabled: CCx interrupt enabled

TIE

Bit 6: Trigger interrupt enable.

Allowed values:
0: Disabled: Trigger interrupt disabled
1: Enabled: Trigger interrupt enabled

UDE

Bit 8: Update DMA request enable.

Allowed values:
0: Disabled: Update DMA request disabled
1: Enabled: Update DMA request enabled

CC1DE

Bit 9: Capture/Compare 1 DMA request enable.

Allowed values:
0: Disabled: CCx DMA request disabled
1: Enabled: CCx DMA request enabled

CC2DE

Bit 10: Capture/Compare 2 DMA request enable.

Allowed values:
0: Disabled: CCx DMA request disabled
1: Enabled: CCx DMA request enabled

CC3DE

Bit 11: Capture/Compare 3 DMA request enable.

Allowed values:
0: Disabled: CCx DMA request disabled
1: Enabled: CCx DMA request enabled

CC4DE

Bit 12: Capture/Compare 4 DMA request enable.

Allowed values:
0: Disabled: CCx DMA request disabled
1: Enabled: CCx DMA request enabled

TDE

Bit 14: Trigger DMA request enable.

Allowed values:
0: Disabled: Trigger DMA request disabled
1: Enabled: Trigger DMA request enabled

SR

status register

Offset: 0x10, reset: 0x0000, access: read-write

10/10 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CC4OF
rw
CC3OF
rw
CC2OF
rw
CC1OF
rw
TIF
rw
CC4IF
rw
CC3IF
rw
CC2IF
rw
CC1IF
rw
UIF
rw
Toggle Fields.

UIF

Bit 0: Update interrupt flag.

Allowed values:
0: Clear: No update occurred
1: UpdatePending: Update interrupt pending.

CC1IF

Bit 1: Capture/compare 1 interrupt flag.

Allowed values:
1: Match: If CC1 is an output: The content of the counter TIMx_CNT matches the content of the TIMx_CCR1 register. If CC1 is an input: The counter value has been captured in TIMx_CCR1 register.

CC2IF

Bit 2: Capture/Compare 2 interrupt flag.

Allowed values:
1: Match: If CC1 is an output: The content of the counter TIMx_CNT matches the content of the TIMx_CCR1 register. If CC1 is an input: The counter value has been captured in TIMx_CCR1 register.

CC3IF

Bit 3: Capture/Compare 3 interrupt flag.

Allowed values:
1: Match: If CC1 is an output: The content of the counter TIMx_CNT matches the content of the TIMx_CCR1 register. If CC1 is an input: The counter value has been captured in TIMx_CCR1 register.

CC4IF

Bit 4: Capture/Compare 4 interrupt flag.

Allowed values:
1: Match: If CC1 is an output: The content of the counter TIMx_CNT matches the content of the TIMx_CCR1 register. If CC1 is an input: The counter value has been captured in TIMx_CCR1 register.

TIF

Bit 6: Trigger interrupt flag.

Allowed values:
0: NoTrigger: No trigger event occurred
1: Trigger: Trigger interrupt pending

CC1OF

Bit 9: Capture/Compare 1 overcapture flag.

Allowed values:
1: Overcapture: The counter value has been captured in TIMx_CCRx register while CCxIF flag was already set

CC2OF

Bit 10: Capture/compare 2 overcapture flag.

Allowed values:
1: Overcapture: The counter value has been captured in TIMx_CCRx register while CCxIF flag was already set

CC3OF

Bit 11: Capture/Compare 3 overcapture flag.

Allowed values:
1: Overcapture: The counter value has been captured in TIMx_CCRx register while CCxIF flag was already set

CC4OF

Bit 12: Capture/Compare 4 overcapture flag.

Allowed values:
1: Overcapture: The counter value has been captured in TIMx_CCRx register while CCxIF flag was already set

EGR

event generation register

Offset: 0x14, reset: 0x0000, access: write-only

6/6 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TG
w
CC4G
w
CC3G
w
CC2G
w
CC1G
w
UG
w
Toggle Fields.

UG

Bit 0: Update generation.

Allowed values:
1: Update: Re-initializes the timer counter and generates an update of the reigsters.

CC1G

Bit 1: Capture/compare 1 generation.

Allowed values:
1: Trigger: If CC1 is an output: CC1IF flag is set, Corresponding interrupt or DMA request is sent if enabled. If CC1 is an input: The current value of the counter is captured in TIMx_CCR1 register.

CC2G

Bit 2: Capture/compare 2 generation.

Allowed values:
1: Trigger: If CC1 is an output: CC1IF flag is set, Corresponding interrupt or DMA request is sent if enabled. If CC1 is an input: The current value of the counter is captured in TIMx_CCR1 register.

CC3G

Bit 3: Capture/compare 3 generation.

Allowed values:
1: Trigger: If CC1 is an output: CC1IF flag is set, Corresponding interrupt or DMA request is sent if enabled. If CC1 is an input: The current value of the counter is captured in TIMx_CCR1 register.

CC4G

Bit 4: Capture/compare 4 generation.

Allowed values:
1: Trigger: If CC1 is an output: CC1IF flag is set, Corresponding interrupt or DMA request is sent if enabled. If CC1 is an input: The current value of the counter is captured in TIMx_CCR1 register.

TG

Bit 6: Trigger generation.

Allowed values:
1: Trigger: The TIF flag is set in TIMx_SR register. Related interrupt or DMA transfer can occur if enabled.

CCMR1_Input

capture/compare mode register 1 (input mode)

Offset: 0x18, reset: 0x00000000, access: read-write

4/6 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
IC2F
rw
IC2PSC
rw
CC2S
rw
IC1F
rw
IC1PSC
rw
CC1S
rw
Toggle Fields.

CC1S

Bits 0-1: Capture/Compare 1 selection.

Allowed values:
1: TI1: CC1 channel is configured as input, IC1 is mapped on TI1
2: TI2: CC1 channel is configured as input, IC1 is mapped on TI2
3: TRC: CC1 channel is configured as input, IC1 is mapped on TRC

IC1PSC

Bits 2-3: Input capture 1 prescaler.

IC1F

Bits 4-7: Input capture 1 filter.

Allowed values:
0: NoFilter: No filter, sampling is done at fDTS
1: FCK_INT_N2: fSAMPLING=fCK_INT, N=2
2: FCK_INT_N4: fSAMPLING=fCK_INT, N=4
3: FCK_INT_N8: fSAMPLING=fCK_INT, N=8
4: FDTS_Div2_N6: fSAMPLING=fDTS/2, N=6
5: FDTS_Div2_N8: fSAMPLING=fDTS/2, N=8
6: FDTS_Div4_N6: fSAMPLING=fDTS/4, N=6
7: FDTS_Div4_N8: fSAMPLING=fDTS/4, N=8
8: FDTS_Div8_N6: fSAMPLING=fDTS/8, N=6
9: FDTS_Div8_N8: fSAMPLING=fDTS/8, N=8
10: FDTS_Div16_N5: fSAMPLING=fDTS/16, N=5
11: FDTS_Div16_N6: fSAMPLING=fDTS/16, N=6
12: FDTS_Div16_N8: fSAMPLING=fDTS/16, N=8
13: FDTS_Div32_N5: fSAMPLING=fDTS/32, N=5
14: FDTS_Div32_N6: fSAMPLING=fDTS/32, N=6
15: FDTS_Div32_N8: fSAMPLING=fDTS/32, N=8

CC2S

Bits 8-9: Capture/compare 2 selection.

Allowed values:
1: TI2: CC2 channel is configured as input, IC2 is mapped on TI2
2: TI1: CC2 channel is configured as input, IC2 is mapped on TI1
3: TRC: CC2 channel is configured as input, IC2 is mapped on TRC

IC2PSC

Bits 10-11: Input capture 2 prescaler.

IC2F

Bits 12-15: Input capture 2 filter.

Allowed values: 0-15

CCMR2_Input

capture/compare mode register 2 (input mode)

Offset: 0x1C, reset: 0x00000000, access: read-write

6/6 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
IC4F
rw
IC4PSC
rw
CC4S
rw
IC3F
rw
IC3PSC
rw
CC3S
rw
Toggle Fields.

CC3S

Bits 0-1: Capture/Compare 3 selection.

Allowed values:
1: TI3: CC3 channel is configured as input, IC3 is mapped on TI3
2: TI4: CC3 channel is configured as input, IC3 is mapped on TI4
3: TRC: CC3 channel is configured as input, IC3 is mapped on TRC

IC3PSC

Bits 2-3: Input capture 3 prescaler.

Allowed values: 0-3

IC3F

Bits 4-7: Input capture 3 filter.

Allowed values: 0-15

CC4S

Bits 8-9: Capture/Compare 4 selection.

Allowed values:
1: TI4: CC4 channel is configured as input, IC4 is mapped on TI4
2: TI3: CC4 channel is configured as input, IC4 is mapped on TI3
3: TRC: CC4 channel is configured as input, IC4 is mapped on TRC

IC4PSC

Bits 10-11: Input capture 4 prescaler.

Allowed values: 0-3

IC4F

Bits 12-15: Input capture 4 filter.

Allowed values: 0-15

CCER

capture/compare enable register

Offset: 0x20, reset: 0x0000, access: read-write

0/8 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CC4P
rw
CC4E
rw
CC3P
rw
CC3E
rw
CC2P
rw
CC2E
rw
CC1P
rw
CC1E
rw
Toggle Fields.

CC1E

Bit 0: Capture/Compare 1 output enable.

CC1P

Bit 1: Capture/Compare 1 output Polarity.

CC2E

Bit 4: Capture/Compare 2 output enable.

CC2P

Bit 5: Capture/Compare 2 output Polarity.

CC3E

Bit 8: Capture/Compare 3 output enable.

CC3P

Bit 9: Capture/Compare 3 output Polarity.

CC4E

Bit 12: Capture/Compare 4 output enable.

CC4P

Bit 13: Capture/Compare 3 output Polarity.

CNT

counter

Offset: 0x24, reset: 0x00000000, access: read-write

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CNT
rw
Toggle Fields.

CNT

Bits 0-15: counter value.

Allowed values: 0-65535

PSC

prescaler

Offset: 0x28, reset: 0x0000, access: read-write

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PSC
rw
Toggle Fields.

PSC

Bits 0-15: Prescaler value.

Allowed values: 0-65535

ARR

auto-reload register

Offset: 0x2C, reset: 0x00000000, access: read-write

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ARR
rw
Toggle Fields.

ARR

Bits 0-15: Auto-reload value.

Allowed values: 0-65535

CCR%s

capture/compare register 1

Offset: 0x34, reset: 0x00000000, access: read-write

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CCR
rw
Toggle Fields.

CCR

Bits 0-15: Capture/Compare 1 value.

Allowed values: 0-65535

DCR

DMA control register

Offset: 0x48, reset: 0x0000, access: read-write

2/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DBL
rw
DBA
rw
Toggle Fields.

DBA

Bits 0-4: DMA base address.

Allowed values: 0-31

DBL

Bits 8-12: DMA burst length.

Allowed values: 0-18

DMAR

DMA address for full transfer

Offset: 0x4C, reset: 0x0000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DMAB
rw
Toggle Fields.

DMAB

Bits 0-15: DMA register for burst accesses.

TIM5

0x40000C00: General purpose timer

74/93 fields covered. Toggle Registers.

CR1

control register 1

Offset: 0x0, reset: 0x0000, access: read-write

8/8 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CKD
rw
ARPE
rw
CMS
rw
DIR
rw
OPM
rw
URS
rw
UDIS
rw
CEN
rw
Toggle Fields.

CEN

Bit 0: Counter enable.

Allowed values:
0: Disabled: Counter disabled
1: Enabled: Counter enabled

UDIS

Bit 1: Update disable.

Allowed values:
0: Enabled: Update event enabled
1: Disabled: Update event disabled

URS

Bit 2: Update request source.

Allowed values:
0: AnyEvent: Any of counter overflow/underflow, setting UG, or update through slave mode, generates an update interrupt or DMA request
1: CounterOnly: Only counter overflow/underflow generates an update interrupt or DMA request

OPM

Bit 3: One-pulse mode.

Allowed values:
0: Disabled: Counter is not stopped at update event
1: Enabled: Counter stops counting at the next update event (clearing the CEN bit)

DIR

Bit 4: Direction.

Allowed values:
0: Up: Counter used as upcounter
1: Down: Counter used as downcounter

CMS

Bits 5-6: Center-aligned mode selection.

Allowed values:
0: EdgeAligned: The counter counts up or down depending on the direction bit
1: CenterAligned1: The counter counts up and down alternatively. Output compare interrupt flags are set only when the counter is counting down.
2: CenterAligned2: The counter counts up and down alternatively. Output compare interrupt flags are set only when the counter is counting up.
3: CenterAligned3: The counter counts up and down alternatively. Output compare interrupt flags are set both when the counter is counting up or down.

ARPE

Bit 7: Auto-reload preload enable.

Allowed values:
0: Disabled: TIMx_APRR register is not buffered
1: Enabled: TIMx_APRR register is buffered

CKD

Bits 8-9: Clock division.

Allowed values:
0: Div1: t_DTS = t_CK_INT
1: Div2: t_DTS = 2 × t_CK_INT
2: Div4: t_DTS = 4 × t_CK_INT

CR2

control register 2

Offset: 0x4, reset: 0x0000, access: read-write

3/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TI1S
rw
MMS
rw
CCDS
rw
Toggle Fields.

CCDS

Bit 3: Capture/compare DMA selection.

Allowed values:
0: OnCompare: CCx DMA request sent when CCx event occurs
1: OnUpdate: CCx DMA request sent when update event occurs

MMS

Bits 4-6: Master mode selection.

Allowed values:
0: Reset: The UG bit from the TIMx_EGR register is used as trigger output
1: Enable: The counter enable signal, CNT_EN, is used as trigger output
2: Update: The update event is selected as trigger output
3: ComparePulse: The trigger output send a positive pulse when the CC1IF flag it to be set, as soon as a capture or a compare match occurred
4: CompareOC1: OC1REF signal is used as trigger output
5: CompareOC2: OC2REF signal is used as trigger output
6: CompareOC3: OC3REF signal is used as trigger output
7: CompareOC4: OC4REF signal is used as trigger output

TI1S

Bit 7: TI1 selection.

Allowed values:
0: Normal: The TIMx_CH1 pin is connected to TI1 input
1: XOR: The TIMx_CH1, CH2, CH3 pins are connected to TI1 input

SMCR

slave mode control register

Offset: 0x8, reset: 0x0000, access: read-write

7/7 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ETP
rw
ECE
rw
ETPS
rw
ETF
rw
MSM
rw
TS
rw
SMS
rw
Toggle Fields.

SMS

Bits 0-2: Slave mode selection.

Allowed values:
0: Disabled: Slave mode disabled - if CEN = ‘1 then the prescaler is clocked directly by the internal clock.
1: Encoder_Mode_1: Encoder mode 1 - Counter counts up/down on TI2FP1 edge depending on TI1FP2 level.
2: Encoder_Mode_2: Encoder mode 2 - Counter counts up/down on TI1FP2 edge depending on TI2FP1 level.
3: Encoder_Mode_3: Encoder mode 3 - Counter counts up/down on both TI1FP1 and TI2FP2 edges depending on the level of the other input.
4: Reset_Mode: Reset Mode - Rising edge of the selected trigger input (TRGI) reinitializes the counter and generates an update of the registers.
5: Gated_Mode: Gated Mode - The counter clock is enabled when the trigger input (TRGI) is high. The counter stops (but is not reset) as soon as the trigger becomes low. Both start and stop of the counter are controlled.
6: Trigger_Mode: Trigger Mode - The counter starts at a rising edge of the trigger TRGI (but it is not reset). Only the start of the counter is controlled.
7: Ext_Clock_Mode: External Clock Mode 1 - Rising edges of the selected trigger (TRGI) clock the counter.

TS

Bits 4-6: Trigger selection.

Allowed values:
0: ITR0: Internal Trigger 0 (ITR0)
1: ITR1: Internal Trigger 1 (ITR1)
2: ITR2: Internal Trigger 2 (ITR2)
4: TI1F_ED: TI1 Edge Detector (TI1F_ED)
5: TI1FP1: Filtered Timer Input 1 (TI1FP1)
6: TI2FP2: Filtered Timer Input 2 (TI2FP2)
7: ETRF: External Trigger input (ETRF)

MSM

Bit 7: Master/Slave mode.

Allowed values:
0: NoSync: No action
1: Sync: The effect of an event on the trigger input (TRGI) is delayed to allow a perfect synchronization between the current timer and its slaves (through TRGO). It is useful if we want to synchronize several timers on a single external event.

ETF

Bits 8-11: External trigger filter.

Allowed values:
0: NoFilter: No filter, sampling is done at fDTS
1: FCK_INT_N2: fSAMPLING=fCK_INT, N=2
2: FCK_INT_N4: fSAMPLING=fCK_INT, N=4
3: FCK_INT_N8: fSAMPLING=fCK_INT, N=8
4: FDTS_Div2_N6: fSAMPLING=fDTS/2, N=6
5: FDTS_Div2_N8: fSAMPLING=fDTS/2, N=8
6: FDTS_Div4_N6: fSAMPLING=fDTS/4, N=6
7: FDTS_Div4_N8: fSAMPLING=fDTS/4, N=8
8: FDTS_Div8_N6: fSAMPLING=fDTS/8, N=6
9: FDTS_Div8_N8: fSAMPLING=fDTS/8, N=8
10: FDTS_Div16_N5: fSAMPLING=fDTS/16, N=5
11: FDTS_Div16_N6: fSAMPLING=fDTS/16, N=6
12: FDTS_Div16_N8: fSAMPLING=fDTS/16, N=8
13: FDTS_Div32_N5: fSAMPLING=fDTS/32, N=5
14: FDTS_Div32_N6: fSAMPLING=fDTS/32, N=6
15: FDTS_Div32_N8: fSAMPLING=fDTS/32, N=8

ETPS

Bits 12-13: External trigger prescaler.

Allowed values:
0: Div1: Prescaler OFF
1: Div2: ETRP frequency divided by 2
2: Div4: ETRP frequency divided by 4
3: Div8: ETRP frequency divided by 8

ECE

Bit 14: External clock enable.

Allowed values:
0: Disabled: External clock mode 2 disabled
1: Enabled: External clock mode 2 enabled. The counter is clocked by any active edge on the ETRF signal.

ETP

Bit 15: External trigger polarity.

Allowed values:
0: NotInverted: ETR is noninverted, active at high level or rising edge
1: Inverted: ETR is inverted, active at low level or falling edge

DIER

DMA/Interrupt enable register

Offset: 0xC, reset: 0x0000, access: read-write

12/12 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TDE
rw
CC4DE
rw
CC3DE
rw
CC2DE
rw
CC1DE
rw
UDE
rw
TIE
rw
CC4IE
rw
CC3IE
rw
CC2IE
rw
CC1IE
rw
UIE
rw
Toggle Fields.

UIE

Bit 0: Update interrupt enable.

Allowed values:
0: Disabled: Update interrupt disabled
1: Enabled: Update interrupt enabled

CC1IE

Bit 1: Capture/Compare 1 interrupt enable.

Allowed values:
0: Disabled: CCx interrupt disabled
1: Enabled: CCx interrupt enabled

CC2IE

Bit 2: Capture/Compare 2 interrupt enable.

Allowed values:
0: Disabled: CCx interrupt disabled
1: Enabled: CCx interrupt enabled

CC3IE

Bit 3: Capture/Compare 3 interrupt enable.

Allowed values:
0: Disabled: CCx interrupt disabled
1: Enabled: CCx interrupt enabled

CC4IE

Bit 4: Capture/Compare 4 interrupt enable.

Allowed values:
0: Disabled: CCx interrupt disabled
1: Enabled: CCx interrupt enabled

TIE

Bit 6: Trigger interrupt enable.

Allowed values:
0: Disabled: Trigger interrupt disabled
1: Enabled: Trigger interrupt enabled

UDE

Bit 8: Update DMA request enable.

Allowed values:
0: Disabled: Update DMA request disabled
1: Enabled: Update DMA request enabled

CC1DE

Bit 9: Capture/Compare 1 DMA request enable.

Allowed values:
0: Disabled: CCx DMA request disabled
1: Enabled: CCx DMA request enabled

CC2DE

Bit 10: Capture/Compare 2 DMA request enable.

Allowed values:
0: Disabled: CCx DMA request disabled
1: Enabled: CCx DMA request enabled

CC3DE

Bit 11: Capture/Compare 3 DMA request enable.

Allowed values:
0: Disabled: CCx DMA request disabled
1: Enabled: CCx DMA request enabled

CC4DE

Bit 12: Capture/Compare 4 DMA request enable.

Allowed values:
0: Disabled: CCx DMA request disabled
1: Enabled: CCx DMA request enabled

TDE

Bit 14: Trigger DMA request enable.

Allowed values:
0: Disabled: Trigger DMA request disabled
1: Enabled: Trigger DMA request enabled

SR

status register

Offset: 0x10, reset: 0x0000, access: read-write

10/10 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CC4OF
rw
CC3OF
rw
CC2OF
rw
CC1OF
rw
TIF
rw
CC4IF
rw
CC3IF
rw
CC2IF
rw
CC1IF
rw
UIF
rw
Toggle Fields.

UIF

Bit 0: Update interrupt flag.

Allowed values:
0: Clear: No update occurred
1: UpdatePending: Update interrupt pending.

CC1IF

Bit 1: Capture/compare 1 interrupt flag.

Allowed values:
1: Match: If CC1 is an output: The content of the counter TIMx_CNT matches the content of the TIMx_CCR1 register. If CC1 is an input: The counter value has been captured in TIMx_CCR1 register.

CC2IF

Bit 2: Capture/Compare 2 interrupt flag.

Allowed values:
1: Match: If CC1 is an output: The content of the counter TIMx_CNT matches the content of the TIMx_CCR1 register. If CC1 is an input: The counter value has been captured in TIMx_CCR1 register.

CC3IF

Bit 3: Capture/Compare 3 interrupt flag.

Allowed values:
1: Match: If CC1 is an output: The content of the counter TIMx_CNT matches the content of the TIMx_CCR1 register. If CC1 is an input: The counter value has been captured in TIMx_CCR1 register.

CC4IF

Bit 4: Capture/Compare 4 interrupt flag.

Allowed values:
1: Match: If CC1 is an output: The content of the counter TIMx_CNT matches the content of the TIMx_CCR1 register. If CC1 is an input: The counter value has been captured in TIMx_CCR1 register.

TIF

Bit 6: Trigger interrupt flag.

Allowed values:
0: NoTrigger: No trigger event occurred
1: Trigger: Trigger interrupt pending

CC1OF

Bit 9: Capture/Compare 1 overcapture flag.

Allowed values:
1: Overcapture: The counter value has been captured in TIMx_CCRx register while CCxIF flag was already set

CC2OF

Bit 10: Capture/compare 2 overcapture flag.

Allowed values:
1: Overcapture: The counter value has been captured in TIMx_CCRx register while CCxIF flag was already set

CC3OF

Bit 11: Capture/Compare 3 overcapture flag.

Allowed values:
1: Overcapture: The counter value has been captured in TIMx_CCRx register while CCxIF flag was already set

CC4OF

Bit 12: Capture/Compare 4 overcapture flag.

Allowed values:
1: Overcapture: The counter value has been captured in TIMx_CCRx register while CCxIF flag was already set

EGR

event generation register

Offset: 0x14, reset: 0x0000, access: write-only

6/6 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TG
w
CC4G
w
CC3G
w
CC2G
w
CC1G
w
UG
w
Toggle Fields.

UG

Bit 0: Update generation.

Allowed values:
1: Update: Re-initializes the timer counter and generates an update of the reigsters.

CC1G

Bit 1: Capture/compare 1 generation.

Allowed values:
1: Trigger: If CC1 is an output: CC1IF flag is set, Corresponding interrupt or DMA request is sent if enabled. If CC1 is an input: The current value of the counter is captured in TIMx_CCR1 register.

CC2G

Bit 2: Capture/compare 2 generation.

Allowed values:
1: Trigger: If CC1 is an output: CC1IF flag is set, Corresponding interrupt or DMA request is sent if enabled. If CC1 is an input: The current value of the counter is captured in TIMx_CCR1 register.

CC3G

Bit 3: Capture/compare 3 generation.

Allowed values:
1: Trigger: If CC1 is an output: CC1IF flag is set, Corresponding interrupt or DMA request is sent if enabled. If CC1 is an input: The current value of the counter is captured in TIMx_CCR1 register.

CC4G

Bit 4: Capture/compare 4 generation.

Allowed values:
1: Trigger: If CC1 is an output: CC1IF flag is set, Corresponding interrupt or DMA request is sent if enabled. If CC1 is an input: The current value of the counter is captured in TIMx_CCR1 register.

TG

Bit 6: Trigger generation.

Allowed values:
1: Trigger: The TIF flag is set in TIMx_SR register. Related interrupt or DMA transfer can occur if enabled.

CCMR1_Input

capture/compare mode register 1 (input mode)

Offset: 0x18, reset: 0x00000000, access: read-write

4/6 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
IC2F
rw
IC2PSC
rw
CC2S
rw
IC1F
rw
IC1PSC
rw
CC1S
rw
Toggle Fields.

CC1S

Bits 0-1: Capture/Compare 1 selection.

Allowed values:
1: TI1: CC1 channel is configured as input, IC1 is mapped on TI1
2: TI2: CC1 channel is configured as input, IC1 is mapped on TI2
3: TRC: CC1 channel is configured as input, IC1 is mapped on TRC

IC1PSC

Bits 2-3: Input capture 1 prescaler.

IC1F

Bits 4-7: Input capture 1 filter.

Allowed values:
0: NoFilter: No filter, sampling is done at fDTS
1: FCK_INT_N2: fSAMPLING=fCK_INT, N=2
2: FCK_INT_N4: fSAMPLING=fCK_INT, N=4
3: FCK_INT_N8: fSAMPLING=fCK_INT, N=8
4: FDTS_Div2_N6: fSAMPLING=fDTS/2, N=6
5: FDTS_Div2_N8: fSAMPLING=fDTS/2, N=8
6: FDTS_Div4_N6: fSAMPLING=fDTS/4, N=6
7: FDTS_Div4_N8: fSAMPLING=fDTS/4, N=8
8: FDTS_Div8_N6: fSAMPLING=fDTS/8, N=6
9: FDTS_Div8_N8: fSAMPLING=fDTS/8, N=8
10: FDTS_Div16_N5: fSAMPLING=fDTS/16, N=5
11: FDTS_Div16_N6: fSAMPLING=fDTS/16, N=6
12: FDTS_Div16_N8: fSAMPLING=fDTS/16, N=8
13: FDTS_Div32_N5: fSAMPLING=fDTS/32, N=5
14: FDTS_Div32_N6: fSAMPLING=fDTS/32, N=6
15: FDTS_Div32_N8: fSAMPLING=fDTS/32, N=8

CC2S

Bits 8-9: Capture/compare 2 selection.

Allowed values:
1: TI2: CC2 channel is configured as input, IC2 is mapped on TI2
2: TI1: CC2 channel is configured as input, IC2 is mapped on TI1
3: TRC: CC2 channel is configured as input, IC2 is mapped on TRC

IC2PSC

Bits 10-11: Input capture 2 prescaler.

IC2F

Bits 12-15: Input capture 2 filter.

Allowed values: 0-15

CCMR2_Input

capture/compare mode register 2 (input mode)

Offset: 0x1C, reset: 0x00000000, access: read-write

6/6 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
IC4F
rw
IC4PSC
rw
CC4S
rw
IC3F
rw
IC3PSC
rw
CC3S
rw
Toggle Fields.

CC3S

Bits 0-1: Capture/Compare 3 selection.

Allowed values:
1: TI3: CC3 channel is configured as input, IC3 is mapped on TI3
2: TI4: CC3 channel is configured as input, IC3 is mapped on TI4
3: TRC: CC3 channel is configured as input, IC3 is mapped on TRC

IC3PSC

Bits 2-3: Input capture 3 prescaler.

Allowed values: 0-3

IC3F

Bits 4-7: Input capture 3 filter.

Allowed values: 0-15

CC4S

Bits 8-9: Capture/Compare 4 selection.

Allowed values:
1: TI4: CC4 channel is configured as input, IC4 is mapped on TI4
2: TI3: CC4 channel is configured as input, IC4 is mapped on TI3
3: TRC: CC4 channel is configured as input, IC4 is mapped on TRC

IC4PSC

Bits 10-11: Input capture 4 prescaler.

Allowed values: 0-3

IC4F

Bits 12-15: Input capture 4 filter.

Allowed values: 0-15

CCER

capture/compare enable register

Offset: 0x20, reset: 0x0000, access: read-write

0/8 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CC4P
rw
CC4E
rw
CC3P
rw
CC3E
rw
CC2P
rw
CC2E
rw
CC1P
rw
CC1E
rw
Toggle Fields.

CC1E

Bit 0: Capture/Compare 1 output enable.

CC1P

Bit 1: Capture/Compare 1 output Polarity.

CC2E

Bit 4: Capture/Compare 2 output enable.

CC2P

Bit 5: Capture/Compare 2 output Polarity.

CC3E

Bit 8: Capture/Compare 3 output enable.

CC3P

Bit 9: Capture/Compare 3 output Polarity.

CC4E

Bit 12: Capture/Compare 4 output enable.

CC4P

Bit 13: Capture/Compare 3 output Polarity.

CNT

counter

Offset: 0x24, reset: 0x00000000, access: read-write

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CNT
rw
Toggle Fields.

CNT

Bits 0-15: counter value.

Allowed values: 0-65535

PSC

prescaler

Offset: 0x28, reset: 0x0000, access: read-write

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PSC
rw
Toggle Fields.

PSC

Bits 0-15: Prescaler value.

Allowed values: 0-65535

ARR

auto-reload register

Offset: 0x2C, reset: 0x00000000, access: read-write

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ARR
rw
Toggle Fields.

ARR

Bits 0-15: Auto-reload value.

Allowed values: 0-65535

CCR%s

capture/compare register 1

Offset: 0x34, reset: 0x00000000, access: read-write

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CCR
rw
Toggle Fields.

CCR

Bits 0-15: Capture/Compare 1 value.

Allowed values: 0-65535

DCR

DMA control register

Offset: 0x48, reset: 0x0000, access: read-write

2/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DBL
rw
DBA
rw
Toggle Fields.

DBA

Bits 0-4: DMA base address.

Allowed values: 0-31

DBL

Bits 8-12: DMA burst length.

Allowed values: 0-18

DMAR

DMA address for full transfer

Offset: 0x4C, reset: 0x0000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DMAB
rw
Toggle Fields.

DMAB

Bits 0-15: DMA register for burst accesses.

TIM6

0x40001000: Basic timer

13/13 fields covered. Toggle Registers.

CR1

control register 1

Offset: 0x0, reset: 0x0000, access: read-write

5/5 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ARPE
rw
OPM
rw
URS
rw
UDIS
rw
CEN
rw
Toggle Fields.

CEN

Bit 0: Counter enable.

Allowed values:
0: Disabled: Counter disabled
1: Enabled: Counter enabled

UDIS

Bit 1: Update disable.

Allowed values:
0: Enabled: Update event enabled
1: Disabled: Update event disabled

URS

Bit 2: Update request source.

Allowed values:
0: AnyEvent: Any of counter overflow/underflow, setting UG, or update through slave mode, generates an update interrupt or DMA request
1: CounterOnly: Only counter overflow/underflow generates an update interrupt or DMA request

OPM

Bit 3: One-pulse mode.

Allowed values:
0: Disabled: Counter is not stopped at update event
1: Enabled: Counter stops counting at the next update event (clearing the CEN bit)

ARPE

Bit 7: Auto-reload preload enable.

Allowed values:
0: Disabled: TIMx_APRR register is not buffered
1: Enabled: TIMx_APRR register is buffered

CR2

control register 2

Offset: 0x4, reset: 0x0000, access: read-write

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MMS
rw
Toggle Fields.

MMS

Bits 4-6: Master mode selection.

Allowed values:
0: Reset: Use UG bit from TIMx_EGR register
1: Enable: Use CNT bit from TIMx_CEN register
2: Update: Use the update event

DIER

DMA/Interrupt enable register

Offset: 0xC, reset: 0x0000, access: read-write

2/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
UDE
rw
UIE
rw
Toggle Fields.

UIE

Bit 0: Update interrupt enable.

Allowed values:
0: Disabled: Update interrupt disabled
1: Enabled: Update interrupt enabled

UDE

Bit 8: Update DMA request enable.

Allowed values:
0: Disabled: Update DMA request disabled
1: Enabled: Update DMA request enabled

SR

status register

Offset: 0x10, reset: 0x0000, access: read-write

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
UIF
rw
Toggle Fields.

UIF

Bit 0: Update interrupt flag.

Allowed values:
0: Clear: No update occurred
1: UpdatePending: Update interrupt pending.

EGR

event generation register

Offset: 0x14, reset: 0x0000, access: write-only

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
UG
w
Toggle Fields.

UG

Bit 0: Update generation.

Allowed values:
1: Update: Re-initializes the timer counter and generates an update of the reigsters.

CNT

counter

Offset: 0x24, reset: 0x00000000, access: read-write

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CNT
rw
Toggle Fields.

CNT

Bits 0-15: Low counter value.

Allowed values: 0-65536

PSC

prescaler

Offset: 0x28, reset: 0x0000, access: read-write

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PSC
rw
Toggle Fields.

PSC

Bits 0-15: Prescaler value.

Allowed values: 0-65535

ARR

auto-reload register

Offset: 0x2C, reset: 0x00000000, access: read-write

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ARR
rw
Toggle Fields.

ARR

Bits 0-15: Low Auto-reload value.

Allowed values: 0-65536

TIM7

0x40001400: Basic timer

13/13 fields covered. Toggle Registers.

CR1

control register 1

Offset: 0x0, reset: 0x0000, access: read-write

5/5 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ARPE
rw
OPM
rw
URS
rw
UDIS
rw
CEN
rw
Toggle Fields.

CEN

Bit 0: Counter enable.

Allowed values:
0: Disabled: Counter disabled
1: Enabled: Counter enabled

UDIS

Bit 1: Update disable.

Allowed values:
0: Enabled: Update event enabled
1: Disabled: Update event disabled

URS

Bit 2: Update request source.

Allowed values:
0: AnyEvent: Any of counter overflow/underflow, setting UG, or update through slave mode, generates an update interrupt or DMA request
1: CounterOnly: Only counter overflow/underflow generates an update interrupt or DMA request

OPM

Bit 3: One-pulse mode.

Allowed values:
0: Disabled: Counter is not stopped at update event
1: Enabled: Counter stops counting at the next update event (clearing the CEN bit)

ARPE

Bit 7: Auto-reload preload enable.

Allowed values:
0: Disabled: TIMx_APRR register is not buffered
1: Enabled: TIMx_APRR register is buffered

CR2

control register 2

Offset: 0x4, reset: 0x0000, access: read-write

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MMS
rw
Toggle Fields.

MMS

Bits 4-6: Master mode selection.

Allowed values:
0: Reset: Use UG bit from TIMx_EGR register
1: Enable: Use CNT bit from TIMx_CEN register
2: Update: Use the update event

DIER

DMA/Interrupt enable register

Offset: 0xC, reset: 0x0000, access: read-write

2/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
UDE
rw
UIE
rw
Toggle Fields.

UIE

Bit 0: Update interrupt enable.

Allowed values:
0: Disabled: Update interrupt disabled
1: Enabled: Update interrupt enabled

UDE

Bit 8: Update DMA request enable.

Allowed values:
0: Disabled: Update DMA request disabled
1: Enabled: Update DMA request enabled

SR

status register

Offset: 0x10, reset: 0x0000, access: read-write

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
UIF
rw
Toggle Fields.

UIF

Bit 0: Update interrupt flag.

Allowed values:
0: Clear: No update occurred
1: UpdatePending: Update interrupt pending.

EGR

event generation register

Offset: 0x14, reset: 0x0000, access: write-only

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
UG
w
Toggle Fields.

UG

Bit 0: Update generation.

Allowed values:
1: Update: Re-initializes the timer counter and generates an update of the reigsters.

CNT

counter

Offset: 0x24, reset: 0x00000000, access: read-write

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CNT
rw
Toggle Fields.

CNT

Bits 0-15: Low counter value.

Allowed values: 0-65536

PSC

prescaler

Offset: 0x28, reset: 0x0000, access: read-write

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PSC
rw
Toggle Fields.

PSC

Bits 0-15: Prescaler value.

Allowed values: 0-65535

ARR

auto-reload register

Offset: 0x2C, reset: 0x00000000, access: read-write

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ARR
rw
Toggle Fields.

ARR

Bits 0-15: Low Auto-reload value.

Allowed values: 0-65536

TIM8

0x40013400: Advanced timer

77/124 fields covered. Toggle Registers.

CR1

control register 1

Offset: 0x0, reset: 0x0000, access: read-write

8/8 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CKD
rw
ARPE
rw
CMS
rw
DIR
rw
OPM
rw
URS
rw
UDIS
rw
CEN
rw
Toggle Fields.

CEN

Bit 0: Counter enable.

Allowed values:
0: Disabled: Counter disabled
1: Enabled: Counter enabled

UDIS

Bit 1: Update disable.

Allowed values:
0: Enabled: Update event enabled
1: Disabled: Update event disabled

URS

Bit 2: Update request source.

Allowed values:
0: AnyEvent: Any of counter overflow/underflow, setting UG, or update through slave mode, generates an update interrupt or DMA request
1: CounterOnly: Only counter overflow/underflow generates an update interrupt or DMA request

OPM

Bit 3: One-pulse mode.

Allowed values:
0: Disabled: Counter is not stopped at update event
1: Enabled: Counter stops counting at the next update event (clearing the CEN bit)

DIR

Bit 4: Direction.

Allowed values:
0: Up: Counter used as upcounter
1: Down: Counter used as downcounter

CMS

Bits 5-6: Center-aligned mode selection.

Allowed values:
0: EdgeAligned: The counter counts up or down depending on the direction bit
1: CenterAligned1: The counter counts up and down alternatively. Output compare interrupt flags are set only when the counter is counting down.
2: CenterAligned2: The counter counts up and down alternatively. Output compare interrupt flags are set only when the counter is counting up.
3: CenterAligned3: The counter counts up and down alternatively. Output compare interrupt flags are set both when the counter is counting up or down.

ARPE

Bit 7: Auto-reload preload enable.

Allowed values:
0: Disabled: TIMx_APRR register is not buffered
1: Enabled: TIMx_APRR register is buffered

CKD

Bits 8-9: Clock division.

Allowed values:
0: Div1: t_DTS = t_CK_INT
1: Div2: t_DTS = 2 × t_CK_INT
2: Div4: t_DTS = 4 × t_CK_INT

CR2

control register 2

Offset: 0x4, reset: 0x0000, access: read-write

3/12 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
OIS4
rw
OIS3N
rw
OIS3
rw
OIS2N
rw
OIS2
rw
OIS1N
rw
OIS1
rw
TI1S
rw
MMS
rw
CCDS
rw
CCUS
rw
CCPC
rw
Toggle Fields.

CCPC

Bit 0: Capture/compare preloaded control.

CCUS

Bit 2: Capture/compare control update selection.

CCDS

Bit 3: Capture/compare DMA selection.

Allowed values:
0: OnCompare: CCx DMA request sent when CCx event occurs
1: OnUpdate: CCx DMA request sent when update event occurs

MMS

Bits 4-6: Master mode selection.

Allowed values:
0: Reset: The UG bit from the TIMx_EGR register is used as trigger output
1: Enable: The counter enable signal, CNT_EN, is used as trigger output
2: Update: The update event is selected as trigger output
3: ComparePulse: The trigger output send a positive pulse when the CC1IF flag it to be set, as soon as a capture or a compare match occurred
4: CompareOC1: OC1REF signal is used as trigger output
5: CompareOC2: OC2REF signal is used as trigger output
6: CompareOC3: OC3REF signal is used as trigger output
7: CompareOC4: OC4REF signal is used as trigger output

TI1S

Bit 7: TI1 selection.

Allowed values:
0: Normal: The TIMx_CH1 pin is connected to TI1 input
1: XOR: The TIMx_CH1, CH2, CH3 pins are connected to TI1 input

OIS1

Bit 8: Output Idle state 1.

OIS1N

Bit 9: Output Idle state 1.

OIS2

Bit 10: Output Idle state 2.

OIS2N

Bit 11: Output Idle state 2.

OIS3

Bit 12: Output Idle state 3.

OIS3N

Bit 13: Output Idle state 3.

OIS4

Bit 14: Output Idle state 4.

SMCR

slave mode control register

Offset: 0x8, reset: 0x0000, access: read-write

7/7 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ETP
rw
ECE
rw
ETPS
rw
ETF
rw
MSM
rw
TS
rw
SMS
rw
Toggle Fields.

SMS

Bits 0-2: Slave mode selection.

Allowed values:
0: Disabled: Slave mode disabled - if CEN = ‘1 then the prescaler is clocked directly by the internal clock.
1: Encoder_Mode_1: Encoder mode 1 - Counter counts up/down on TI2FP1 edge depending on TI1FP2 level.
2: Encoder_Mode_2: Encoder mode 2 - Counter counts up/down on TI1FP2 edge depending on TI2FP1 level.
3: Encoder_Mode_3: Encoder mode 3 - Counter counts up/down on both TI1FP1 and TI2FP2 edges depending on the level of the other input.
4: Reset_Mode: Reset Mode - Rising edge of the selected trigger input (TRGI) reinitializes the counter and generates an update of the registers.
5: Gated_Mode: Gated Mode - The counter clock is enabled when the trigger input (TRGI) is high. The counter stops (but is not reset) as soon as the trigger becomes low. Both start and stop of the counter are controlled.
6: Trigger_Mode: Trigger Mode - The counter starts at a rising edge of the trigger TRGI (but it is not reset). Only the start of the counter is controlled.
7: Ext_Clock_Mode: External Clock Mode 1 - Rising edges of the selected trigger (TRGI) clock the counter.

TS

Bits 4-6: Trigger selection.

Allowed values:
0: ITR0: Internal Trigger 0 (ITR0)
1: ITR1: Internal Trigger 1 (ITR1)
2: ITR2: Internal Trigger 2 (ITR2)
4: TI1F_ED: TI1 Edge Detector (TI1F_ED)
5: TI1FP1: Filtered Timer Input 1 (TI1FP1)
6: TI2FP2: Filtered Timer Input 2 (TI2FP2)
7: ETRF: External Trigger input (ETRF)

MSM

Bit 7: Master/Slave mode.

Allowed values:
0: NoSync: No action
1: Sync: The effect of an event on the trigger input (TRGI) is delayed to allow a perfect synchronization between the current timer and its slaves (through TRGO). It is useful if we want to synchronize several timers on a single external event.

ETF

Bits 8-11: External trigger filter.

Allowed values:
0: NoFilter: No filter, sampling is done at fDTS
1: FCK_INT_N2: fSAMPLING=fCK_INT, N=2
2: FCK_INT_N4: fSAMPLING=fCK_INT, N=4
3: FCK_INT_N8: fSAMPLING=fCK_INT, N=8
4: FDTS_Div2_N6: fSAMPLING=fDTS/2, N=6
5: FDTS_Div2_N8: fSAMPLING=fDTS/2, N=8
6: FDTS_Div4_N6: fSAMPLING=fDTS/4, N=6
7: FDTS_Div4_N8: fSAMPLING=fDTS/4, N=8
8: FDTS_Div8_N6: fSAMPLING=fDTS/8, N=6
9: FDTS_Div8_N8: fSAMPLING=fDTS/8, N=8
10: FDTS_Div16_N5: fSAMPLING=fDTS/16, N=5
11: FDTS_Div16_N6: fSAMPLING=fDTS/16, N=6
12: FDTS_Div16_N8: fSAMPLING=fDTS/16, N=8
13: FDTS_Div32_N5: fSAMPLING=fDTS/32, N=5
14: FDTS_Div32_N6: fSAMPLING=fDTS/32, N=6
15: FDTS_Div32_N8: fSAMPLING=fDTS/32, N=8

ETPS

Bits 12-13: External trigger prescaler.

Allowed values:
0: Div1: Prescaler OFF
1: Div2: ETRP frequency divided by 2
2: Div4: ETRP frequency divided by 4
3: Div8: ETRP frequency divided by 8

ECE

Bit 14: External clock enable.

Allowed values:
0: Disabled: External clock mode 2 disabled
1: Enabled: External clock mode 2 enabled. The counter is clocked by any active edge on the ETRF signal.

ETP

Bit 15: External trigger polarity.

Allowed values:
0: NotInverted: ETR is noninverted, active at high level or rising edge
1: Inverted: ETR is inverted, active at low level or falling edge

DIER

DMA/Interrupt enable register

Offset: 0xC, reset: 0x0000, access: read-write

12/15 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TDE
rw
COMDE
rw
CC4DE
rw
CC3DE
rw
CC2DE
rw
CC1DE
rw
UDE
rw
BIE
rw
TIE
rw
COMIE
rw
CC4IE
rw
CC3IE
rw
CC2IE
rw
CC1IE
rw
UIE
rw
Toggle Fields.

UIE

Bit 0: Update interrupt enable.

Allowed values:
0: Disabled: Update interrupt disabled
1: Enabled: Update interrupt enabled

CC1IE

Bit 1: Capture/Compare 1 interrupt enable.

Allowed values:
0: Disabled: CCx interrupt disabled
1: Enabled: CCx interrupt enabled

CC2IE

Bit 2: Capture/Compare 2 interrupt enable.

Allowed values:
0: Disabled: CCx interrupt disabled
1: Enabled: CCx interrupt enabled

CC3IE

Bit 3: Capture/Compare 3 interrupt enable.

Allowed values:
0: Disabled: CCx interrupt disabled
1: Enabled: CCx interrupt enabled

CC4IE

Bit 4: Capture/Compare 4 interrupt enable.

Allowed values:
0: Disabled: CCx interrupt disabled
1: Enabled: CCx interrupt enabled

COMIE

Bit 5: COM interrupt enable.

TIE

Bit 6: Trigger interrupt enable.

Allowed values:
0: Disabled: Trigger interrupt disabled
1: Enabled: Trigger interrupt enabled

BIE

Bit 7: Break interrupt enable.

UDE

Bit 8: Update DMA request enable.

Allowed values:
0: Disabled: Update DMA request disabled
1: Enabled: Update DMA request enabled

CC1DE

Bit 9: Capture/Compare 1 DMA request enable.

Allowed values:
0: Disabled: CCx DMA request disabled
1: Enabled: CCx DMA request enabled

CC2DE

Bit 10: Capture/Compare 2 DMA request enable.

Allowed values:
0: Disabled: CCx DMA request disabled
1: Enabled: CCx DMA request enabled

CC3DE

Bit 11: Capture/Compare 3 DMA request enable.

Allowed values:
0: Disabled: CCx DMA request disabled
1: Enabled: CCx DMA request enabled

CC4DE

Bit 12: Capture/Compare 4 DMA request enable.

Allowed values:
0: Disabled: CCx DMA request disabled
1: Enabled: CCx DMA request enabled

COMDE

Bit 13: COM DMA request enable.

TDE

Bit 14: Trigger DMA request enable.

Allowed values:
0: Disabled: Trigger DMA request disabled
1: Enabled: Trigger DMA request enabled

SR

status register

Offset: 0x10, reset: 0x0000, access: read-write

10/12 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CC4OF
rw
CC3OF
rw
CC2OF
rw
CC1OF
rw
BIF
rw
TIF
rw
COMIF
rw
CC4IF
rw
CC3IF
rw
CC2IF
rw
CC1IF
rw
UIF
rw
Toggle Fields.

UIF

Bit 0: Update interrupt flag.

Allowed values:
0: Clear: No update occurred
1: UpdatePending: Update interrupt pending.

CC1IF

Bit 1: Capture/compare 1 interrupt flag.

Allowed values:
1: Match: If CC1 is an output: The content of the counter TIMx_CNT matches the content of the TIMx_CCR1 register. If CC1 is an input: The counter value has been captured in TIMx_CCR1 register.

CC2IF

Bit 2: Capture/Compare 2 interrupt flag.

Allowed values:
1: Match: If CC1 is an output: The content of the counter TIMx_CNT matches the content of the TIMx_CCR1 register. If CC1 is an input: The counter value has been captured in TIMx_CCR1 register.

CC3IF

Bit 3: Capture/Compare 3 interrupt flag.

Allowed values:
1: Match: If CC1 is an output: The content of the counter TIMx_CNT matches the content of the TIMx_CCR1 register. If CC1 is an input: The counter value has been captured in TIMx_CCR1 register.

CC4IF

Bit 4: Capture/Compare 4 interrupt flag.

Allowed values:
1: Match: If CC1 is an output: The content of the counter TIMx_CNT matches the content of the TIMx_CCR1 register. If CC1 is an input: The counter value has been captured in TIMx_CCR1 register.

COMIF

Bit 5: COM interrupt flag.

TIF

Bit 6: Trigger interrupt flag.

Allowed values:
0: NoTrigger: No trigger event occurred
1: Trigger: Trigger interrupt pending

BIF

Bit 7: Break interrupt flag.

CC1OF

Bit 9: Capture/Compare 1 overcapture flag.

Allowed values:
1: Overcapture: The counter value has been captured in TIMx_CCRx register while CCxIF flag was already set

CC2OF

Bit 10: Capture/compare 2 overcapture flag.

Allowed values:
1: Overcapture: The counter value has been captured in TIMx_CCRx register while CCxIF flag was already set

CC3OF

Bit 11: Capture/Compare 3 overcapture flag.

Allowed values:
1: Overcapture: The counter value has been captured in TIMx_CCRx register while CCxIF flag was already set

CC4OF

Bit 12: Capture/Compare 4 overcapture flag.

Allowed values:
1: Overcapture: The counter value has been captured in TIMx_CCRx register while CCxIF flag was already set

EGR

event generation register

Offset: 0x14, reset: 0x0000, access: write-only

6/8 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
BG
w
TG
w
COMG
w
CC4G
w
CC3G
w
CC2G
w
CC1G
w
UG
w
Toggle Fields.

UG

Bit 0: Update generation.

Allowed values:
1: Update: Re-initializes the timer counter and generates an update of the reigsters.

CC1G

Bit 1: Capture/compare 1 generation.

Allowed values:
1: Trigger: If CC1 is an output: CC1IF flag is set, Corresponding interrupt or DMA request is sent if enabled. If CC1 is an input: The current value of the counter is captured in TIMx_CCR1 register.

CC2G

Bit 2: Capture/compare 2 generation.

Allowed values:
1: Trigger: If CC1 is an output: CC1IF flag is set, Corresponding interrupt or DMA request is sent if enabled. If CC1 is an input: The current value of the counter is captured in TIMx_CCR1 register.

CC3G

Bit 3: Capture/compare 3 generation.

Allowed values:
1: Trigger: If CC1 is an output: CC1IF flag is set, Corresponding interrupt or DMA request is sent if enabled. If CC1 is an input: The current value of the counter is captured in TIMx_CCR1 register.

CC4G

Bit 4: Capture/compare 4 generation.

Allowed values:
1: Trigger: If CC1 is an output: CC1IF flag is set, Corresponding interrupt or DMA request is sent if enabled. If CC1 is an input: The current value of the counter is captured in TIMx_CCR1 register.

COMG

Bit 5: Capture/Compare control update generation.

TG

Bit 6: Trigger generation.

Allowed values:
1: Trigger: The TIF flag is set in TIMx_SR register. Related interrupt or DMA transfer can occur if enabled.

BG

Bit 7: Break generation.

CCMR1_Input

capture/compare mode register 1 (input mode)

Offset: 0x18, reset: 0x00000000, access: read-write

4/6 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
IC2F
rw
IC2PSC
rw
CC2S
rw
IC1F
rw
IC1PSC
rw
CC1S
rw
Toggle Fields.

CC1S

Bits 0-1: Capture/Compare 1 selection.

Allowed values:
1: TI1: CC1 channel is configured as input, IC1 is mapped on TI1
2: TI2: CC1 channel is configured as input, IC1 is mapped on TI2
3: TRC: CC1 channel is configured as input, IC1 is mapped on TRC

IC1PSC

Bits 2-3: Input capture 1 prescaler.

IC1F

Bits 4-7: Input capture 1 filter.

Allowed values:
0: NoFilter: No filter, sampling is done at fDTS
1: FCK_INT_N2: fSAMPLING=fCK_INT, N=2
2: FCK_INT_N4: fSAMPLING=fCK_INT, N=4
3: FCK_INT_N8: fSAMPLING=fCK_INT, N=8
4: FDTS_Div2_N6: fSAMPLING=fDTS/2, N=6
5: FDTS_Div2_N8: fSAMPLING=fDTS/2, N=8
6: FDTS_Div4_N6: fSAMPLING=fDTS/4, N=6
7: FDTS_Div4_N8: fSAMPLING=fDTS/4, N=8
8: FDTS_Div8_N6: fSAMPLING=fDTS/8, N=6
9: FDTS_Div8_N8: fSAMPLING=fDTS/8, N=8
10: FDTS_Div16_N5: fSAMPLING=fDTS/16, N=5
11: FDTS_Div16_N6: fSAMPLING=fDTS/16, N=6
12: FDTS_Div16_N8: fSAMPLING=fDTS/16, N=8
13: FDTS_Div32_N5: fSAMPLING=fDTS/32, N=5
14: FDTS_Div32_N6: fSAMPLING=fDTS/32, N=6
15: FDTS_Div32_N8: fSAMPLING=fDTS/32, N=8

CC2S

Bits 8-9: Capture/Compare 2 selection.

Allowed values:
1: TI2: CC2 channel is configured as input, IC2 is mapped on TI2
2: TI1: CC2 channel is configured as input, IC2 is mapped on TI1
3: TRC: CC2 channel is configured as input, IC2 is mapped on TRC

IC2PSC

Bits 10-11: Input capture 2 prescaler.

IC2F

Bits 12-15: Input capture 2 filter.

Allowed values: 0-15

CCMR2_Input

capture/compare mode register 2 (input mode)

Offset: 0x1C, reset: 0x00000000, access: read-write

6/6 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
IC4F
rw
IC4PSC
rw
CC4S
rw
IC3F
rw
IC3PSC
rw
CC3S
rw
Toggle Fields.

CC3S

Bits 0-1: Capture/compare 3 selection.

Allowed values:
1: TI3: CC3 channel is configured as input, IC3 is mapped on TI3
2: TI4: CC3 channel is configured as input, IC3 is mapped on TI4
3: TRC: CC3 channel is configured as input, IC3 is mapped on TRC

IC3PSC

Bits 2-3: Input capture 3 prescaler.

Allowed values: 0-3

IC3F

Bits 4-7: Input capture 3 filter.

Allowed values: 0-15

CC4S

Bits 8-9: Capture/Compare 4 selection.

Allowed values:
1: TI4: CC4 channel is configured as input, IC4 is mapped on TI4
2: TI3: CC4 channel is configured as input, IC4 is mapped on TI3
3: TRC: CC4 channel is configured as input, IC4 is mapped on TRC

IC4PSC

Bits 10-11: Input capture 4 prescaler.

Allowed values: 0-3

IC4F

Bits 12-15: Input capture 4 filter.

Allowed values: 0-15

CCER

capture/compare enable register

Offset: 0x20, reset: 0x0000, access: read-write

0/14 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CC4P
rw
CC4E
rw
CC3NP
rw
CC3NE
rw
CC3P
rw
CC3E
rw
CC2NP
rw
CC2NE
rw
CC2P
rw
CC2E
rw
CC1NP
rw
CC1NE
rw
CC1P
rw
CC1E
rw
Toggle Fields.

CC1E

Bit 0: Capture/Compare 1 output enable.

CC1P

Bit 1: Capture/Compare 1 output Polarity.

CC1NE

Bit 2: Capture/Compare 1 complementary output enable.

CC1NP

Bit 3: Capture/Compare 1 output Polarity.

CC2E

Bit 4: Capture/Compare 2 output enable.

CC2P

Bit 5: Capture/Compare 2 output Polarity.

CC2NE

Bit 6: Capture/Compare 2 complementary output enable.

CC2NP

Bit 7: Capture/Compare 2 output Polarity.

CC3E

Bit 8: Capture/Compare 3 output enable.

CC3P

Bit 9: Capture/Compare 3 output Polarity.

CC3NE

Bit 10: Capture/Compare 3 complementary output enable.

CC3NP

Bit 11: Capture/Compare 3 output Polarity.

CC4E

Bit 12: Capture/Compare 4 output enable.

CC4P

Bit 13: Capture/Compare 3 output Polarity.

CNT

counter

Offset: 0x24, reset: 0x00000000, access: read-write

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CNT
rw
Toggle Fields.

CNT

Bits 0-15: counter value.

Allowed values: 0-65535

PSC

prescaler

Offset: 0x28, reset: 0x0000, access: read-write

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PSC
rw
Toggle Fields.

PSC

Bits 0-15: Prescaler value.

Allowed values: 0-65535

ARR

auto-reload register

Offset: 0x2C, reset: 0x00000000, access: read-write

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ARR
rw
Toggle Fields.

ARR

Bits 0-15: Auto-reload value.

Allowed values: 0-65535

RCR

repetition counter register

Offset: 0x30, reset: 0x0000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
REP
rw
Toggle Fields.

REP

Bits 0-7: Repetition counter value.

CCR%s

capture/compare register 1

Offset: 0x34, reset: 0x00000000, access: read-write

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CCR
rw
Toggle Fields.

CCR

Bits 0-15: Capture/Compare 1 value.

Allowed values: 0-65535

BDTR

break and dead-time register

Offset: 0x44, reset: 0x0000, access: read-write

3/8 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MOE
rw
AOE
rw
BKP
rw
BKE
rw
OSSR
rw
OSSI
rw
LOCK
rw
DTG
rw
Toggle Fields.

DTG

Bits 0-7: Dead-time generator setup.

LOCK

Bits 8-9: Lock configuration.

OSSI

Bit 10: Off-state selection for Idle mode.

Allowed values:
0: Disabled: When inactive, OC/OCN outputs are disabled
1: IdleLevel: When inactive, OC/OCN outputs are forced to idle level

OSSR

Bit 11: Off-state selection for Run mode.

Allowed values:
0: Disabled: When inactive, OC/OCN outputs are disabled
1: IdleLevel: When inactive, OC/OCN outputs are enabled with their inactive level

BKE

Bit 12: Break enable.

BKP

Bit 13: Break polarity.

AOE

Bit 14: Automatic output enable.

MOE

Bit 15: Main output enable.

Allowed values:
0: DisabledIdle: OC/OCN are disabled or forced idle depending on OSSI
1: Enabled: OC/OCN are enabled if CCxE/CCxNE are set

DCR

DMA control register

Offset: 0x48, reset: 0x0000, access: read-write

2/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DBL
rw
DBA
rw
Toggle Fields.

DBA

Bits 0-4: DMA base address.

Allowed values: 0-31

DBL

Bits 8-12: DMA burst length.

Allowed values: 0-18

DMAR

DMA address for full transfer

Offset: 0x4C, reset: 0x0000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DMAB
rw
Toggle Fields.

DMAB

Bits 0-15: DMA register for burst accesses.

TIM9

0x40014C00: General purpose timer

10/48 fields covered. Toggle Registers.

CR1

control register 1

Offset: 0x0, reset: 0x0000, access: read-write

6/6 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CKD
rw
ARPE
rw
OPM
rw
URS
rw
UDIS
rw
CEN
rw
Toggle Fields.

CEN

Bit 0: Counter enable.

Allowed values:
0: Disabled: Counter disabled
1: Enabled: Counter enabled

UDIS

Bit 1: Update disable.

Allowed values:
0: Enabled: Update event enabled
1: Disabled: Update event disabled

URS

Bit 2: Update request source.

Allowed values:
0: AnyEvent: Any of counter overflow/underflow, setting UG, or update through slave mode, generates an update interrupt or DMA request
1: CounterOnly: Only counter overflow/underflow generates an update interrupt or DMA request

OPM

Bit 3: One-pulse mode.

Allowed values:
0: Disabled: Counter is not stopped at update event
1: Enabled: Counter stops counting at the next update event (clearing the CEN bit)

ARPE

Bit 7: Auto-reload preload enable.

Allowed values:
0: Disabled: TIMx_APRR register is not buffered
1: Enabled: TIMx_APRR register is buffered

CKD

Bits 8-9: Clock division.

Allowed values:
0: Div1: t_DTS = t_CK_INT
1: Div2: t_DTS = 2 × t_CK_INT
2: Div4: t_DTS = 4 × t_CK_INT

CR2

control register 2

Offset: 0x4, reset: 0x0000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MMS
rw
Toggle Fields.

MMS

Bits 4-6: Master mode selection.

SMCR

slave mode control register

Offset: 0x8, reset: 0x0000, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MSM
rw
TS
rw
SMS
rw
Toggle Fields.

SMS

Bits 0-2: Slave mode selection.

TS

Bits 4-6: Trigger selection.

MSM

Bit 7: Master/Slave mode.

DIER

DMA/Interrupt enable register

Offset: 0xC, reset: 0x0000, access: read-write

1/4 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TIE
rw
CC2IE
rw
CC1IE
rw
UIE
rw
Toggle Fields.

UIE

Bit 0: Update interrupt enable.

Allowed values:
0: Disabled: Update interrupt disabled
1: Enabled: Update interrupt enabled

CC1IE

Bit 1: Capture/Compare 1 interrupt enable.

CC2IE

Bit 2: Capture/Compare 2 interrupt enable.

TIE

Bit 6: Trigger interrupt enable.

SR

status register

Offset: 0x10, reset: 0x0000, access: read-write

1/6 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CC2OF
rw
CC1OF
rw
TIF
rw
CC2IF
rw
CC1IF
rw
UIF
rw
Toggle Fields.

UIF

Bit 0: Update interrupt flag.

Allowed values:
0: Clear: No update occurred
1: UpdatePending: Update interrupt pending.

CC1IF

Bit 1: Capture/compare 1 interrupt flag.

CC2IF

Bit 2: Capture/Compare 2 interrupt flag.

TIF

Bit 6: Trigger interrupt flag.

CC1OF

Bit 9: Capture/Compare 1 overcapture flag.

CC2OF

Bit 10: Capture/compare 2 overcapture flag.

EGR

event generation register

Offset: 0x14, reset: 0x0000, access: write-only

1/4 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TG
w
CC2G
w
CC1G
w
UG
w
Toggle Fields.

UG

Bit 0: Update generation.

Allowed values:
1: Update: Re-initializes the timer counter and generates an update of the reigsters.

CC1G

Bit 1: Capture/compare 1 generation.

CC2G

Bit 2: Capture/compare 2 generation.

TG

Bit 6: Trigger generation.

CCMR1_Input

capture/compare mode register 1 (input mode)

Offset: 0x18, reset: 0x00000000, access: read-write

0/6 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
IC2F
rw
IC2PSC
rw
CC2S
rw
IC1F
rw
IC1PSC
rw
CC1S
rw
Toggle Fields.

CC1S

Bits 0-1: Capture/Compare 1 selection.

IC1PSC

Bits 2-3: Input capture 1 prescaler.

IC1F

Bits 4-7: Input capture 1 filter.

CC2S

Bits 8-9: Capture/Compare 2 selection.

IC2PSC

Bits 10-11: Input capture 2 prescaler.

IC2F

Bits 12-15: Input capture 2 filter.

CCER

capture/compare enable register

Offset: 0x20, reset: 0x0000, access: read-write

0/6 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CC2NP
rw
CC2P
rw
CC2E
rw
CC1NP
rw
CC1P
rw
CC1E
rw
Toggle Fields.

CC1E

Bit 0: Capture/Compare 1 output enable.

CC1P

Bit 1: Capture/Compare 1 output Polarity.

CC1NP

Bit 3: Capture/Compare 1 output Polarity.

CC2E

Bit 4: Capture/Compare 2 output enable.

CC2P

Bit 5: Capture/Compare 2 output Polarity.

CC2NP

Bit 7: Capture/Compare 2 output Polarity.

CNT

counter

Offset: 0x24, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CNT
rw
Toggle Fields.

CNT

Bits 0-15: counter value.

PSC

prescaler

Offset: 0x28, reset: 0x0000, access: read-write

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PSC
rw
Toggle Fields.

PSC

Bits 0-15: Prescaler value.

Allowed values: 0-65535

ARR

auto-reload register

Offset: 0x2C, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ARR
rw
Toggle Fields.

ARR

Bits 0-15: Auto-reload value.

CCR%s

capture/compare register 1

Offset: 0x34, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CCR
rw
Toggle Fields.

CCR

Bits 0-15: Capture/Compare 1 value.

UART4

0x40004C00: Universal asynchronous receiver transmitter

34/37 fields covered. Toggle Registers.

SR

UART4_SR

Offset: 0x0, reset: 0x0, access: Unspecified

6/9 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LBD
rw
TXE
r
TC
rw
RXNE
rw
IDLE
r
ORE
r
NE
r
FE
r
PE
r
Toggle Fields.

PE

Bit 0: Parity error.

FE

Bit 1: Framing error.

NE

Bit 2: Noise error flag.

ORE

Bit 3: Overrun error.

IDLE

Bit 4: IDLE line detected.

RXNE

Bit 5: Read data register not empty.

TC

Bit 6: Transmission complete.

TXE

Bit 7: Transmit data register empty.

LBD

Bit 8: LIN break detection flag.

DR

UART4_DR

Offset: 0x4, reset: 0x0, access: read-write

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DR
rw
Toggle Fields.

DR

Bits 0-8: DR.

Allowed values: 0-511

BRR

UART4_BRR

Offset: 0x8, reset: 0x0, access: read-write

2/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DIV_Mantissa
rw
DIV_Fraction
rw
Toggle Fields.

DIV_Fraction

Bits 0-3: DIV_Fraction.

Allowed values: 0-15

DIV_Mantissa

Bits 4-15: DIV_Mantissa.

Allowed values: 0-4095

CR1

UART4_CR1

Offset: 0xC, reset: 0x0, access: read-write

14/14 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
UE
rw
M
rw
WAKE
rw
PCE
rw
PS
rw
PEIE
rw
TXEIE
rw
TCIE
rw
RXNEIE
rw
IDLEIE
rw
TE
rw
RE
rw
RWU
rw
SBK
rw
Toggle Fields.

SBK

Bit 0: Send break.

Allowed values:
0: NoBreak: No break character is transmitted
1: Break: Break character transmitted

RWU

Bit 1: Receiver wakeup.

Allowed values:
0: Active: Receiver in active mode
1: Mute: Receiver in mute mode

RE

Bit 2: Receiver enable.

Allowed values:
0: Disabled: Receiver disabled
1: Enabled: Receiver enabled

TE

Bit 3: Transmitter enable.

Allowed values:
0: Disabled: Transmitter disabled
1: Enabled: Transmitter enabled

IDLEIE

Bit 4: IDLE interrupt enable.

Allowed values:
0: Disabled: IDLE interrupt disabled
1: Enabled: IDLE interrupt enabled

RXNEIE

Bit 5: RXNE interrupt enable.

Allowed values:
0: Disabled: RXNE interrupt disabled
1: Enabled: RXNE interrupt enabled

TCIE

Bit 6: Transmission complete interrupt enable.

Allowed values:
0: Disabled: TC interrupt disabled
1: Enabled: TC interrupt enabled

TXEIE

Bit 7: TXE interrupt enable.

Allowed values:
0: Disabled: TXE interrupt disabled
1: Enabled: TXE interrupt enabled

PEIE

Bit 8: PE interrupt enable.

Allowed values:
0: Disabled: PE interrupt disabled
1: Enabled: PE interrupt enabled

PS

Bit 9: Parity selection.

Allowed values:
0: Even: Even parity
1: Odd: Odd parity

PCE

Bit 10: Parity control enable.

Allowed values:
0: Disabled: Parity control disabled
1: Enabled: Parity control enabled

WAKE

Bit 11: Wakeup method.

Allowed values:
0: IdleLine: USART wakeup on idle line
1: AddressMark: USART wakeup on address mark

M

Bit 12: Word length.

Allowed values:
0: M8: 8 data bits
1: M9: 9 data bits

UE

Bit 13: USART enable.

Allowed values:
0: Disabled: USART prescaler and outputs disabled
1: Enabled: USART enabled

CR2

UART4_CR2

Offset: 0x10, reset: 0x0, access: read-write

5/5 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LINEN
rw
STOP
rw
LBDIE
rw
LBDL
rw
ADD
rw
Toggle Fields.

ADD

Bits 0-3: Address of the USART node.

Allowed values: 0-15

LBDL

Bit 5: lin break detection length.

Allowed values:
0: LBDL10: 10-bit break detection
1: LBDL11: 11-bit break detection

LBDIE

Bit 6: LIN break detection interrupt enable.

Allowed values:
0: Disabled: LIN break detection interrupt disabled
1: Enabled: LIN break detection interrupt enabled

STOP

Bits 12-13: STOP bits.

Allowed values:
0: Stop1: 1 stop bit
2: Stop2: 2 stop bits

LINEN

Bit 14: LIN mode enable.

Allowed values:
0: Disabled: LIN mode disabled
1: Enabled: LIN mode enabled

CR3

UART4_CR3

Offset: 0x14, reset: 0x0, access: read-write

6/6 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DMAT
rw
DMAR
rw
HDSEL
rw
IRLP
rw
IREN
rw
EIE
rw
Toggle Fields.

EIE

Bit 0: Error interrupt enable.

Allowed values:
0: Disabled: Error interrupt disabled
1: Enabled: Error interrupt enabled

IREN

Bit 1: IrDA mode enable.

Allowed values:
0: Disabled: IrDA disabled
1: Enabled: IrDA enabled

IRLP

Bit 2: IrDA low-power.

Allowed values:
0: Normal: Normal mode
1: LowPower: Low-power mode

HDSEL

Bit 3: Half-duplex selection.

Allowed values:
0: FullDuplex: Half duplex mode is not selected
1: HalfDuplex: Half duplex mode is selected

DMAR

Bit 6: DMA enable receiver.

Allowed values:
0: Disabled: DMA mode is disabled for reception
1: Enabled: DMA mode is enabled for reception

DMAT

Bit 7: DMA enable transmitter.

Allowed values:
0: Disabled: DMA mode is disabled for transmission
1: Enabled: DMA mode is enabled for transmission

UART5

0x40005000: Universal asynchronous receiver transmitter

34/37 fields covered. Toggle Registers.

SR

UART4_SR

Offset: 0x0, reset: 0x0, access: Unspecified

6/9 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LBD
rw
TXE
r
TC
rw
RXNE
rw
IDLE
r
ORE
r
NE
r
FE
r
PE
r
Toggle Fields.

PE

Bit 0: Parity error.

FE

Bit 1: Framing error.

NE

Bit 2: Noise error flag.

ORE

Bit 3: Overrun error.

IDLE

Bit 4: IDLE line detected.

RXNE

Bit 5: Read data register not empty.

TC

Bit 6: Transmission complete.

TXE

Bit 7: Transmit data register empty.

LBD

Bit 8: LIN break detection flag.

DR

UART4_DR

Offset: 0x4, reset: 0x0, access: read-write

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DR
rw
Toggle Fields.

DR

Bits 0-8: DR.

Allowed values: 0-511

BRR

UART4_BRR

Offset: 0x8, reset: 0x0, access: read-write

2/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DIV_Mantissa
rw
DIV_Fraction
rw
Toggle Fields.

DIV_Fraction

Bits 0-3: DIV_Fraction.

Allowed values: 0-15

DIV_Mantissa

Bits 4-15: DIV_Mantissa.

Allowed values: 0-4095

CR1

UART4_CR1

Offset: 0xC, reset: 0x0, access: read-write

14/14 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
UE
rw
M
rw
WAKE
rw
PCE
rw
PS
rw
PEIE
rw
TXEIE
rw
TCIE
rw
RXNEIE
rw
IDLEIE
rw
TE
rw
RE
rw
RWU
rw
SBK
rw
Toggle Fields.

SBK

Bit 0: Send break.

Allowed values:
0: NoBreak: No break character is transmitted
1: Break: Break character transmitted

RWU

Bit 1: Receiver wakeup.

Allowed values:
0: Active: Receiver in active mode
1: Mute: Receiver in mute mode

RE

Bit 2: Receiver enable.

Allowed values:
0: Disabled: Receiver disabled
1: Enabled: Receiver enabled

TE

Bit 3: Transmitter enable.

Allowed values:
0: Disabled: Transmitter disabled
1: Enabled: Transmitter enabled

IDLEIE

Bit 4: IDLE interrupt enable.

Allowed values:
0: Disabled: IDLE interrupt disabled
1: Enabled: IDLE interrupt enabled

RXNEIE

Bit 5: RXNE interrupt enable.

Allowed values:
0: Disabled: RXNE interrupt disabled
1: Enabled: RXNE interrupt enabled

TCIE

Bit 6: Transmission complete interrupt enable.

Allowed values:
0: Disabled: TC interrupt disabled
1: Enabled: TC interrupt enabled

TXEIE

Bit 7: TXE interrupt enable.

Allowed values:
0: Disabled: TXE interrupt disabled
1: Enabled: TXE interrupt enabled

PEIE

Bit 8: PE interrupt enable.

Allowed values:
0: Disabled: PE interrupt disabled
1: Enabled: PE interrupt enabled

PS

Bit 9: Parity selection.

Allowed values:
0: Even: Even parity
1: Odd: Odd parity

PCE

Bit 10: Parity control enable.

Allowed values:
0: Disabled: Parity control disabled
1: Enabled: Parity control enabled

WAKE

Bit 11: Wakeup method.

Allowed values:
0: IdleLine: USART wakeup on idle line
1: AddressMark: USART wakeup on address mark

M

Bit 12: Word length.

Allowed values:
0: M8: 8 data bits
1: M9: 9 data bits

UE

Bit 13: USART enable.

Allowed values:
0: Disabled: USART prescaler and outputs disabled
1: Enabled: USART enabled

CR2

UART4_CR2

Offset: 0x10, reset: 0x0, access: read-write

5/5 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LINEN
rw
STOP
rw
LBDIE
rw
LBDL
rw
ADD
rw
Toggle Fields.

ADD

Bits 0-3: Address of the USART node.

Allowed values: 0-15

LBDL

Bit 5: lin break detection length.

Allowed values:
0: LBDL10: 10-bit break detection
1: LBDL11: 11-bit break detection

LBDIE

Bit 6: LIN break detection interrupt enable.

Allowed values:
0: Disabled: LIN break detection interrupt disabled
1: Enabled: LIN break detection interrupt enabled

STOP

Bits 12-13: STOP bits.

Allowed values:
0: Stop1: 1 stop bit
2: Stop2: 2 stop bits

LINEN

Bit 14: LIN mode enable.

Allowed values:
0: Disabled: LIN mode disabled
1: Enabled: LIN mode enabled

CR3

UART4_CR3

Offset: 0x14, reset: 0x0, access: read-write

6/6 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DMAT
rw
DMAR
rw
HDSEL
rw
IRLP
rw
IREN
rw
EIE
rw
Toggle Fields.

EIE

Bit 0: Error interrupt enable.

Allowed values:
0: Disabled: Error interrupt disabled
1: Enabled: Error interrupt enabled

IREN

Bit 1: IrDA mode enable.

Allowed values:
0: Disabled: IrDA disabled
1: Enabled: IrDA enabled

IRLP

Bit 2: IrDA low-power.

Allowed values:
0: Normal: Normal mode
1: LowPower: Low-power mode

HDSEL

Bit 3: Half-duplex selection.

Allowed values:
0: FullDuplex: Half duplex mode is not selected
1: HalfDuplex: Half duplex mode is selected

DMAR

Bit 6: DMA enable receiver.

Allowed values:
0: Disabled: DMA mode is disabled for reception
1: Enabled: DMA mode is enabled for reception

DMAT

Bit 7: DMA enable transmitter.

Allowed values:
0: Disabled: DMA mode is disabled for transmission
1: Enabled: DMA mode is enabled for transmission

USART1

0x40013800: Universal synchronous asynchronous receiver transmitter

42/49 fields covered. Toggle Registers.

SR

Status register

Offset: 0x0, reset: 0x00C0, access: Unspecified

6/10 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CTS
rw
LBD
rw
TXE
r
TC
rw
RXNE
rw
IDLE
r
ORE
r
NE
r
FE
r
PE
r
Toggle Fields.

PE

Bit 0: Parity error.

FE

Bit 1: Framing error.

NE

Bit 2: Noise error flag.

ORE

Bit 3: Overrun error.

IDLE

Bit 4: IDLE line detected.

RXNE

Bit 5: Read data register not empty.

TC

Bit 6: Transmission complete.

TXE

Bit 7: Transmit data register empty.

LBD

Bit 8: LIN break detection flag.

CTS

Bit 9: CTS flag.

DR

Data register

Offset: 0x4, reset: 0x00000000, access: read-write

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DR
rw
Toggle Fields.

DR

Bits 0-8: Data value.

Allowed values: 0-511

BRR

Baud rate register

Offset: 0x8, reset: 0x0000, access: read-write

2/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DIV_Mantissa
rw
DIV_Fraction
rw
Toggle Fields.

DIV_Fraction

Bits 0-3: fraction of USARTDIV.

Allowed values: 0-15

DIV_Mantissa

Bits 4-15: mantissa of USARTDIV.

Allowed values: 0-4095

CR1

Control register 1

Offset: 0xC, reset: 0x0000, access: read-write

14/14 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
UE
rw
M
rw
WAKE
rw
PCE
rw
PS
rw
PEIE
rw
TXEIE
rw
TCIE
rw
RXNEIE
rw
IDLEIE
rw
TE
rw
RE
rw
RWU
rw
SBK
rw
Toggle Fields.

SBK

Bit 0: Send break.

Allowed values:
0: NoBreak: No break character is transmitted
1: Break: Break character transmitted

RWU

Bit 1: Receiver wakeup.

Allowed values:
0: Active: Receiver in active mode
1: Mute: Receiver in mute mode

RE

Bit 2: Receiver enable.

Allowed values:
0: Disabled: Receiver disabled
1: Enabled: Receiver enabled

TE

Bit 3: Transmitter enable.

Allowed values:
0: Disabled: Transmitter disabled
1: Enabled: Transmitter enabled

IDLEIE

Bit 4: IDLE interrupt enable.

Allowed values:
0: Disabled: IDLE interrupt disabled
1: Enabled: IDLE interrupt enabled

RXNEIE

Bit 5: RXNE interrupt enable.

Allowed values:
0: Disabled: RXNE interrupt disabled
1: Enabled: RXNE interrupt enabled

TCIE

Bit 6: Transmission complete interrupt enable.

Allowed values:
0: Disabled: TC interrupt disabled
1: Enabled: TC interrupt enabled

TXEIE

Bit 7: TXE interrupt enable.

Allowed values:
0: Disabled: TXE interrupt disabled
1: Enabled: TXE interrupt enabled

PEIE

Bit 8: PE interrupt enable.

Allowed values:
0: Disabled: PE interrupt disabled
1: Enabled: PE interrupt enabled

PS

Bit 9: Parity selection.

Allowed values:
0: Even: Even parity
1: Odd: Odd parity

PCE

Bit 10: Parity control enable.

Allowed values:
0: Disabled: Parity control disabled
1: Enabled: Parity control enabled

WAKE

Bit 11: Wakeup method.

Allowed values:
0: IdleLine: USART wakeup on idle line
1: AddressMark: USART wakeup on address mark

M

Bit 12: Word length.

Allowed values:
0: M8: 8 data bits
1: M9: 9 data bits

UE

Bit 13: USART enable.

Allowed values:
0: Disabled: USART prescaler and outputs disabled
1: Enabled: USART enabled

CR2

Control register 2

Offset: 0x10, reset: 0x0000, access: read-write

8/9 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LINEN
rw
STOP
rw
CLKEN
rw
CPOL
rw
CPHA
rw
LBCL
rw
LBDIE
rw
LBDL
rw
ADD
rw
Toggle Fields.

ADD

Bits 0-3: Address of the USART node.

Allowed values: 0-15

LBDL

Bit 5: lin break detection length.

Allowed values:
0: LBDL10: 10-bit break detection
1: LBDL11: 11-bit break detection

LBDIE

Bit 6: LIN break detection interrupt enable.

Allowed values:
0: Disabled: LIN break detection interrupt disabled
1: Enabled: LIN break detection interrupt enabled

LBCL

Bit 8: Last bit clock pulse.

CPHA

Bit 9: Clock phase.

Allowed values:
0: First: The first clock transition is the first data capture edge
1: Second: The second clock transition is the first data capture edge

CPOL

Bit 10: Clock polarity.

Allowed values:
0: Low: Steady low value on CK pin outside transmission window
1: High: Steady high value on CK pin outside transmission window

CLKEN

Bit 11: Clock enable.

Allowed values:
0: Disabled: CK pin disabled
1: Enabled: CK pin enabled

STOP

Bits 12-13: STOP bits.

Allowed values:
0: Stop1: 1 stop bit
1: Stop0p5: 0.5 stop bits
2: Stop2: 2 stop bits
3: Stop1p5: 1.5 stop bits

LINEN

Bit 14: LIN mode enable.

Allowed values:
0: Disabled: LIN mode disabled
1: Enabled: LIN mode enabled

CR3

Control register 3

Offset: 0x14, reset: 0x0000, access: read-write

11/11 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CTSIE
rw
CTSE
rw
RTSE
rw
DMAT
rw
DMAR
rw
SCEN
rw
NACK
rw
HDSEL
rw
IRLP
rw
IREN
rw
EIE
rw
Toggle Fields.

EIE

Bit 0: Error interrupt enable.

Allowed values:
0: Disabled: Error interrupt disabled
1: Enabled: Error interrupt enabled

IREN

Bit 1: IrDA mode enable.

Allowed values:
0: Disabled: IrDA disabled
1: Enabled: IrDA enabled

IRLP

Bit 2: IrDA low-power.

Allowed values:
0: Normal: Normal mode
1: LowPower: Low-power mode

HDSEL

Bit 3: Half-duplex selection.

Allowed values:
0: FullDuplex: Half duplex mode is not selected
1: HalfDuplex: Half duplex mode is selected

NACK

Bit 4: Smartcard NACK enable.

Allowed values:
0: Disabled: NACK transmission in case of parity error is disabled
1: Enabled: NACK transmission during parity error is enabled

SCEN

Bit 5: Smartcard mode enable.

Allowed values:
0: Disabled: Smartcard mode disabled
1: Enabled: Smartcard mode enabled

DMAR

Bit 6: DMA enable receiver.

Allowed values:
0: Disabled: DMA mode is disabled for reception
1: Enabled: DMA mode is enabled for reception

DMAT

Bit 7: DMA enable transmitter.

Allowed values:
0: Disabled: DMA mode is disabled for transmission
1: Enabled: DMA mode is enabled for transmission

RTSE

Bit 8: RTS enable.

Allowed values:
0: Disabled: RTS hardware flow control disabled
1: Enabled: RTS hardware flow control enabled

CTSE

Bit 9: CTS enable.

Allowed values:
0: Disabled: CTS hardware flow control disabled
1: Enabled: CTS hardware flow control enabled

CTSIE

Bit 10: CTS interrupt enable.

Allowed values:
0: Disabled: CTS interrupt disabled
1: Enabled: CTS interrupt enabled

GTPR

Guard time and prescaler register

Offset: 0x18, reset: 0x0000, access: read-write

0/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
GT
rw
PSC
rw
Toggle Fields.

PSC

Bits 0-7: Prescaler value.

GT

Bits 8-15: Guard time value.

USART2

0x40004400: Universal synchronous asynchronous receiver transmitter

42/49 fields covered. Toggle Registers.

SR

Status register

Offset: 0x0, reset: 0x00C0, access: Unspecified

6/10 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CTS
rw
LBD
rw
TXE
r
TC
rw
RXNE
rw
IDLE
r
ORE
r
NE
r
FE
r
PE
r
Toggle Fields.

PE

Bit 0: Parity error.

FE

Bit 1: Framing error.

NE

Bit 2: Noise error flag.

ORE

Bit 3: Overrun error.

IDLE

Bit 4: IDLE line detected.

RXNE

Bit 5: Read data register not empty.

TC

Bit 6: Transmission complete.

TXE

Bit 7: Transmit data register empty.

LBD

Bit 8: LIN break detection flag.

CTS

Bit 9: CTS flag.

DR

Data register

Offset: 0x4, reset: 0x00000000, access: read-write

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DR
rw
Toggle Fields.

DR

Bits 0-8: Data value.

Allowed values: 0-511

BRR

Baud rate register

Offset: 0x8, reset: 0x0000, access: read-write

2/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DIV_Mantissa
rw
DIV_Fraction
rw
Toggle Fields.

DIV_Fraction

Bits 0-3: fraction of USARTDIV.

Allowed values: 0-15

DIV_Mantissa

Bits 4-15: mantissa of USARTDIV.

Allowed values: 0-4095

CR1

Control register 1

Offset: 0xC, reset: 0x0000, access: read-write

14/14 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
UE
rw
M
rw
WAKE
rw
PCE
rw
PS
rw
PEIE
rw
TXEIE
rw
TCIE
rw
RXNEIE
rw
IDLEIE
rw
TE
rw
RE
rw
RWU
rw
SBK
rw
Toggle Fields.

SBK

Bit 0: Send break.

Allowed values:
0: NoBreak: No break character is transmitted
1: Break: Break character transmitted

RWU

Bit 1: Receiver wakeup.

Allowed values:
0: Active: Receiver in active mode
1: Mute: Receiver in mute mode

RE

Bit 2: Receiver enable.

Allowed values:
0: Disabled: Receiver disabled
1: Enabled: Receiver enabled

TE

Bit 3: Transmitter enable.

Allowed values:
0: Disabled: Transmitter disabled
1: Enabled: Transmitter enabled

IDLEIE

Bit 4: IDLE interrupt enable.

Allowed values:
0: Disabled: IDLE interrupt disabled
1: Enabled: IDLE interrupt enabled

RXNEIE

Bit 5: RXNE interrupt enable.

Allowed values:
0: Disabled: RXNE interrupt disabled
1: Enabled: RXNE interrupt enabled

TCIE

Bit 6: Transmission complete interrupt enable.

Allowed values:
0: Disabled: TC interrupt disabled
1: Enabled: TC interrupt enabled

TXEIE

Bit 7: TXE interrupt enable.

Allowed values:
0: Disabled: TXE interrupt disabled
1: Enabled: TXE interrupt enabled

PEIE

Bit 8: PE interrupt enable.

Allowed values:
0: Disabled: PE interrupt disabled
1: Enabled: PE interrupt enabled

PS

Bit 9: Parity selection.

Allowed values:
0: Even: Even parity
1: Odd: Odd parity

PCE

Bit 10: Parity control enable.

Allowed values:
0: Disabled: Parity control disabled
1: Enabled: Parity control enabled

WAKE

Bit 11: Wakeup method.

Allowed values:
0: IdleLine: USART wakeup on idle line
1: AddressMark: USART wakeup on address mark

M

Bit 12: Word length.

Allowed values:
0: M8: 8 data bits
1: M9: 9 data bits

UE

Bit 13: USART enable.

Allowed values:
0: Disabled: USART prescaler and outputs disabled
1: Enabled: USART enabled

CR2

Control register 2

Offset: 0x10, reset: 0x0000, access: read-write

8/9 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LINEN
rw
STOP
rw
CLKEN
rw
CPOL
rw
CPHA
rw
LBCL
rw
LBDIE
rw
LBDL
rw
ADD
rw
Toggle Fields.

ADD

Bits 0-3: Address of the USART node.

Allowed values: 0-15

LBDL

Bit 5: lin break detection length.

Allowed values:
0: LBDL10: 10-bit break detection
1: LBDL11: 11-bit break detection

LBDIE

Bit 6: LIN break detection interrupt enable.

Allowed values:
0: Disabled: LIN break detection interrupt disabled
1: Enabled: LIN break detection interrupt enabled

LBCL

Bit 8: Last bit clock pulse.

CPHA

Bit 9: Clock phase.

Allowed values:
0: First: The first clock transition is the first data capture edge
1: Second: The second clock transition is the first data capture edge

CPOL

Bit 10: Clock polarity.

Allowed values:
0: Low: Steady low value on CK pin outside transmission window
1: High: Steady high value on CK pin outside transmission window

CLKEN

Bit 11: Clock enable.

Allowed values:
0: Disabled: CK pin disabled
1: Enabled: CK pin enabled

STOP

Bits 12-13: STOP bits.

Allowed values:
0: Stop1: 1 stop bit
1: Stop0p5: 0.5 stop bits
2: Stop2: 2 stop bits
3: Stop1p5: 1.5 stop bits

LINEN

Bit 14: LIN mode enable.

Allowed values:
0: Disabled: LIN mode disabled
1: Enabled: LIN mode enabled

CR3

Control register 3

Offset: 0x14, reset: 0x0000, access: read-write

11/11 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CTSIE
rw
CTSE
rw
RTSE
rw
DMAT
rw
DMAR
rw
SCEN
rw
NACK
rw
HDSEL
rw
IRLP
rw
IREN
rw
EIE
rw
Toggle Fields.

EIE

Bit 0: Error interrupt enable.

Allowed values:
0: Disabled: Error interrupt disabled
1: Enabled: Error interrupt enabled

IREN

Bit 1: IrDA mode enable.

Allowed values:
0: Disabled: IrDA disabled
1: Enabled: IrDA enabled

IRLP

Bit 2: IrDA low-power.

Allowed values:
0: Normal: Normal mode
1: LowPower: Low-power mode

HDSEL

Bit 3: Half-duplex selection.

Allowed values:
0: FullDuplex: Half duplex mode is not selected
1: HalfDuplex: Half duplex mode is selected

NACK

Bit 4: Smartcard NACK enable.

Allowed values:
0: Disabled: NACK transmission in case of parity error is disabled
1: Enabled: NACK transmission during parity error is enabled

SCEN

Bit 5: Smartcard mode enable.

Allowed values:
0: Disabled: Smartcard mode disabled
1: Enabled: Smartcard mode enabled

DMAR

Bit 6: DMA enable receiver.

Allowed values:
0: Disabled: DMA mode is disabled for reception
1: Enabled: DMA mode is enabled for reception

DMAT

Bit 7: DMA enable transmitter.

Allowed values:
0: Disabled: DMA mode is disabled for transmission
1: Enabled: DMA mode is enabled for transmission

RTSE

Bit 8: RTS enable.

Allowed values:
0: Disabled: RTS hardware flow control disabled
1: Enabled: RTS hardware flow control enabled

CTSE

Bit 9: CTS enable.

Allowed values:
0: Disabled: CTS hardware flow control disabled
1: Enabled: CTS hardware flow control enabled

CTSIE

Bit 10: CTS interrupt enable.

Allowed values:
0: Disabled: CTS interrupt disabled
1: Enabled: CTS interrupt enabled

GTPR

Guard time and prescaler register

Offset: 0x18, reset: 0x0000, access: read-write

0/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
GT
rw
PSC
rw
Toggle Fields.

PSC

Bits 0-7: Prescaler value.

GT

Bits 8-15: Guard time value.

USART3

0x40004800: Universal synchronous asynchronous receiver transmitter

42/49 fields covered. Toggle Registers.

SR

Status register

Offset: 0x0, reset: 0x00C0, access: Unspecified

6/10 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CTS
rw
LBD
rw
TXE
r
TC
rw
RXNE
rw
IDLE
r
ORE
r
NE
r
FE
r
PE
r
Toggle Fields.

PE

Bit 0: Parity error.

FE

Bit 1: Framing error.

NE

Bit 2: Noise error flag.

ORE

Bit 3: Overrun error.

IDLE

Bit 4: IDLE line detected.

RXNE

Bit 5: Read data register not empty.

TC

Bit 6: Transmission complete.

TXE

Bit 7: Transmit data register empty.

LBD

Bit 8: LIN break detection flag.

CTS

Bit 9: CTS flag.

DR

Data register

Offset: 0x4, reset: 0x00000000, access: read-write

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DR
rw
Toggle Fields.

DR

Bits 0-8: Data value.

Allowed values: 0-511

BRR

Baud rate register

Offset: 0x8, reset: 0x0000, access: read-write

2/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DIV_Mantissa
rw
DIV_Fraction
rw
Toggle Fields.

DIV_Fraction

Bits 0-3: fraction of USARTDIV.

Allowed values: 0-15

DIV_Mantissa

Bits 4-15: mantissa of USARTDIV.

Allowed values: 0-4095

CR1

Control register 1

Offset: 0xC, reset: 0x0000, access: read-write

14/14 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
UE
rw
M
rw
WAKE
rw
PCE
rw
PS
rw
PEIE
rw
TXEIE
rw
TCIE
rw
RXNEIE
rw
IDLEIE
rw
TE
rw
RE
rw
RWU
rw
SBK
rw
Toggle Fields.

SBK

Bit 0: Send break.

Allowed values:
0: NoBreak: No break character is transmitted
1: Break: Break character transmitted

RWU

Bit 1: Receiver wakeup.

Allowed values:
0: Active: Receiver in active mode
1: Mute: Receiver in mute mode

RE

Bit 2: Receiver enable.

Allowed values:
0: Disabled: Receiver disabled
1: Enabled: Receiver enabled

TE

Bit 3: Transmitter enable.

Allowed values:
0: Disabled: Transmitter disabled
1: Enabled: Transmitter enabled

IDLEIE

Bit 4: IDLE interrupt enable.

Allowed values:
0: Disabled: IDLE interrupt disabled
1: Enabled: IDLE interrupt enabled

RXNEIE

Bit 5: RXNE interrupt enable.

Allowed values:
0: Disabled: RXNE interrupt disabled
1: Enabled: RXNE interrupt enabled

TCIE

Bit 6: Transmission complete interrupt enable.

Allowed values:
0: Disabled: TC interrupt disabled
1: Enabled: TC interrupt enabled

TXEIE

Bit 7: TXE interrupt enable.

Allowed values:
0: Disabled: TXE interrupt disabled
1: Enabled: TXE interrupt enabled

PEIE

Bit 8: PE interrupt enable.

Allowed values:
0: Disabled: PE interrupt disabled
1: Enabled: PE interrupt enabled

PS

Bit 9: Parity selection.

Allowed values:
0: Even: Even parity
1: Odd: Odd parity

PCE

Bit 10: Parity control enable.

Allowed values:
0: Disabled: Parity control disabled
1: Enabled: Parity control enabled

WAKE

Bit 11: Wakeup method.

Allowed values:
0: IdleLine: USART wakeup on idle line
1: AddressMark: USART wakeup on address mark

M

Bit 12: Word length.

Allowed values:
0: M8: 8 data bits
1: M9: 9 data bits

UE

Bit 13: USART enable.

Allowed values:
0: Disabled: USART prescaler and outputs disabled
1: Enabled: USART enabled

CR2

Control register 2

Offset: 0x10, reset: 0x0000, access: read-write

8/9 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LINEN
rw
STOP
rw
CLKEN
rw
CPOL
rw
CPHA
rw
LBCL
rw
LBDIE
rw
LBDL
rw
ADD
rw
Toggle Fields.

ADD

Bits 0-3: Address of the USART node.

Allowed values: 0-15

LBDL

Bit 5: lin break detection length.

Allowed values:
0: LBDL10: 10-bit break detection
1: LBDL11: 11-bit break detection

LBDIE

Bit 6: LIN break detection interrupt enable.

Allowed values:
0: Disabled: LIN break detection interrupt disabled
1: Enabled: LIN break detection interrupt enabled

LBCL

Bit 8: Last bit clock pulse.

CPHA

Bit 9: Clock phase.

Allowed values:
0: First: The first clock transition is the first data capture edge
1: Second: The second clock transition is the first data capture edge

CPOL

Bit 10: Clock polarity.

Allowed values:
0: Low: Steady low value on CK pin outside transmission window
1: High: Steady high value on CK pin outside transmission window

CLKEN

Bit 11: Clock enable.

Allowed values:
0: Disabled: CK pin disabled
1: Enabled: CK pin enabled

STOP

Bits 12-13: STOP bits.

Allowed values:
0: Stop1: 1 stop bit
1: Stop0p5: 0.5 stop bits
2: Stop2: 2 stop bits
3: Stop1p5: 1.5 stop bits

LINEN

Bit 14: LIN mode enable.

Allowed values:
0: Disabled: LIN mode disabled
1: Enabled: LIN mode enabled

CR3

Control register 3

Offset: 0x14, reset: 0x0000, access: read-write

11/11 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CTSIE
rw
CTSE
rw
RTSE
rw
DMAT
rw
DMAR
rw
SCEN
rw
NACK
rw
HDSEL
rw
IRLP
rw
IREN
rw
EIE
rw
Toggle Fields.

EIE

Bit 0: Error interrupt enable.

Allowed values:
0: Disabled: Error interrupt disabled
1: Enabled: Error interrupt enabled

IREN

Bit 1: IrDA mode enable.

Allowed values:
0: Disabled: IrDA disabled
1: Enabled: IrDA enabled

IRLP

Bit 2: IrDA low-power.

Allowed values:
0: Normal: Normal mode
1: LowPower: Low-power mode

HDSEL

Bit 3: Half-duplex selection.

Allowed values:
0: FullDuplex: Half duplex mode is not selected
1: HalfDuplex: Half duplex mode is selected

NACK

Bit 4: Smartcard NACK enable.

Allowed values:
0: Disabled: NACK transmission in case of parity error is disabled
1: Enabled: NACK transmission during parity error is enabled

SCEN

Bit 5: Smartcard mode enable.

Allowed values:
0: Disabled: Smartcard mode disabled
1: Enabled: Smartcard mode enabled

DMAR

Bit 6: DMA enable receiver.

Allowed values:
0: Disabled: DMA mode is disabled for reception
1: Enabled: DMA mode is enabled for reception

DMAT

Bit 7: DMA enable transmitter.

Allowed values:
0: Disabled: DMA mode is disabled for transmission
1: Enabled: DMA mode is enabled for transmission

RTSE

Bit 8: RTS enable.

Allowed values:
0: Disabled: RTS hardware flow control disabled
1: Enabled: RTS hardware flow control enabled

CTSE

Bit 9: CTS enable.

Allowed values:
0: Disabled: CTS hardware flow control disabled
1: Enabled: CTS hardware flow control enabled

CTSIE

Bit 10: CTS interrupt enable.

Allowed values:
0: Disabled: CTS interrupt disabled
1: Enabled: CTS interrupt enabled

GTPR

Guard time and prescaler register

Offset: 0x18, reset: 0x0000, access: read-write

0/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
GT
rw
PSC
rw
Toggle Fields.

PSC

Bits 0-7: Prescaler value.

GT

Bits 8-15: Guard time value.

USB

0x40005C00: Universal serial bus full-speed device interface

35/41 fields covered. Toggle Registers.

EP%sR

endpoint 0 register

Offset: 0x0, reset: 0x00000000, access: read-write

4/10 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CTR_RX
rw
DTOG_RX
rw
STAT_RX
rw
SETUP
rw
EP_TYPE
rw
EP_KIND
rw
CTR_TX
rw
DTOG_TX
rw
STAT_TX
rw
EA
rw
Toggle Fields.

EA

Bits 0-3: Endpoint address.

Allowed values: 0-15

STAT_TX

Bits 4-5: Status bits, for transmission transfers.

Allowed values:
0: Disabled: all transmission requests addressed to this endpoint are ignored
1: Stall: the endpoint is stalled and all transmission requests result in a STALL handshake
2: Nak: the endpoint is naked and all transmission requests result in a NAK handshake
3: Valid: this endpoint is enabled for transmission

DTOG_TX

Bit 6: Data Toggle, for transmission transfers.

CTR_TX

Bit 7: Correct Transfer for transmission.

EP_KIND

Bit 8: Endpoint kind.

EP_TYPE

Bits 9-10: Endpoint type.

Allowed values:
0: Bulk: Bulk endpoint
1: Control: Control endpoint
2: Iso: Iso endpoint
3: Interrupt: Interrupt endpoint

SETUP

Bit 11: Setup transaction completed.

STAT_RX

Bits 12-13: Status bits, for reception transfers.

Allowed values:
0: Disabled: all reception requests addressed to this endpoint are ignored
1: Stall: the endpoint is stalled and all reception requests result in a STALL handshake
2: Nak: the endpoint is naked and all reception requests result in a NAK handshake
3: Valid: this endpoint is enabled for reception

DTOG_RX

Bit 14: Data Toggle, for reception transfers.

CTR_RX

Bit 15: Correct transfer for reception.

CNTR

control register

Offset: 0x40, reset: 0x00000003, access: read-write

13/13 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CTRM
rw
PMAOVRM
rw
ERRM
rw
WKUPM
rw
SUSPM
rw
RESETM
rw
SOFM
rw
ESOFM
rw
RESUME
rw
FSUSP
rw
LPMODE
rw
PDWN
rw
FRES
rw
Toggle Fields.

FRES

Bit 0: Force USB Reset.

Allowed values:
0: NoReset: Clear USB reset
1: Reset: Force a reset of the USB peripheral, exactly like a RESET signaling on the USB

PDWN

Bit 1: Power down.

Allowed values:
0: Disabled: No power down
1: Enabled: Enter power down mode

LPMODE

Bit 2: Low-power mode.

Allowed values:
0: Disabled: No low-power mode
1: Enabled: Enter low-power mode

FSUSP

Bit 3: Force suspend.

Allowed values:
0: NoEffect: No effect
1: Suspend: Enter suspend mode. Clocks and static power dissipation in the analog transceiver are left unaffected

RESUME

Bit 4: Resume request.

Allowed values:
1: Requested: Resume requested

ESOFM

Bit 8: Expected start of frame interrupt mask.

Allowed values:
0: Disabled: ESOF Interrupt disabled
1: Enabled: ESOF Interrupt enabled, an interrupt request is generated when the corresponding bit in the USB_ISTR register is set

SOFM

Bit 9: Start of frame interrupt mask.

Allowed values:
0: Disabled: SOF Interrupt disabled
1: Enabled: SOF Interrupt enabled, an interrupt request is generated when the corresponding bit in the USB_ISTR register is set

RESETM

Bit 10: USB reset interrupt mask.

Allowed values:
0: Disabled: RESET Interrupt disabled
1: Enabled: RESET Interrupt enabled, an interrupt request is generated when the corresponding bit in the USB_ISTR register is set

SUSPM

Bit 11: Suspend mode interrupt mask.

Allowed values:
0: Disabled: Suspend Mode Request SUSP Interrupt disabled
1: Enabled: SUSP Interrupt enabled, an interrupt request is generated when the corresponding bit in the USB_ISTR register is set

WKUPM

Bit 12: Wakeup interrupt mask.

Allowed values:
0: Disabled: WKUP Interrupt disabled
1: Enabled: WKUP Interrupt enabled, an interrupt request is generated when the corresponding bit in the USB_ISTR register is set

ERRM

Bit 13: Error interrupt mask.

Allowed values:
0: Disabled: ERR Interrupt disabled
1: Enabled: ERR Interrupt enabled, an interrupt request is generated when the corresponding bit in the USB_ISTR register is set

PMAOVRM

Bit 14: Packet memory area over / underrun interrupt mask.

Allowed values:
0: Disabled: PMAOVR Interrupt disabled
1: Enabled: PMAOVR Interrupt enabled, an interrupt request is generated when the corresponding bit in the USB_ISTR register is set

CTRM

Bit 15: Correct transfer interrupt mask.

Allowed values:
0: Disabled: Correct Transfer (CTR) Interrupt disabled
1: Enabled: CTR Interrupt enabled, an interrupt request is generated when the corresponding bit in the USB_ISTR register is set

ISTR

interrupt status register

Offset: 0x44, reset: 0x00000000, access: read-write

10/10 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CTR
rw
PMAOVR
rw
ERR
rw
WKUP
rw
SUSP
rw
RESET
rw
SOF
rw
ESOF
rw
DIR
rw
EP_ID
rw
Toggle Fields.

EP_ID

Bits 0-3: Endpoint Identifier.

Allowed values: 0-15

DIR

Bit 4: Direction of transaction.

Allowed values:
0: To: data transmitted by the USB peripheral to the host PC
1: From: data received by the USB peripheral from the host PC

ESOF

Bit 8: Expected start frame.

Allowed values:
1: ExpectedStartOfFrame: an SOF packet is expected but not received

SOF

Bit 9: start of frame.

Allowed values:
1: StartOfFrame: beginning of a new USB frame and it is set when a SOF packet arrives through the USB bus

RESET

Bit 10: reset request.

Allowed values:
1: Reset: peripheral detects an active USB RESET signal at its inputs

SUSP

Bit 11: Suspend mode request.

Allowed values:
1: Suspend: no traffic has been received for 3 ms, indicating a suspend mode request from the USB bus

WKUP

Bit 12: Wakeup.

Allowed values:
1: Wakeup: activity is detected that wakes up the USB peripheral

ERR

Bit 13: Error.

Allowed values:
1: Error: One of No ANSwer, Cyclic Redundancy Check, Bit Stuffing or Framing format Violation error occurred

PMAOVR

Bit 14: Packet memory area over / underrun.

Allowed values:
1: Overrun: microcontroller has not been able to respond in time to an USB memory request

CTR

Bit 15: Correct transfer.

Allowed values:
1: Completed: endpoint has successfully completed a transaction

FNR

frame number register

Offset: 0x48, reset: 0x0000, access: read-only

5/5 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RXDP
r
RXDM
r
LCK
r
LSOF
r
FN
r
Toggle Fields.

FN

Bits 0-10: Frame number.

Allowed values: 0-2047

LSOF

Bits 11-12: Lost SOF.

Allowed values: 0-3

LCK

Bit 13: Locked.

Allowed values:
1: Locked: the frame timer remains in this state until an USB reset or USB suspend event occurs

RXDM

Bit 14: Receive data - line status.

Allowed values:
1: Received: received data minus upstream port data line

RXDP

Bit 15: Receive data + line status.

Allowed values:
1: Received: received data plus upstream port data line

DADDR

device address

Offset: 0x4C, reset: 0x0000, access: read-write

2/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
EF
rw
ADD
rw
Toggle Fields.

ADD

Bits 0-6: Device address.

Allowed values: 0-127

EF

Bit 7: Enable function.

Allowed values:
0: Disabled: USB device disabled
1: Enabled: USB device enabled

BTABLE

Buffer table address

Offset: 0x50, reset: 0x0000, access: read-write

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
BTABLE
rw
Toggle Fields.

BTABLE

Bits 3-15: Buffer table.

Allowed values: 0-8191

WWDG

0x40002C00: Window watchdog

6/6 fields covered. Toggle Registers.

CR

Control register (WWDG_CR)

Offset: 0x0, reset: 0x0000007F, access: read-write

2/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
WDGA
rw
T
rw
Toggle Fields.

T

Bits 0-6: 7-bit counter (MSB to LSB).

Allowed values: 0-127

WDGA

Bit 7: Activation bit.

Allowed values:
0: Disabled: Watchdog disabled
1: Enabled: Watchdog enabled

CFR

Configuration register (WWDG_CFR)

Offset: 0x4, reset: 0x0000007F, access: read-write

3/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
EWI
rw
WDGTB
rw
W
rw
Toggle Fields.

W

Bits 0-6: 7-bit window value.

Allowed values: 0-127

WDGTB

Bits 7-8: Timer Base.

Allowed values:
0: Div1: Counter clock (PCLK1 div 4096) div 1
1: Div2: Counter clock (PCLK1 div 4096) div 2
2: Div4: Counter clock (PCLK1 div 4096) div 4
3: Div8: Counter clock (PCLK1 div 4096) div 8

EWI

Bit 9: Early Wakeup Interrupt.

Allowed values:
1: Enable: interrupt occurs whenever the counter reaches the value 0x40

SR

Status register (WWDG_SR)

Offset: 0x8, reset: 0x00000000, access: read-write

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
EWIF
rw
Toggle Fields.

EWIF

Bit 0: Early Wakeup Interrupt.

Allowed values:
1: Pending: The EWI Interrupt Service Routine has been triggered
0: Finished: The EWI Interrupt Service Routine has been serviced